Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
1124 commits 42 branches 14 tags 31 MiB
Commit graph

246 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
9c7ad6b05b fhdl: RenameClockDomains decorator 2013-07-26 15:42:14 +02:00
Sebastien Bourdeauducq
cec8fc4ca4 fhdl/specials/Instance: fix item sorting 2013-07-26 14:00:29 +02:00
Sebastien Bourdeauducq
b96eb339af fhdl: compact Instance syntax 2013-07-25 20:34:19 +02:00
Sebastien Bourdeauducq
b7ed19c6c5 fhdl: do not export Fragment 2013-07-25 18:52:54 +02:00
Sebastien Bourdeauducq
b367932498 fhdl: introduce module decorators 2013-07-25 17:56:31 +02:00
Sebastien Bourdeauducq
411e6ec114 fhdl/tools: do not export resort_statements 2013-07-17 16:50:09 +02:00
Sebastien Bourdeauducq
d5d2e64dc3 Revert "fhdl/tools/group_by_target: remove resort_statements" 
This reverts commit 939f01cee2.
 2013-07-17 16:49:26 +02:00
Sebastien Bourdeauducq
939f01cee2 fhdl/tools/group_by_target: remove resort_statements 2013-07-17 10:38:39 +02:00
David Carne
16ebe41028 fhdl/tools: BUGFIX: fix group_by_target grouping 
group_by_target does not properly combine target groups if statements
are presented in the order:

 ({A}, statement1)
 ({B}, statement2)
 ({A, B}, statement3)

which returns groups:

 ({A, B}, [statement1, statement3])
 ({B}, [statement2])

This patch fixes group_by_target such that the resulting group is:

 ({A, B}, [statement1, statement2, statement3])
 2013-07-17 10:14:39 +02:00
David Carne
faa8b7c49a fhdl/tools: clock domain merging for clock renaming 2013-07-16 18:17:44 +02:00
Sebastien Bourdeauducq
04efee7847 fhdl: mark variable as deprecated 2013-06-30 20:14:20 +02:00
Sebastien Bourdeauducq
71b89e4c46 fhdl/verilog: lower complex slices before reset insertion 2013-06-30 14:32:47 +02:00
Sebastien Bourdeauducq
ded5e569eb fhdl/tools: separate complex slice lowerer from basic lowerer 2013-06-30 14:32:19 +02:00
Robert Jördens
a255296171 support re-slicing and non-unit step size 
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
 2013-06-30 14:03:34 +02:00
Sebastien Bourdeauducq
080afdc3f9 fhdl/verilog: fix signedness rules for comparison 2013-06-26 22:45:47 +02:00
Sebastien Bourdeauducq
b56cb3cefc fhdl/verilog: improve error reporting 2013-06-24 19:44:25 +02:00
Sebastien Bourdeauducq
f0b0942055 bitreverse: fhdl/tools -> genlib/misc 2013-05-30 18:44:37 +02:00
Sebastien Bourdeauducq
bac62a32a9 Make memory ports part of specials 
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
 2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq
70ffe86356 New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq
f202946717 fhdl/tools/_TargetLister: do not include array keys in targets 2013-05-11 17:28:41 +02:00
Sebastien Bourdeauducq
b862b070d6 fhdl/verilog: recursive Special lowering 2013-04-25 14:56:26 +02:00
Sebastien Bourdeauducq
fee228a09f fhdl/specials/memory: do not write address register for async reads 2013-04-25 13:30:05 +02:00
Florent Kermarrec
f599fe4ade Support for resetless clock domains 2013-04-23 11:54:05 +02:00
Sebastien Bourdeauducq
ea63389823 fhdl: support len() on all values 2013-04-14 13:50:26 +02:00
Sebastien Bourdeauducq
75d33a0c05 fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec) 2013-04-11 18:55:49 +02:00
Sebastien Bourdeauducq
4c9018ea17 fhdl/visit: add TransformModule 2013-04-10 23:42:14 +02:00
Sebastien Bourdeauducq
633e5e6747 fhdl/module/finalize: pass additional args to do_finalize 2013-03-30 11:29:46 +01:00
Sebastien Bourdeauducq
574becc1fc fhdl/specials: clean up clock domain handling 2013-03-26 11:58:34 +01:00
Sebastien Bourdeauducq
ca431fc7c2 fhdl/module: support clock domain remapping of submodules 2013-03-22 18:17:54 +01:00
Sebastien Bourdeauducq
17f2b17654 fhdl/verilog: optionally disable clock domain creation 2013-03-18 18:45:19 +01:00
Sebastien Bourdeauducq
7a06e9457c Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
Sebastien Bourdeauducq
dc55289323 fhdl/tools/_ArrayLowerer: complete support for arrays as targets 2013-03-18 14:38:01 +01:00
Sebastien Bourdeauducq
e95d2f4779 fhdl/tools/value_bits_sign: support not 2013-03-18 09:52:43 +01:00
Sebastien Bourdeauducq
b6fe3ace05 fhdl/structure: style fix 2013-03-17 15:33:38 +01:00
Sébastien Bourdeauducq
2a4cc3875c Merge pull request #6 from larsclausen/master 
Minor improvements
 2013-03-17 07:33:14 -07:00
Sebastien Bourdeauducq
7b49fd9386 fhdl/specials: fix rename_clock_domain declarations 2013-03-15 19:47:01 +01:00
Sebastien Bourdeauducq
dd0f3311cd structure: remove Fragment.call_sim 2013-03-15 19:15:48 +01:00
Sebastien Bourdeauducq
bd8bbd9305 Make ClockDomains part of fragments 2013-03-15 18:17:33 +01:00
Lars-Peter Clausen
72579a6129 Add support for negative slice indices 
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].

Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
	reg.eq(Cat(Replicate(0, n), reg[-n:])

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2013-03-12 21:56:01 +01:00
Sebastien Bourdeauducq
ecfe1646ec fhdl/verilog: implicit get_fragment 2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq
4ada2ead05 fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq
04df076fba bank: automatic register naming 2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq
7e2581bf17 fhdl/tracer: recognize CALL_FUNCTION_VAR opcode 2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq
12158ceadf fhdl/tracer: recognize LOAD_DEREF opcode 2013-03-12 10:31:56 +01:00
Sebastien Bourdeauducq
3c75121783 fhdl/tracer: remove leading underscores from names 2013-03-11 22:21:58 +01:00
Sebastien Bourdeauducq
17e0dfe120 fhdl/module: replace autofragment 2013-03-10 19:27:55 +01:00
Sebastien Bourdeauducq
d0676e2dd1 migen/fhdl/autofragment: factorize 2013-03-09 23:23:24 +01:00
Sebastien Bourdeauducq
d0d2df3c4b fhdl/autofragment: remove legacy functions 2013-03-09 23:05:45 +01:00
Sebastien Bourdeauducq
72fb6fd6bd fhdl/tools/flat_iteration: generalize 2013-03-09 23:03:15 +01:00
Sebastien Bourdeauducq
f53acb92e7 fhdl/autofragment: fix submodules 2013-03-09 21:15:38 +01:00
Sebastien Bourdeauducq
6da8eb906f fhdl/autofragment: empty build_fragment by default 2013-03-09 19:10:47 +01:00
Sebastien Bourdeauducq
2b8dc52c13 Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq
6fa30053bf fhdl/verilog: tristate outputs are always wire 2013-03-06 11:30:52 +01:00
Sebastien Bourdeauducq
bb5ee8d3bd fhdl/autofragment: bugfixes + add auto_attr 2013-03-03 17:53:06 +01:00
Sebastien Bourdeauducq
cc8118d35c fhdl/autofragment: FModule 2013-03-02 23:30:54 +01:00
Sebastien Bourdeauducq
c10622f5e2 fhdl/verilog: insert reset before listing signals 2013-02-27 18:10:04 +01:00
Sebastien Bourdeauducq
a81781f589 fhdl/specials: allow setting memory name 2013-02-25 23:14:03 +01:00
Sebastien Bourdeauducq
55ab01f928 fhdl/specials/Instance: _printintbool -> verilog_printexpr 2013-02-24 13:08:01 +01:00
Sebastien Bourdeauducq
7c4e6c35e5 fhdl/verilog: support special lowering and overrides 2013-02-23 19:03:16 +01:00
Sebastien Bourdeauducq
38664d6e16 fhdl: inline synthesis directive support 2013-02-22 19:10:02 +01:00
Sebastien Bourdeauducq
49cfba50fa New 'specials' API 2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq
1b18194b1d fhdl: TSTriple 2013-02-19 17:26:02 +01:00
Sebastien Bourdeauducq
dc93a231c6 fhdl: tristate support 2013-02-15 00:17:24 +01:00
Sebastien Bourdeauducq
63d399b6ad fhdl/autofragment: from_attributes 2013-02-11 18:34:01 +01:00
Sebastien Bourdeauducq
473fd20f8c fhdl/structure: store clock domain name 2013-01-24 13:49:49 +01:00
Sebastien Bourdeauducq
3201554f76 fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert() 2013-01-23 15:13:06 +01:00
Sebastien Bourdeauducq
badba89686 fhdl: support nested statement lists 2013-01-05 14:18:15 +01:00
Sebastien Bourdeauducq
3fae6c8f03 Do not use super() 2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq
b06fbdedd6 fhdl/tools: bitreverse 2012-12-14 23:56:16 +01:00
Sebastien Bourdeauducq
483b821342 fhdl/structure: do not create Signal in Instance when parameter is int 2012-12-06 20:56:46 +01:00
Sebastien Bourdeauducq
70e97e0456 Fix various errors from new bitwidth/signedness system conversion 2012-11-29 23:36:55 +01:00
Sebastien Bourdeauducq
261166d92b fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style) 
See http://jandecaluwe.com/hdldesign/counting.html
 2012-11-29 22:59:54 +01:00
Sebastien Bourdeauducq
55d143a454 fhdl/structure: add unary minus 2012-11-29 22:52:57 +01:00
Sebastien Bourdeauducq
50ed73c937 New specification for width and signedness 2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq
6eebfce44a Refactor Case 2012-11-29 01:11:15 +01:00
Sebastien Bourdeauducq
fee22a4631 Remove Constant 2012-11-28 23:18:43 +01:00
Sebastien Bourdeauducq
59831e0485 fhdl/structure: improved bits_for function 2012-11-28 18:39:44 +01:00
Sebastien Bourdeauducq
11b1e53224 visit/NodeTransformer: copy most nodes 2012-11-28 17:50:55 +01:00
Sebastien Bourdeauducq
a2bcbfdf8f fhdl/tools: use NodeTransformer to lower arrays 2012-11-28 17:46:15 +01:00
Sebastien Bourdeauducq
3bc15024ac fhdl/tools: use NodeVisitor 2012-11-26 21:40:23 +01:00
Sebastien Bourdeauducq
1460f069f6 fhdl/structure: remove deprecated MemoryPort 2012-11-26 19:36:43 +01:00
Sebastien Bourdeauducq
27d87c9412 fhdl/structure: disable we_granularity when larger than width 2012-11-23 23:08:12 +01:00
Sebastien Bourdeauducq
f42683b71e fhdl/structure/Memory: fix we width 2012-11-23 19:21:52 +01:00
Sebastien Bourdeauducq
0f6215a13a fhdl/structure: add Memory.get_port API 2012-11-23 19:17:49 +01:00
Sebastien Bourdeauducq
9d3e218863 fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs. 2012-11-23 18:38:03 +01:00
Sebastien Bourdeauducq
3971600917 fhdl/structure: use sets for memories and instance collections 2012-11-23 17:20:08 +01:00
Sebastien Bourdeauducq
51e2e6ecd0 fhdl/verilog: remove empty cases 2012-11-18 16:32:51 +01:00
Sebastien Bourdeauducq
26cf1b8840 fhdl: make constants hashable 2012-11-09 20:17:43 +01:00
Sebastien Bourdeauducq
7744655ef2 fhdl/visit: add missing self 2012-11-09 17:37:24 +01:00
Sebastien Bourdeauducq
13af0ce556 fhdl: visit module (untested) 2012-11-09 16:00:11 +01:00
Sebastien Bourdeauducq
56d4cdeb48 fhdl/structure: make all values hashable 2012-11-06 13:51:51 +01:00
Sebastien Bourdeauducq
8101b68965 fhdl: fix instance get_io 2012-09-28 18:02:03 +02:00
Sebastien Bourdeauducq
c273866b08 fhdl: support expressions in instance ports 2012-09-22 20:51:10 +02:00
Sebastien Bourdeauducq
2fc9cae88a fhdl: support inverted clock ports in instances 2012-09-22 20:50:49 +02:00
Sebastien Bourdeauducq
2e14569b5c fhdl/verilog: sort clock domains by name 2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq
9a18a9df3f fhdl: list signals in execution order 2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq
e16353a281 Multi-clock design support + new instance API 2012-09-10 23:45:02 +02:00
Sebastien Bourdeauducq
b45c9546eb fhdl/namer: better handling of indices 2012-09-09 19:33:55 +02:00
Sebastien Bourdeauducq
589251fffd fhdl/tracer: support BUILD_LIST opcode 2012-09-09 18:53:24 +02:00
Sebastien Bourdeauducq
910c350021 fhdl/namer: use execution order indices for variable names as well 2012-09-09 17:31:35 +02:00