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VexRiscv
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536 Commits

Author SHA1 Message Date
Charles Papon e7f3dd5553 Rework CsrPlugin exception delegation 2019-04-05 23:40:39 +02:00
Charles Papon ddf0f06834 Add more delegation tests 
Reduce dcache test duration
 2019-04-05 22:56:12 +02:00
Charles Papon acaa931e11 Rework CsrPlugin interrupt delegation 2019-04-05 22:55:42 +02:00
Charles Papon 9e72971ff0 Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin 
SUM was in fact already supported
 2019-04-05 21:34:44 +02:00
Charles Papon 82c894932a update todolist 2019-04-05 20:04:28 +02:00
Charles Papon aeb418a99e Add dcache tests 2019-04-05 20:03:22 +02:00
Charles Papon 5a6665e57f Fix DataCache flush on the last line 2019-04-05 20:02:57 +02:00
Charles Papon 8459d423b8 add icache flush test 2019-04-05 18:11:33 +02:00
Charles Papon 60a41bfc75 rework i$ flush 2019-04-05 18:11:10 +02:00
Charles Papon f5d4e745c7 Look like precise fence.i isn't required in practice 2019-04-05 18:08:25 +02:00
Charles Papon 446e9625af Centralised all todo in linux.scala 
Sorted out fence fence.i instruction in iBus/dBus plugins.
Fixed MMU permitions while in used mode and bypassing the MMU
 2019-04-05 12:17:29 +02:00
Charles Papon 888e1c0b8a Fix RVC instruction cache xtval allignement 2019-04-05 01:08:57 +02:00
Charles Papon 8e6010fd71 Got the debug plugin working with the linux config (had to disable CSR ebreak) 2019-04-05 00:25:27 +02:00
Charles Papon 4f0a02594c Change LR/SC to reserve the whole memory 
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
 2019-04-04 20:34:35 +02:00
Charles Papon f8b438d9dc cleaning 2019-04-04 12:59:08 +02:00
Charles Papon de1c9c6fea Removing D$ reports 2019-04-03 14:47:00 +02:00
Charles Papon 3f7a859e07 Got multiway I$ D$ running linux fine. 2019-04-03 14:33:35 +02:00
Charles Papon 922c18ee49 Add data cache flush feature 2019-04-03 15:56:58 +02:00
Charles Papon 066f562c5e Got the MMU refilling itself with datacache cached memory access instead of io accesses 2019-04-03 14:32:21 +02:00
Charles Papon 8be40e637b #60 Got the new data cache design passing all tests and running linux 2019-04-02 23:44:53 +02:00
Charles Papon fd4da77084 #60 Got the new instruction cache design passing the standard regressions 2019-04-02 00:26:53 +02:00
Charles Papon bc0af02c97 #60 Got instruction cache running linux :D 2019-04-01 11:59:04 +02:00
Charles Papon 1dff9aff8a #60 Fix interrupt causing fetch privilege issues 2019-04-01 10:47:54 +02:00
Charles Papon e74a5a71eb Better simulation console integration 2019-04-01 10:31:55 +02:00
Charles Papon 369a3d0f5f #60 Sync everything, added much comment on the top of Linux.scala to help reproduce 2019-03-31 23:43:56 +02:00
Charles Papon c7314cc606 Got buildroot login, userspace, commands working 
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
 2019-03-31 15:17:45 +02:00
Dolu1990 de500ad8f9 Add qemu command 2019-03-30 18:29:17 +01:00
Dolu1990 9383445e0b Add a qemu option (wip) 2019-03-30 18:26:44 +01:00
Charles Papon 1a36f2689d #60 Fix software model. Forgot physical address for on RVC instruction 2019-03-30 11:24:29 +01:00
Charles Papon 29980016f3 #60 Fix instruction fetch exception PC by forcing LSB to be zero 2019-03-30 10:10:25 +01:00
Dolu1990 9fff419346 Better fix 2019-03-29 09:18:44 +01:00
Dolu1990 391cff69d3 #60 should fix the first instruction fetch privilege after interrupt 2019-03-29 09:02:44 +01:00
Dolu1990 0c48729611 Sync impact less changes (asfar i know) 2019-03-29 08:43:15 +01:00
Dolu1990 9ac4998478 Fix emulator nested exception redirection privilege 2019-03-28 00:38:38 +01:00
Dolu1990 ac06111163 Fix MMU MPRV, Fix emulator nested exception 2019-03-27 22:58:30 +01:00
Dolu1990 0bed511a6c Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign 2019-03-27 18:58:02 +01:00
Dolu1990 43c3922a3d Add prerequired stuff 2019-03-27 10:55:20 +01:00
Dolu1990 f113946e66 Added a neutral LINUX_SOC for sim purposes 2019-03-27 10:53:41 +01:00
Dolu1990 b69c474fa2 #60 user space reached 
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
 2019-03-27 00:26:51 +01:00
Dolu1990 94fc2c3ecf Fix some models missmatch 
Add more SBI
Add hardware LR/SC support in dbus cacheless
 2019-03-26 01:25:18 +01:00
Dolu1990 1c3fd5c38b Fix mprv and add it into the softare model 2019-03-25 12:03:32 +01:00
Dolu1990 1ec11dc03d Fix mprv 2019-03-25 11:47:56 +01:00
Dolu1990 c34f5413a3 Add MMU MPRIV for easier machinemode emulation #60 2019-03-25 10:30:13 +01:00
Dolu1990 9d55283b3b Machine mode emulator 2019-03-25 02:00:19 +01:00
Dolu1990 e28702eb40 Add PlicCost test 2019-03-24 12:17:39 +01:00
Dolu1990 6c0608f0dd #60 
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
 2019-03-24 10:52:56 +01:00
Tom Verbeure ea62fd0e16 Same thing for DBusSimpleBus. 2019-03-23 23:36:13 +00:00
Tom Verbeure 95c3e436dc Make toPipelinedMemoryBus() just like the other busses 2019-03-23 22:32:48 +00:00
Dolu1990 0656a49332 Make xtval more compliant 2019-03-23 20:12:36 +01:00
Dolu1990 7159237104 Fix csrrs/csrrc for xip registers 2019-03-23 18:11:26 +01:00
Dolu1990 505bff6f45 CSR Plugin now implement interruptions as specified in the spec 2019-03-23 12:56:04 +01:00
Dolu1990 3652ede130 Add mdeleg tests 2019-03-23 11:41:10 +01:00
Dolu1990 9139b4d269 Restore all tests 2019-03-22 18:03:35 +01:00
Dolu1990 597336b491 MMU sum/mxr tested and ok, all seem finen 2019-03-22 17:11:55 +01:00
Dolu1990 f7b793b7bf Add SSTATUS.SUM/MXR feature, need testing 2019-03-22 15:49:36 +01:00
Dolu1990 e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990 2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990 af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Dolu1990 ea56481ead Add supervisor CSR in the riscv golden model 2019-03-20 23:26:08 +01:00
Dolu1990 7cbe399f1f Fix some supervisor CSR access 2019-03-20 23:25:52 +01:00
Dolu1990 6f2e5a0eb7 goldenmodel Implement some of the supervisor CSR 2019-03-20 20:28:04 +01:00
Dolu1990 39b2803914 Fix some CsrPlugin flags issues 2019-03-20 20:27:47 +01:00
Dolu1990 6c2fe934fd Bring changes and fixies from @kgugala @daveshah1. Thanks guys ! 2019-03-20 16:27:35 +01:00
Dolu1990 130a69eeae Pass regressions machinemode with CSR config including Supervisor 2019-03-20 14:14:59 +01:00
Dolu1990 d205f88fb8 riscv golden model and RTL pass all current regressions 
add RVC into the linux config
 2019-03-20 12:17:43 +01:00
Dolu1990 3c66f7c58a goldenmodel now pass more machine mode CSR tests 2019-03-20 11:46:27 +01:00
Dolu1990 ee402ec5dc clearning 2019-03-20 01:16:39 +01:00
Dolu1990 3a38fe4130 Add mmu regresion blank project 2019-03-20 01:13:05 +01:00
Dolu1990 ccc3b63d7c Enable golden model check for all regressions 
Need to implement missing CSR of the golden model
 2019-03-20 01:12:03 +01:00
Dolu1990 8f22365959 Disable MMU in machine mode 2019-03-19 22:21:30 +01:00
Dolu1990 3fbc2f4458 Fix generation 2019-03-19 20:29:28 +01:00
Dolu1990 915db9d6c9 cleaning 2019-03-18 20:50:19 +01:00
Dolu1990 001ca45c57 Add cachless dBus IBus access right checks 2019-03-18 12:52:22 +01:00
Dolu1990 c490838202 Added MMU support into cacheless DBus IBus plugins (for testing purposes) 
Probably full of bugs, need testing
 2019-03-18 12:17:43 +01:00
Dolu1990 ffa489d211 hardware refilled MmuPlugin wip 2019-03-17 21:06:47 +01:00
Tom Verbeure b63395435f SimpleMul core. 2019-03-16 15:44:18 +00:00
Tom Verbeure 5bc53c08ce Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple 2019-03-16 15:39:07 +00:00
Dolu1990 9a61ff8347 Merge remote-tracking branch 'origin/dev' 2019-03-10 11:14:09 +01:00
Dolu1990 bad60f39cd Fix Decoding benchmark 2019-03-10 11:12:32 +01:00
Dolu1990 434793711b fix part of #59 2019-02-26 17:26:42 +01:00
Dolu1990 e0c8ac01d2 Add custom external interrupts 2019-02-03 15:20:34 +01:00
Dolu1990 11f55359c6 IBusCache can now avoid injectorStage in singleStage mode 2019-01-30 01:37:47 +01:00
Dolu1990 56e3321394 cpp regresion now print the time of failure 2019-01-30 01:36:24 +01:00
Dolu1990 f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990 b5caca54cd restore all feature in TestsWorkspace 2019-01-16 15:25:50 +01:00
Dolu1990 927ab6d127 Merge remote-tracking branch 'origin/master' into dev 2018-12-30 15:53:25 +01:00
Dolu1990 dd42e30c61 Merge remote-tracking branch 'origin/master' into dev 2018-12-29 14:04:07 +01:00
Dolu1990 d617bafb08 Roll back VexRiscvAvalonForSim to use caches 2018-12-25 00:15:23 +01:00
Brett Foster 961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00
Dolu1990 76ebfb2243 Fix machine mode to supervisor delegation 2018-12-10 13:15:03 +01:00
Dolu1990 d9029c2efc Fix #46 by filling missing return statements 2018-12-10 01:44:47 +01:00
Dolu1990 281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990 1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990 f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990 9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990 52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990 68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990 eca54585b0 Fix hardware breakpoint 2018-12-04 16:57:24 +01:00
Dolu1990 ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990 3d71045159 DebugPlugin doesn't require memory/writeback stage anymore 2018-12-01 18:24:33 +01:00