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1017 commits

Author SHA1 Message Date
Dolu1990
1c3b9e93a2
Merge pull request #182 from rdolbeau/extra_config 
Make the [ID]TLB size configurable from Litex
 2021-05-12 13:54:27 +02:00
Dolu1990
fe739b907a Bench DecoderPlugin 2021-05-10 10:47:15 +02:00
Romain Dolbeau
1bd33a369e Make the [ID]TLB size configurable from Litex 2021-05-08 07:59:34 -04:00
Dolu1990
e78c0546a0 fix #178 2021-05-04 21:09:42 +02:00
Dolu1990
fa2899a1a2 Merge branch 'debugPlugin' into dev 2021-04-26 11:11:38 +02:00
Dolu1990
45e67ccf56 sync 2021-04-26 11:10:55 +02:00
Dolu1990
0a0998fcea #176 fix typo 2021-04-22 14:02:46 +02:00
Dolu1990
32e4ea406f update #176 when DebugPlugin ebreak are enabled it disable CsrPlugin ebreak. Also, DebugPlugin ebreak can be disabled via the debug bus. 2021-04-22 13:59:33 +02:00
Dolu1990
bfe65da1eb implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used. 2021-04-20 23:23:18 +02:00
Samuel Lindemer
79bc09e69a Decouple PMP and CSR plugins 2021-04-13 08:35:07 +02:00
Samuel Lindemer
15137742fc
Merge branch 'dev' into new_pmp 2021-04-12 13:23:10 +02:00
Samuel Lindemer
b41db0af93 Prevent PMP access from U-mode, fix tests 2021-04-12 13:20:15 +02:00
Samuel Lindemer
bf399cc927 Initial commit of optimized PMP plugin 2021-04-12 13:20:15 +02:00
Tim Callahan
36c896f95b Update CFU immed field to use sext([31:24]) to match spec. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2021-04-02 13:16:53 -07:00
Dolu1990
66f5c3079b CfuPlugin names fixes 2021-04-02 12:50:21 -07:00
Dolu1990
73893ce5d9 CfuPlugin names fixes 2021-04-02 09:20:26 +02:00
Dolu1990
a42c089119 IBusSimplePlugin ensure AHB persistance 2021-03-31 19:03:38 +02:00
Dolu1990
9ac6625ef3 FpuCore improve FMA rounding 2021-03-29 16:31:18 +02:00
Dolu1990
9462496386 Add rvc support and fix rvc with FPU 2021-03-25 14:14:19 +01:00
Dolu1990
6f481f51ef Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage) 2021-03-25 14:13:12 +01:00
Dolu1990
21c91c6b70 fpu now lift wfi 2021-03-24 16:21:37 +01:00
Dolu1990
925edd160e RVC implement RVF RVD 
Rework RVC_GEN
 2021-03-24 12:04:27 +01:00
Romain Dolbeau
8495fe3dde Attempt at supporting C (ompressed) and F/D (floating-point) together 2021-03-24 11:07:09 +01:00
Dolu1990
da458dea7e litex cluster add cpuPerFpu option 2021-03-23 20:00:50 +01:00
Dolu1990
80f64f0f9f litex better pipelining for better fmax, create one FPU for each 4 cores 2021-03-18 11:10:22 +01:00
Dolu1990
6956db2b21 fpu add schedulerM2sPipe optino 2021-03-18 11:10:22 +01:00
Dolu1990
099dea743b fpu cleanup 2021-03-18 10:54:51 +01:00
Dolu1990
f6e620196d litex add fpu suport 2021-03-17 13:19:41 +01:00
Dolu1990
e23687c45d Handle ClockDomain improvements 2021-03-16 14:46:30 +01:00
Dolu1990
02c572b6f1 fpu improve FMax and add asyncronus regfile support 2021-03-16 14:45:59 +01:00
Dolu1990
5aa1f2e996 fpu improve pipline cycles 2021-03-15 17:27:14 +01:00
Dolu1990
341c159d06 data cache relax assert into error 2021-03-15 14:43:22 +01:00
Dolu1990
3a34b8dae2 Merge branch 'dev' into fiber 
# Conflicts:
#	src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
#	src/main/scala/vexriscv/plugin/MulPlugin.scala
 2021-03-15 10:35:02 +01:00
Charles Papon
ff4e5e4666 wipe generator 2021-03-11 18:02:02 +01:00
Charles Papon
adc37b269c FpuPlugin.pending is now 6 bits 2021-03-11 13:06:50 +01:00
Charles Papon
845cfcb966 DebugPlugin.fromBscane2 added 2021-03-10 20:35:44 +01:00
Charles Papon
67d2f72a4b fiber sync 2021-03-07 20:43:02 +01:00
Dolu1990
e384bfe145 fiber update 2021-03-05 22:04:20 +01:00
Dolu1990
fd234bbf9e fix cfu gen error 2021-03-05 09:41:05 +01:00
Dolu1990
aee8841438 CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck 2021-03-05 09:41:05 +01:00
Dolu1990
ec507308e7 fix cfu gen error 2021-03-04 20:29:33 +01:00
Dolu1990
bdc52097b6 CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck 2021-03-04 20:15:01 +01:00
Dolu1990
0530d22a1d sync 2021-03-04 16:06:18 +01:00
Dolu1990
caf1bde49b Add MuraxAsicBlackBox example 2021-03-04 10:16:45 +01:00
Dolu1990
4bdab667cc fpu fix cmd / commit race condition 2021-03-02 19:39:55 +01:00
Dolu1990
636d53cf63 fpu now track commits using a counter per pipeline per port 2021-03-02 16:13:12 +01:00
Dolu1990
81c193af1f Improve subnormal/normal rounding 2021-02-26 16:32:42 +01:00
Dolu1990
de81da36eb Fpu fix a few div special cases 2021-02-25 19:39:57 +01:00
Dolu1990
de09ed3fcb fpu added exact div/sqrt implementations using iterative approaches 2021-02-25 15:28:38 +01:00
Dolu1990
be81cc1e0e CfuPlugin.response_ok removed 2021-02-23 12:23:48 +01:00
Dolu1990
47673863fb fpu test cleaning 2021-02-22 19:27:55 +01:00
Dolu1990
b1f4c06d4e fpu fix arbitration/lock bugs 
add getVexRiscvRegressionArgs
 2021-02-22 19:27:26 +01:00
Dolu1990
a6e89fe05c fpu vex regression goldenModel can now assert FPU interface 2021-02-19 17:55:56 +01:00
Dolu1990
3f226b758c fpu fix exception flag handeling 2021-02-19 13:03:48 +01:00
Dolu1990
e504afbf18 fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined) 2021-02-19 11:26:28 +01:00
Dolu1990
8537d18b16 fpu improve fmax 2021-02-17 16:35:52 +01:00
Dolu1990
1e647f799c fpu Fix VexRiscv integration and add software f64 tests (pass) 2021-02-17 12:33:27 +01:00
Dolu1990
06b7a91de4 MulPlugin fix buffer interraction with partial regfile bypass 2021-02-17 11:35:17 +01:00
Dolu1990
f180ba2fc9 fpu double fixes 
DataCache now support wide load/store
 2021-02-16 15:38:51 +01:00
Dolu1990
8b2a2afb6f VexRIscvSmpCluster add options 2021-02-16 14:42:31 +01:00
Dolu1990
1752b9e6d6 DataCache.toBmb with aggregation sync path pipelined 2021-02-16 14:17:21 +01:00
Dolu1990
fe690528f7 MulPlugin.outputBuffer feature added 2021-02-16 14:16:57 +01:00
Dolu1990
3b99090879 VexRiscvConfig.get added 2021-02-16 14:15:20 +01:00
Dolu1990
7d3b35c32c fpu f64/f32 pass all tests 2021-02-12 14:48:44 +01:00
Dolu1990
9a25a12879 fpu add FCVT_X_X 2021-02-11 17:40:35 +01:00
Dolu1990
82dfd10dba fpu fix f32 tests for f64 fpu 2021-02-11 16:42:17 +01:00
Dolu1990
b6eda1ad7a fpu f64 load/store/mv/mul seems ok 2021-02-11 16:07:47 +01:00
Dolu1990
e97c2de837 fpu f64 wip 2021-02-10 19:27:26 +01:00
Dolu1990
88dffc21f7 fpu f64 wip 2021-02-10 13:20:17 +01:00
Dolu1990
889cc5fde2 fpu refractoring 2021-02-10 12:16:56 +01:00
Dolu1990
1fe993ad10 fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully 2021-02-09 18:35:47 +01:00
Dolu1990
bf6a64b6b5 fpu sgnj / fclass / fmv pass 2021-02-08 15:29:50 +01:00
Dolu1990
bf0829231d fpu min max pass 2021-02-06 14:08:21 +01:00
Dolu1990
008fadeaa9 fpu eq lt le pass testfloat 2021-02-06 13:20:27 +01:00
Dolu1990
6170243283 fpu got exception flag right for add/sub/mul/i2f/f2i 2021-02-05 16:24:14 +01:00
Dolu1990
f278900cbe VexRiscvSmpCluster can now set regfile read kind 2021-02-05 11:09:18 +01:00
Dolu1990
0f1ca72171 fix synthesis bench 2021-02-04 12:43:31 +01:00
Dolu1990
936e5823dc fpu test wip 2021-02-04 12:41:49 +01:00
Dolu1990
3710fd3492 fix synthesis bench 2021-02-04 12:41:31 +01:00
Dolu1990
02b5b9b05c fpu load subnormal and i2f now use single cycle shifter 2021-02-03 16:48:09 +01:00
Dolu1990
8e7e736e3e Merge branch 'dev' into fpu 
# Conflicts:
#	src/main/scala/vexriscv/Riscv.scala
#	src/main/scala/vexriscv/ip/fpu/FpuCore.scala
#	src/main/scala/vexriscv/ip/fpu/Interface.scala
#	src/test/scala/vexriscv/ip/fpu/FpuTest.scala
 2021-02-03 16:06:17 +01:00
Dolu1990
8eb8356dea fpu wip 2021-02-03 14:28:02 +01:00
Dolu1990
1d0eecdcb0 fpu f2i rounding ok and full shifter 2021-02-03 14:27:52 +01:00
Dolu1990
ef011fa0d4 fpu moved 1 bit from round to mantissa 2021-02-02 11:29:35 +01:00
Dolu1990
a87cb202b1 fpu i2f rounding ok 2021-02-01 16:12:38 +01:00
Dolu1990
6aa6191240 Merge branch 'master' into dev 
# Conflicts:
#	build.sbt
#	src/main/scala/vexriscv/Riscv.scala
#	src/main/scala/vexriscv/ip/DataCache.scala
#	src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
#	src/main/scala/vexriscv/plugin/MmuPlugin.scala
#	src/test/cpp/regression/makefile
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
 2021-01-30 20:30:21 +01:00
Dolu1990
c51b0fcafe fpu mul now pass all roundings 2021-01-29 22:30:19 +01:00
Dolu1990
0997592768 fpu mul sems all good excepted subnormal rounding 2021-01-29 16:13:49 +01:00
Dolu1990
3c4df1e963 fpu moved overflow rounding to writeback 2021-01-29 14:37:52 +01:00
Dolu1990
fc3e6a6d0a fpu add rounding is ok excepted infinity result 2021-01-28 20:26:43 +01:00
Dolu1990
1ae84ea83b fpu added proper rounding for add (need to manage substraction) 2021-01-28 00:25:16 +01:00
Dolu1990
195e4c422d fpu now integrate f2i shifter withing the subnormal shifter 2021-01-27 12:11:30 +01:00
Dolu1990
444bcdba0a fpu merged i2f with load pipeline 2021-01-26 15:28:09 +01:00
Dolu1990
3334364f5f fpu added more tests for min max sqrt div 2021-01-26 12:50:23 +01:00
Dolu1990
f818fb3ba4 fpu got proper subnormal support, pass add/mul 2021-01-26 10:49:53 +01:00
Dolu1990
d6e8a5ef22 VexRiscvSmpLitex options refractoring 2021-01-23 20:16:58 +01:00
Dolu1990
ce143e06f2 VexRiscvSmpLitex --in-order-decoder --wishbone-memory added 2021-01-23 17:48:34 +01:00
Dolu1990
bdb5bc1180 fpu div implement some special values handeling 2021-01-22 20:47:31 +01:00
Dolu1990
7d79685fe2 fpu mul now support special floats values and better rounding 2021-01-22 18:15:45 +01:00
Dolu1990
4bd637cf88 fpu add now support special floats values and better rounding 2021-01-22 14:55:37 +01:00