Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,369 Commits 39 Branches 2 Tags 15 MiB
Commit Graph

1369 Commits

Author SHA1 Message Date
Dolu1990 b2e61caf9e CfuPlugin now implement upstream spec 2022-03-23 18:54:07 +01:00
Dolu1990 9149c42065 DecoderPlugin now implement forceIllegal API 2022-03-23 18:53:43 +01:00
Dolu1990 51b8865b66 Fix VexRiscvSmpClusterGen linux less mhartid 2022-03-18 12:36:05 +01:00
Dolu1990 e558b79582 Fix Briey simulation floating rxd blocking the uart #238 2022-02-22 16:15:14 +01:00
Dolu1990 9d3b83366c Merge branch 'master' into dev 2022-02-17 16:27:26 +01:00
Dolu1990 36f57d5eb7
Merge pull request #236 from dnltz/WIP/dnltz/remove-assert 
plugin: DBusSimplePlugin: Remove assert
 2022-02-17 16:25:45 +01:00
Dolu1990 5b45ddab1b SpinalHDL 1.6.4 2022-02-16 14:26:58 +01:00
Dolu1990 e4fde184d9 SpinalHDL 1.6.5 2022-02-16 14:12:00 +01:00
Daniel Schultz 807aa98d37 plugin: DBusSimplePlugin: Remove assert 
This assert triggered sometimes at the beginning of a simulation.
Since it's not really needed anymore, we can remove it.

Signed-off-by: Daniel Schultz <daniel.schultz@aesc-silicon.de>
 2022-02-10 19:55:08 +01:00
Dolu1990 77e361e91e Merge branch 'dev' 2022-02-05 12:08:43 +01:00
Dolu1990 5714680278 Merge branch 'master' into dev 
# Conflicts:
#	build.sbt
 2022-02-05 11:32:40 +01:00
Dolu1990 62c07670af version++ 2022-02-05 11:31:04 +01:00
Dolu1990 4dd650736f verilator++ 2022-02-04 16:36:11 +01:00
Dolu1990 378c0f8723 verilator++ 2022-02-04 16:20:43 +01:00
Dolu1990 8b2f107d46 verilator++ 2022-02-04 15:10:57 +01:00
Dolu1990 7d9a50357f
Merge pull request #233 from dnltz/WIP/dnltz/csr-registers 
plugin: CsrPlugin: Init cycle and instret registers
 2022-01-27 12:05:43 +01:00
Daniel Schultz 57dd80a566 plugin: CsrPlugin: Init cycle and instret registers 
Both counters are initialized with "randBoot()". This is fine for FPGA
designs because the registers can be loaded with default values but
ASIC designs require to load the value during a reset.

Since both counters require to start at 0 (read-only CSR registers),
change both registers from "randBoot()" to "init(0)".

Error:

    reg        [63:0]   CsrPlugin_mcycle = 64'b0000000...00000000000;

           |
  Warning : Ignoring unsynthesizable construct. [VLOGPT-37]

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
 2022-01-26 08:59:03 +01:00
Dolu1990 9c34a1fd2e updated related to JtagInstructionWrapper.ignoreWidth 2022-01-14 09:59:24 +01:00
Dolu1990 b8e904e43f syncronize golden model with dut for lrsc reservation 2022-01-10 19:55:28 +01:00
Dolu1990 6e77f32087 sim golden model lrsc reservation sync 2022-01-10 16:08:38 +01:00
Dolu1990 da53de360f Fix lrsc from last commit 2022-01-10 14:21:20 +01:00
Dolu1990 f46ad43f39
DataCache.withInternalLrSc reserved clearing fix 2022-01-10 13:39:41 +01:00
Dolu1990 349993b235
Merge pull request #230 from OscarShiang/typo 
Fix typo in Linux.scala
 2022-01-04 11:02:27 +01:00
Oscar Shiang fe6c391fe4 Fix typo in Linux.scala 
Correct "machime" to "machine".
 2022-01-04 16:31:23 +08:00
Dolu1990 34e5cafb75 Enable scala 2.13 compatibility 2021-12-20 09:38:35 +01:00
Dolu1990 4824827b7e Enable scala 2.13 compatibility 2021-12-20 09:38:02 +01:00
Dolu1990 a340798840
Update build.properties 2021-12-18 09:11:08 +01:00
Dolu1990 53a3330340
Update build.properties 2021-12-18 09:10:43 +01:00
Dolu1990 dd12047aa7 Merge branch dev (SpinalHDL 1.6.1) 2021-12-15 09:22:46 +01:00
Dolu1990 0539dd7110
SpinalHDL 1.6.2 2021-12-08 23:45:05 +01:00
Dolu1990 6c5908f7a3
Merge pull request #220 from BLangOS/patch-1 
Update DebugPlugin.scala: Add optional readback of hardware breakpoint values
 2021-11-15 09:25:00 +01:00
B.Lang 411d946a58
Update DebugPlugin.scala 
Add readback of the hardware breakpoint values.
A new parameter is added to the plugin to switch readback on and off.
 2021-11-11 12:12:23 +01:00
Dolu1990 acf14385d8 #213 disable pmp test with region overlapping 2021-10-22 17:24:51 +02:00
Dolu1990 9df704cad9
Merge pull request #213 from occheung/pmp-fix 
PMP Plugin: Fix PMP region size & priority
 2021-10-21 10:13:21 +02:00
occheung a3807660e3 pmp perm: revert to mux for priority 2021-10-19 11:40:39 +08:00
occheung df03c99ab2 pmp_setter: fix mask generation 2021-10-19 11:39:25 +08:00
Dolu1990 c3c3a94c5d IBusSimplePlugin can now use a Vec based buffer 2021-10-13 16:26:16 +02:00
Dolu1990 97a3c1955b VexRiscvSmpCluster add d$ i$ less arg 2021-10-11 11:57:39 +02:00
Dolu1990 35754a0709 Fix BrieySim (SpinalSim) 2021-09-25 13:28:37 +02:00
Dolu1990 8c0fbcadac Add BrieySim (SpinalSim) 2021-09-25 13:18:55 +02:00
Dolu1990 5f5f4afbf2 Briey revert RVC unwanted addition 2021-09-22 15:01:08 +02:00
Dolu1990 b807254759 Briey and Murax verilators now use FST instead of VCD 2021-09-22 12:57:27 +02:00
Dolu1990 65cda95176 Fix wishbone bridges with datawidth > 32 2021-09-17 09:43:30 +02:00
Dolu1990 c1481ae244 update ScopeProperty usages 2021-09-16 19:08:41 +02:00
Dolu1990 42bb1ab591 d$ / i$ toWishbone bridges can now be bigger than 32 bits 
https://github.com/m-labs/VexRiscv-verilog/pull/12
 2021-09-15 11:36:51 +02:00
Dolu1990 68e704f309 restore avalon d$ tests 2021-09-02 15:42:33 +02:00
Dolu1990 efd3cd4737 Merge branch 'master' into dev 2021-09-02 14:16:07 +02:00
Dolu1990 cc9f3e753a Fix d$ toAxi bridge 2021-09-02 14:14:42 +02:00
Dolu1990 bc561c30eb Add PmpPluginOld (support TOR) 2021-09-01 11:27:12 +02:00
Dolu1990 5c7e4a0294 #170 wishbone example now set dBusCmdMasterPipe 2021-08-24 23:24:29 +02:00