a9ecbffe8f
Merge pull request #520 from josuah/crosslink_nx_prog_flash
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targets/lattice_crosslink_nx_evn: fix arguments in flash programming
2023-08-28 16:33:23 +02:00
2c3d77b5be
Merge branch 'master' into crosslink_nx_spi_flash
2023-08-28 16:32:37 +02:00
efb76133be
Merge pull request #519 from josuah/fix_crosslink_nx_uartbone
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Crosslink-NX EVN: fix UARTBone always disabled
2023-08-28 16:31:29 +02:00
5799c35247
platforms/gsd_orangecrab: Set alt point to DFUProg.
2023-08-28 16:28:04 +02:00
a5a6a313cc
targets/lattice_crosslink_nx_evn: add main_ram section for firmware
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This takes the values from the Antmicro SDI MIPI converter as a model
and is enough to run a Zephyr hello world, but not seemingly enough for
a the Zephyr Shell sample.
Related: https://github.com/litex-hub/zephyr-on-litex-vexriscv/pull/13
2023-08-18 19:56:58 +02:00
ebfb9b8e01
sipeed_tang_mega_138k: new board
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Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-15 16:33:13 +08:00
2e5c6eb7a7
platforms/crosslink_nx_evn: add SPI flash support
2023-08-11 16:46:52 +02:00
1a46bcce5e
targets/lattice_crosslink_nx_evn: fix arguments in flash programming
2023-08-10 14:39:01 +02:00
3c0b6956cc
platforms/crosslink_nx_evn: Fix 5412d0e always disabling uartbone
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Also fix a warning about register_mem being deprecated, taking
inspiration from platforms/crosslink_nx_vip
2023-08-09 18:07:13 +02:00
8172a304b3
platforms/crosslink_nx_evn: allow use of OpenOCD
2023-08-08 23:25:41 +02:00
3903cdee92
Merge pull request #517 from bayi/master
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Digilent CMOD A7 ISSIRAM fix
2023-08-08 19:29:32 +02:00
4362cb23a1
Fix Digilent Cmod A7 ISSIRAM reading
2023-08-05 19:56:32 +02:00
a6b025f7f3
Fix Digilent Cmod A7 ISSIRAM reading
2023-08-05 19:56:15 +02:00
5412d0e0e9
platforms/crosslink_nx_evn: allow use of UARTBone
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This goes along a small resistor jumper modification and firmware flashing like
it is for the ECP5 board. A warning message is added as the default serial might
be affected (--serial serial by default). The FTDI modification software used
for the ECP5 seems to be requried and matching.
This can be tested this way:
targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load
litex_server --uart --uart-port /dev/ttyUSB1
litex_cli --regs
2023-08-04 20:47:32 +02:00
efc15a91a9
global: Use new WaitTimer integrated cast to int.
2023-08-01 14:56:35 +02:00
538399cb3b
lattice_ecp5_evn: update OpenOCD syntax
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When running `litex_server`, this error appeared:
can't read "_CHIPNAME": no such variable
This is a fix for the specific lattice_ecp5_evn board.
It also refreshes the OpenOCD syntax.
2023-07-31 14:05:34 +02:00
cbcf6df26f
lattice_ecp5_evn: add_jtagbone flag
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This follows https://github.com/enjoy-digital/litex/pull/1087 which
allows using the built-in JTAG for both the FPGA programming and the
internal core of the FPGA.
2023-07-31 13:53:24 +02:00
2d3b81a532
efinix_trion_t120_bga576: Add Ethernet through RGMII PMOD and switch to it.
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See https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-859366899 for the PMOD.
2023-07-27 11:52:40 +02:00
c1088befe5
targets/CRG: Add rst signal when missing.
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Allow properly reseting the PLL from the SoC.
2023-07-26 16:56:27 +02:00
ace789653f
platforms/ti60_f225: Add connector numbering to ease review/schematic comparison.
2023-07-21 09:08:22 +02:00
ce121663ff
targets/uartbone: Update with LiteX change.
2023-07-20 15:42:47 +02:00
72a951081a
xu8_pe3: Fix clk_p/n on pcie_x8.
2023-07-13 18:10:46 +02:00
18a3909a9c
global: Switch to litex.gen.genlib.misc.
2023-07-06 22:11:45 +02:00
67be3ab677
targets: +x on alchitry_cu and vcu128.
2023-07-06 13:29:35 +02:00
e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu
2023-06-27 21:35:55 +05:30
061a768495
Add Alchitry Cu board
2023-06-16 21:36:57 +05:30
c49a50a934
platform/gsd_butterstick: Add mssing USB comment.
2023-06-16 09:10:47 +02:00
28ecb1e9f3
enclustra_mercury_xu8_pe3: Fix pcie_x8 and add GTH banks for pcie_x4/x8.
2023-06-15 17:57:38 +02:00
06e8829eb4
platforms/gsd_butterstick: Add default programmer to avoid breaking older designs.
2023-06-14 16:40:35 +02:00
58805f037c
avnet_aesku40: Expose ethernet/etherbone parameters.
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To be able to test more easily usrgmii build.
2023-06-13 09:26:07 +02:00
4705a0274e
Support SPI Flash in Colorlight 5A-75x
2023-06-09 13:43:34 -04:00
96175a9986
sitlinv_stlv7325_v2: Add default value to vccio.
2023-06-07 15:00:49 +02:00
765ee1a3ce
sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V
2023-06-07 10:12:55 +07:00
b01abce7d5
platform/stlv7325-v2: update VCCIO to fix --with-pcie generation
2023-06-01 16:45:33 -04:00
7fc8ca9816
Merge pull request #506 from sensille/rv901t-spiflash
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Add spiflash definition to linsn_rv901t board
2023-05-30 22:36:14 +02:00
8a263c18f2
sitlinv_stlv7325: Rename to v1 and update VCCIO to fix --with-pcie generation.
2023-05-30 10:39:20 +02:00
4a05e56058
Add spiflash definition to linsn_rv901t board
2023-05-27 16:20:32 +02:00
2ae2dfa6a3
Add vcu128 target ( #497 )
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Add initial VCU128 support.
2023-05-25 22:25:44 +02:00
9362e589ac
Add initial Enclustra XU8/PE3 platform definition with Clk/I2C/PCIe/DDR4 and FMC connector definition.
2023-05-25 10:01:19 +02:00
e59d75f593
qmtech_xc7k325t: Fix build/CI.
2023-05-12 12:19:16 +02:00
ca6b607255
targets/qmtech: Add missing +x.
2023-05-12 12:09:20 +02:00
550bc0eee5
add QMTech XC7K325T board, add seven segment display to daughterboard
2023-05-08 11:51:51 +07:00
187080228c
add qmtech_xc7l325t
2023-05-08 05:17:35 +07:00
d33cf1a74c
mnt_rkx7: Cosmetic cleanups.
2023-05-05 09:48:06 +02:00
c05c494a82
targets/mnt_rkx7/usb_ohci: Use SoC.bus if SoC does not have a DMA bus.
2023-05-05 09:43:19 +02:00
6144966d24
Merge pull request #501 from mntmn/master
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mnt_rkx7: RGB and USB fix, add HDMI terminal
2023-05-05 09:37:40 +02:00
9c222454cc
Merge pull request #503 from chmousset/add_colorlight_i5a-907
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Add colorlight i5a 907
2023-05-03 09:50:26 +02:00
2bff2d4260
target/stlv7325-v2: tune eth phy delay
2023-05-01 09:28:03 -04:00
31c680abf8
[enh] added option for uartbone
2023-04-30 09:42:31 +02:00
874532871f
[enh] taking advantage of pins directly connected
2023-04-30 09:24:49 +02:00
1202c387bf
[init] added colorlight i5a-907 support
2023-04-30 09:24:46 +02:00
fd5511f3fd
[fix] add pmod uart in default config
2023-04-30 09:24:15 +02:00
f5dfdf9abf
[enh] added doc about JTAG and ext. board
2023-04-29 19:39:51 +02:00
322cc5d45b
[init] added colorlight i9+ based on XC7A50 FPGA
2023-04-29 18:36:35 +02:00
1f6e7f36a5
target/stlv7325-v2: fix typo in eth phy delay
2023-04-28 16:56:37 -04:00
1185ff51f1
Initial support for STLV7325 (v2) Kintex-7 board.
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This is the 2nd (2023) version of the board sold through
https://www.aliexpress.us/item/3256801088848039.html
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-04-28 10:24:21 -04:00
a9e3e3c050
Merge branch 'master' of https://github.com/litex-hub/litex-boards
2023-04-25 20:29:11 +02:00
d160a5ad5d
mnt_rkx7: swap RGB red/blue channels
2023-04-25 20:28:16 +02:00
17a5d3c130
mnt_rkx7: add HDMI terminal, default USB to true
2023-04-25 20:27:29 +02:00
68bfb325a5
Fix Memory test failure of Alveo U250
2023-04-24 17:35:58 +09:00
9322869196
Merge pull request #495 from vietthanh85/master
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Fix Memory initialization of Alveo U200 failed #1606
2023-04-24 08:09:25 +02:00
03913e2e15
Update terasic_de10nano.py
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Corrected pin number
2023-04-23 22:28:00 -05:00
340da5393c
Fix Memory initialization of Alveo U200 failed #1606
2023-04-17 18:59:50 +07:00
2ed66317c7
efinix_xyloni_dev_kit: fix build error
2023-04-14 22:31:21 +10:00
b8cb2eaa47
Merge pull request #493 from hansfbaier/deca-ddr3
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make DDR3 memory work on the DECA with the UniPHY
2023-04-11 15:27:02 +02:00
60ac45e80c
make DDR3 memory work on the DECA with the UniPHY
2023-04-11 19:59:49 +07:00
e120b77ef0
enclustra kx2/st1: fix connectors
2023-04-11 10:58:52 +07:00
c7077880b9
copyright notices on enclustra
2023-04-11 10:29:52 +07:00
ed947d1b55
enclustra: add baseboard ST1
2023-04-11 10:29:44 +07:00
be8ee26b2c
enclustra_mercury_kx2: Add ST1 baseboard, part 1
2023-04-11 05:39:11 +07:00
58679262ad
enclustra kx2: add connectors
2023-04-10 14:06:42 +07:00
a8eb0b20c1
Merge pull request #491 from hansfbaier/stlv7325-hdmi
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STL7325: Add Video, and connectors (FMC, BTB, 2.54mm)
2023-04-07 09:06:55 +02:00
52ca60c2ac
stlv7325: fix HDMI io standard
2023-04-07 09:50:04 +07:00
2f13decc49
stlv7325: make VCCIO configurable
2023-04-07 09:27:03 +07:00
566a753dd3
stlv7325: S7PLL is enough
2023-04-07 08:45:06 +07:00
7c99f0758d
stlv7325: fix video args
2023-04-07 08:35:49 +07:00
66cbd27bbf
stlv7325: fix video PHY
2023-04-07 08:25:59 +07:00
abd639ba9e
stlv7325: add 2.54mm headers
2023-04-07 08:21:17 +07:00
3f85e4ae62
stlv7325: add BTB connectors
2023-04-07 08:09:27 +07:00
b3e44324d1
sitlinv_stlv7325: add FMC connector
2023-04-07 07:56:27 +07:00
5067a2683f
sitlinv_stlv7325: add video HDMI, enable compressed bitstream
2023-04-07 07:31:42 +07:00
43ce24dcb3
add QMTech 5CEFA5 Cyclone V board support
2023-04-06 18:27:51 +07:00
ae3d5d599b
sqrl_fk33: Remove es1 workaround now that recent version of Vivado support it non-es devices.
2023-04-04 18:11:38 +02:00
a4925d14f9
Merge pull request #488 from Icenowy/stlv7325-s7pll
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sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock
2023-04-04 08:22:16 +02:00
1b9a74bf08
targets/nexys-video: simplify sata configuration
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Make nexys-video SATA configuration similar to the way it is supported
on the majority of other SATA-capable targets.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-04-03 12:28:12 -04:00
b1107e94d4
sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock
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As we do not need fine phase tweaking for the main system clock, use
S7PLL instead of S7MMCM to allow higher VCO frequency and more flexible
sys_clk_freq.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-04-03 16:45:13 +08:00
e11d40a249
Merge pull request #487 from ICE-V-Wireless/master
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Add PMOD registrations to ICE-V Wireless
2023-04-02 11:44:02 +02:00
5de47baa44
Add PMOD registrations to ICE-V Wireless
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Signed-off-by: Michael Welling <mwelling@ieee.org>
2023-04-02 03:31:55 -05:00
f564f80826
terasic_deca: hdmi i2s uses 1.8V, not 3.3V
2023-04-01 08:14:09 +07:00
74c8569a5c
DDR3 RAM works on 1.5V, not 1.35V
2023-03-27 15:17:42 +07:00
40c8e62b09
use bistream compression on those large devices
2023-03-21 09:25:56 +07:00
0125ae4271
Add support for QMTech Artix7 200T FBG484 board
2023-03-20 08:21:36 +07:00
98ddb97f5e
Support QMTech XC7A75T, XC7A100T core boards
2023-03-20 07:57:58 +07:00
6b8a5d35c0
sipeed_tang_nano_20k: support copackaged SDRAM
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The copackaged SDRAM of GW2AR-18 QN88 package is 8MB size, 32bit DQ
width.
Add support for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-03-13 17:11:06 +08:00
291c43b898
sipeed_tang_nano_20k: new board
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This board uses Gowin GW2AR series chip (which is GW2A with integrated
RAM).
Support for the integrated SDRAM on Tang Nano 20K is still TODO.
Note: currently when the SD card is enabled, block 0 could be correctly
read but block 1 will fail.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-03-13 16:45:25 +08:00
28a1aefc21
Update sipeed_tang_nano_9k.py
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add pin info for _connectors
2023-03-09 17:57:39 +01:00
bf4f688164
targets/pcie: Update Xilinx S7 constraints.
2023-03-06 12:20:34 +01:00
1df46d1571
platforms/sipeed_tang_nano_9k: Review SPI RGB LCD addition.
2023-03-06 09:03:12 +01:00
8d35591f47
Update sipeed_tang_nano_9k.py
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add SPI-Interface for the 1.14inch LCD
2023-03-04 15:25:59 +01:00
943cf2636f
platforms/sipeed_tang_primer_20k: Add checkme on leds IOstandard.
2023-03-02 12:14:04 +01:00
enjoy-digital
Josuah Demangeon
Icenowy Zheng
Bayi
Mark1626
Ilya Ostrovskiy
Hans Baier
Gabriel Somlo
Arne Jansen
Chen
Charles-Henri Mousset
Lukas F. Hartmann
offNaria
594rk
Do Viet Thanh
Richard Tucker
Michael Welling
Marco