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386 commits

Author SHA1 Message Date
Florent Kermarrec
0e2d9a571e alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards). 2021-03-10 11:23:27 +01:00
enjoy-digital
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280 
Alveo U280 board
 2021-03-10 11:16:32 +01:00
enjoy-digital
7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x 
crosslink_nx_vip: Remove constraints for hard MIPI pins
 2021-03-10 11:13:49 +01:00
Florent Kermarrec
47faaf20d5 deca: Integrate Video Terminal (untested, resource issue). 2021-03-09 15:02:30 +01:00
gatecat
496cae54ff crosslink_nx_vip: Remove constraint for MIPI pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 14:26:40 +00:00
gatecat
547157c9ca crosslink_nx_vip: Fix cam_reset IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 11:26:56 +00:00
gatecat
542001dddf crosslink_nx_vip: Split camera MCLK to its own resource 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 11:18:37 +00:00
Florent Kermarrec
51a0bbfa65 platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support. 2021-03-03 18:05:24 +01:00
Florent Kermarrec
3af8ec0c8d targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal. 2021-03-03 17:10:22 +01:00
Florent Kermarrec
7e3b8ab3b5 icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core. 
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash

https://twitter.com/enjoy_digital/status/1365324823447171074
 2021-03-03 16:21:04 +01:00
enjoy-digital
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod 2021-02-25 09:37:34 +01:00
Hans Baier
6f558a5d65 Add board support for Terasic/Arrow DECA board 2021-02-25 12:25:43 +07:00
Joel Stanley
2b49082696 platforms/arty: Add numato sd card pmod 
It has a different layout.

Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817

 Expansion Pin 	SD 	SPI SD 	Artix 	Arty-A7 	PMOD PIN 	PMOD Index
 2 		DATA_2 	  	D4 	JD1 		1 		0
 4 		CMD 	MOSI 	D3 	JD2 		2 		1
 6 		DATA_0 	MISO 	F4 	JD3 		3 		2
   		CD 	  	F3 	JD4 		4 		3
 1 		DATA_3 	CS_N 	E2 	JD7 		7 		4
 3 		CLK 	CLK 	D2 	JD8 		8 		5
 5 		DATA_1 	  	H2 	JD9 		9 		6
   	  		  	G2 	JD10

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-02-24 14:59:50 +10:30
enjoy-digital
5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk 
fix vc707 default_clk_period
 2021-02-23 12:17:45 +01:00
Florent Kermarrec
a90c0bc8f9 platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope. 2021-02-22 13:45:48 +01:00
Michael Betz
09c3bd616b Merge branch 'master' into vc707_clk 2021-02-19 22:49:46 -08:00
Michael Betz
c32e790421 vc707: fix default clock frequency 2021-02-19 22:47:18 -08:00
enjoy-digital
1fcd96971d
Merge pull request #172 from hansfbaier/master 
sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
 2021-02-16 22:44:52 +01:00
Florent Kermarrec
975150ca68 platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks. 2021-02-16 17:32:41 +01:00
Florent Kermarrec
9baa9d5d83 platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811). 2021-02-12 15:23:17 +01:00
Hans Baier
9a94e835c3 sockit: Add an option to plug in an UART via the GPIO daughter board 2021-02-10 14:52:19 +07:00
Michael Betz
7442c2dada vc707.py: clk156 add missing constraint 2021-02-08 19:04:01 -08:00
Florent Kermarrec
fef9dd036a platforms/de0nano: directly use JP1 connector for serial pins. 2021-02-08 09:52:26 +01:00
enjoy-digital
ea58ef94a7
Merge pull request #170 from hansfbaier/master 
arrow_sockit: add support for MiSTer XS SDRAM modules
 2021-02-04 16:44:58 +01:00
Jan Kowalewski
cdff5e3ca3 nexys_video: enable symbiflow toolchain 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-02-03 14:52:54 +01:00
Hans Baier
c64e13f687 arrow_sockit: add support for MiSTer XS SDRAM modules 2021-02-03 09:37:03 +07:00
Sergiu Mosanu
a1d830566a added ddr4_sdram_c1 constraints 2021-02-01 12:22:41 -05:00
Florent Kermarrec
7c48af9b50 tec0117: get SDRAM working and increase sys_clk_freq to 25MHz. 
./tec0117.py --build --load

Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb  1 2021 13:09:35
 BIOS CRC passed (5abceb2e)

 Migen git sha1: 40b1092
 LiteX git sha1: f324f953

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 25MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		24KiB
SRAM:		4KiB
L2:		0KiB
SDRAM:		8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB
   Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 5MiB/s
   Read speed: 6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list

Available memory regions:
ROM       0x00000000 0x6000
SRAM      0x01000000 0x1000
SPIFLASH  0x80000000 0x1000000
MAIN_RAM  0x40000000 0x800000
CSR       0x82000000 0x10000

litex> mem_test 0x40000000 0x800000

Memtest at 0x40000000 (8MiB)...
  Write: 0x40000000-0x40800000 8MiB
   Read: 0x40000000-0x40800000 8MiB
Memtest OK

litex>
 2021-02-01 13:32:01 +01:00
Florent Kermarrec
6cce07d9db tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios. 2021-02-01 13:31:44 +01:00
Florent Kermarrec
0831b33285 tec0117: fix copyrights. 2021-02-01 13:31:39 +01:00
Hans Baier
5e4b29c0b5 sockit: Fix cable name, default to jtag_atlantic 2021-02-01 11:48:06 +07:00
enjoy-digital
601c297c8f
Merge pull request #164 from rdolbeau/ztex213 
Support file for the ZTEX USB-FPGA Module 2.13
 2021-01-30 21:43:07 +01:00
Guillaume REMBERT
31df53ef0a Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work) 2021-01-30 13:19:08 +01:00
Romain Dolbeau
027e57b851 Support file for the ZTEX USB-FPGA Module 2.13 2021-01-30 05:19:18 -05:00
Florent Kermarrec
abccd12058 tec0117: add initial SDRAM support for the embedded SDRAM of the SIP. 
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
 2021-01-29 22:28:40 +01:00
Vadzim Dambrouski
345feddce9 ECPIX-5: ddram: Add missing address pin. 
Fixes #161
 2021-01-29 16:03:43 +03:00
Florent Kermarrec
7525b8772f platforms/fpc_iii: avoid dummy pin on ethernet.rst_n. 
rst_n is optional in LiteEth's PHYs.
 2021-01-29 09:33:33 +01:00
Florent Kermarrec
19767e1a2a platforms/fpc_iii: avoid using dummy pin on odt. 
Now possible with 2f5784432d.
 2021-01-29 09:30:54 +01:00
Florent Kermarrec
6c6d8a1393 platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance. 2021-01-29 08:41:10 +01:00
Sergiu Mosanu
1916677dc9 use VREF constraint for DDR4 C0 2021-01-28 19:58:38 -05:00
Gary Wong
4e5bb1bf1e Add FPC-III board support. 
FPC-III is the Free Permutable Computer; details on the board are
available from:

    https://repo.or.cz/fpc-iii.git
 2021-01-28 09:51:42 -07:00
Florent Kermarrec
aa20fca1f1 ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3. 2021-01-28 14:25:16 +01:00
enjoy-digital
691bfd8b70
Merge pull request #159 from euryecetelecom/master 
Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
 2021-01-28 14:01:01 +01:00
Alessandro Comodi
bd716d956f netv2: add device variant to allow 100T as well 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-28 13:19:53 +01:00
Guillaume REMBERT
9beba7209d Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration 2021-01-28 12:00:28 +01:00
Sergiu Mosanu
84656a9c2e re-compare and adjust to u250 2021-01-26 23:03:09 -05:00
Kaz Kojima
c3fa0eac8b Add colorlight i5 board support 2021-01-27 11:44:59 +09:00
Florent Kermarrec
537f494cbb arrow_sockit: review/harmonize with others boards. 2021-01-25 09:14:46 +01:00
Florent Kermarrec
4adc1b14c4 platforms/de0nano: use separator for connectors. 2021-01-25 08:58:12 +01:00
enjoy-digital
bbaa2fdc98
Merge pull request #149 from hansfbaier/master 
Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
 2021-01-25 08:55:48 +01:00
enjoy-digital
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash 
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
 2021-01-24 21:22:35 +01:00
enjoy-digital
8132f9f65b
Merge pull request #154 from euryecetelecom/master 
Fix SDCard issue when no SDCard inserted in ECPIX5 board.
 2021-01-24 21:14:58 +01:00
Blake Smith
cae51c0c24 ULX3S: Make spiflash optionally accessible from the SoC, and bootable 2021-01-23 14:44:26 -06:00
Hans Baier
aa771e9ff4 de0-nano: add connectors 2021-01-23 20:18:15 +07:00
Hans Baier
c9f0745d54 sockit: add board definitions for Terasic SocKit 2021-01-23 20:17:38 +07:00
Guillaume REMBERT
b386ee5059 Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence. 
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
 2021-01-20 18:02:13 +01:00
Vadim Kaushan
a678672fc9
ecpix5: add option to select ECP5 device 2021-01-19 01:22:52 +03:00
Sergiu Mosanu
7a738245af fix bitstream problem 2021-01-14 21:53:25 -05:00
Sergiu Mosanu
5a73eb0b6d initiate target and platform for alveo_u280 board 2021-01-14 18:35:43 -05:00
enjoy-digital
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard 
genesys2: LiteSDCard support
 2021-01-07 08:12:24 +01:00
Gabriel Somlo
4eb0026a69 genesys2: add "rst" and "cd" signals to (spi-)sdcard records 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:10:13 -05:00
Geert Uytterhoeven
4a95b94dbf platforms/ecp5: Fix slewrate configuration 
When building linux-on-litex-vexriscv for OrangeCrab:

    Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
    Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
    Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
    Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)

Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW".  Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2021-01-04 17:08:51 +01:00
Florent Kermarrec
93779ecb95 platforms/colorlight_5a_75b: revert toolchain args. 
Useful to do tests with Diamiond.
 2020-12-29 14:22:42 +01:00
enjoy-digital
f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0 
add colorlight v8.0 PCB
 2020-12-29 14:20:29 +01:00
Florent Kermarrec
b67b18caad qmtech_wukong: review/cleanup platform. 2020-12-29 14:10:49 +01:00
la6m
3e6b934961 add colorlight v8.0 PCB 2020-12-29 13:52:13 +01:00
Shinken Sanada
4b721eded7 add QmTech Wukong board support. 2020-12-29 13:20:42 +01:00
Florent Kermarrec
9beaf25822 nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue. 2020-12-24 10:15:29 +01:00
Sahaj Sarup
2a04c5c74e nexys4ddr: add support for litexvideo VGA Terminal 
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.

The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
 2020-12-23 02:24:18 +05:30
Florent Kermarrec
ec4ccc9fa5 platforms/xcu1525: fix ddram 1/2/3 pinout. 
DDR4 now validated successfully with LiteDRAM on the 4 channels.
 2020-12-11 13:58:26 +01:00
Robert Winkler
18337cdf25 targets/arty: sync with litex repository 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-12-07 17:32:40 +01:00
Alessandro Comodi
f66860c201 zybo_z7: fix clock pin constraint 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-12-07 16:46:20 +01:00
Gwenhael Goavec-Merou
8d1095224f add support for redpitaya14/16 2020-11-26 06:54:11 +01:00
David Shah
11fa5c34ac nexus: Allow selection of toolchain 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-25 09:45:25 +00:00
Nathaniel R. Lewis
389b623fe2 targets/litefury: new target 
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.

https://rhsresearch.com/collections/rhs-public/products/litefury
 2020-11-19 21:52:14 -08:00
Florent Kermarrec
27f60b2e93 add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated). 
Pinout from https://github.com/360nosc0pe project.
 2020-11-13 12:20:15 +01:00
Florent Kermarrec
843e724e3d targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe. 2020-11-12 16:39:42 +01:00
Florent Kermarrec
9f11bfb0d1 qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets. 2020-11-12 14:33:45 +01:00
enjoy-digital
31eb74dc2d
Merge pull request #122 from baselsayeh/master 
add Qmtech EP4CE15 coreboard support
 2020-11-12 14:27:49 +01:00
Florent Kermarrec
46e8a957fe platforms/zybo_z7: fix default_clk typo. 2020-11-12 14:26:36 +01:00
Florent Kermarrec
ac075f18c7 platforms/crosslink_nx_evn/vip: add default_clk. 2020-11-12 14:26:17 +01:00
Basel Sayeh
0fc67ddfdb
update copyright 2020-11-12 15:25:39 +02:00
Florent Kermarrec
a4d05522d4 platforms/ice40/ecp5: add toolchain parameter with default to trellis (ECP5) or icestorm (iCE40). 
Required to simplify simple.py target and use trellis/icestorm as default toolchain.
 2020-11-12 13:33:30 +01:00
Basel Sayeh
1b1ed5ebf1
add Qmtech EP4CE15 coreboard support 2020-11-12 01:56:36 +02:00
davidcorrigan714
97b64d16a6 Lattice NX PLL Support 2020-11-08 20:34:46 -06:00
Florent Kermarrec
1f52fbaca6 xcu1525: fix last ddram channel numbering. 2020-11-06 10:48:26 +01:00
Florent Kermarrec
2da4eabffe platforms/icebreaker: fix refactoring typo. 2020-11-04 09:30:01 +01:00
Florent Kermarrec
c093d0d0fc platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:48:57 +01:00
Kevin Mehall
d1c9cc7553 Add LFE5U-12F device for ULX3S 2020-11-01 23:45:32 +00:00
Florent Kermarrec
d626861e95 platforms/acorn_cle_215: add serial_io (on P2). 2020-10-29 12:10:12 +01:00
enjoy-digital
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip 
Add CrossLink-NX VIP board platform and target
 2020-10-22 11:03:47 +02:00
Florent Kermarrec
a38c1e7062 mist: add copyrights. 2020-10-22 10:48:58 +02:00
David Shah
20720693c4 crosslink_nx_vip: Add HyperRAM support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-22 09:15:40 +01:00
David Shah
b278d8bccc Add CrossLink-NX VIP board platform and target 2020-10-22 09:15:35 +01:00
YanekJ
4541c39e94 Initial support for the MIST board (https://github.com/mist-devel/mist-board/wiki) 2020-10-17 12:28:22 +02:00
Florent Kermarrec
982cfd5ad5 platforms/xcu1525: fix ddram constraints, add clk300 constraints for all channels. 2020-10-13 11:50:36 +02:00
Florent Kermarrec
ddf7038c78 ulx3s: add 1.7 and 2.0 revisions support. 2020-10-12 13:23:26 +02:00
Bryan Jacobs
3b11e60fb1 Update ULX3S SD pins for revision 2.0 2020-10-11 14:17:48 +11:00
Florent Kermarrec
55da8b867a platforms/zedboard: minor cleanups to uniformize with other platforms. 2020-10-07 11:25:20 +02:00
Michael Betz
e225cbd28f add zedboard platform to CI 2020-10-06 11:35:03 -07:00
Michael Betz
8ee20a3f30 clean up imports 2020-10-06 11:24:34 -07:00
Michael Betz
865c2bd98c zedboard platform: clean up 
* remove unused code
  * remove oled integration code
  * openocd = default programmer
 2020-10-06 11:00:36 -07:00
Michael Betz
12aed44577 add zedboard platform 2020-10-06 00:28:54 -07:00
enjoy-digital
79ef091a06
Merge pull request #110 from pepijndevos/gowin 
Add initial support for Trenz TEC0117 board
 2020-10-05 19:50:09 +02:00
enjoy-digital
2ee32f2a15
Merge pull request #109 from geertu/orangecrab-Fix-r0.1-user_led-mapping 
orangecrab: Fix r0.1 user_led mapping
 2020-10-02 09:40:41 +02:00
enjoy-digital
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc 
crosslink_nx_evn: Improve documentation on UART jumpers
 2020-10-02 09:40:04 +02:00
Pepijn de Vos
81e4f1f158 add initial support for Trenz TEC0117 board 2020-09-30 14:01:36 +02:00
Geert Uytterhoeven
b2e34f5faf orangecrab: Fix r0.1 user_led mapping 
On r0.1, all three user_leds are mapped to the same pin.
Fix this by mapping them to the pins connected to the individual
channels of the RGB LED, to match the comments, the schematics, and the
spirit of r0.2.

Untested on real hardware (I have r0.2 only).

Fixes: c94cbae0c0 ("orangecrab: add user_led (RGB leds), DFUProg and --load support.")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-09-25 10:33:21 +02:00
Florent Kermarrec
c6610b4a3f platforms/xcu1525: update ddram1/2/3 pinout. 
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMMx.xdc
 2020-09-20 21:07:00 +02:00
Florent Kermarrec
e5a144e9cd platforms/xcu1525: update ddram0 pinout. 
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc.
 2020-09-19 23:28:34 +02:00
Florent Kermarrec
8ffb86c0dc platforms/fk33/xcu1525: define pcie_x2/x4/x8/x16. 2020-09-19 22:37:05 +02:00
David Shah
8a9fd02768 crosslink_nx_evn: Improve documentation on UART jumpers 
Signed-off-by: David Shah <dave@ds0.me>
 2020-09-05 09:58:28 +01:00
Florent Kermarrec
76ac4a69a8 rename forest_kitten_33 platform/target to fk33. 2020-09-04 20:05:18 +02:00
Florent Kermarrec
979fee7517 forest_kitten_33: add pcie. 2020-09-04 20:02:43 +02:00
Florent Kermarrec
ad48728160 xcu1525: update headers (were still using old format). 2020-09-04 19:59:09 +02:00
enjoy-digital
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie 
alveo_u250: Add PCIe x4 support
 2020-09-04 19:22:48 +02:00
enjoy-digital
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0 
Add support for 5A-75E V6.0 board
 2020-09-04 19:21:02 +02:00
David Shah
ae6a052e57 alveo_u250: Add PCIe x4 support 
Based on the implementation in xcu1525

Signed-off-by: David Shah <dave@ds0.me>
 2020-09-04 14:20:04 +01:00
Florent Kermarrec
2eda9d0252 xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested). 2020-09-04 11:34:33 +02:00
Florent Kermarrec
7b6b71d4e3 xcu1525: add initial DDR4 support in C0 (untested). 2020-09-03 19:48:23 +02:00
Florent Kermarrec
51e881d1ff add minimal xcu1525 support (VCU1525 or BCU1525 boards). 2020-09-03 19:06:43 +02:00
DerFetzer
cc78574297 targets/colorlight_5a_75x: fix rx_data pin order for Ethernet PHY 0 2020-09-02 22:04:23 +02:00
DerFetzer
8b1fee0e66 Add support for 5A-75E V6.0 board 2020-09-01 17:02:17 +02:00
Florent Kermarrec
beccecf59f orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM. 
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.

Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.

See https://github.com/enjoy-digital/litedram/issues/216.
 2020-08-28 20:01:54 +02:00
Florent Kermarrec
63b65e278c crosslink_nx_evn: update copyrights. 2020-08-24 22:33:58 +02:00
Piense
795e34aafd add initial Crosslink-NX support. 2020-08-24 16:47:38 +02:00
Florent Kermarrec
70594a5305 ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. 2020-08-24 09:05:58 +02:00
Florent Kermarrec
1781be166a general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
Florent Kermarrec
83d8b8d1b4 platforms/acorn_cle_215: integrated sdcard ios as extension. 2020-08-22 22:11:51 +02:00
connorwk
f328909578 Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header. 2020-08-09 16:27:41 -04:00
Pawel Sagan
d2cd6d4c0e arty: Change USB-uart and I2S Pmod configuration 
This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board).
 2020-08-05 11:54:25 +02:00
Pepijn de Vos
eba70377b7 add optional OLED peripheral to ULX3S target 2020-08-04 11:07:30 +02:00
Florent Kermarrec
929e55d7e6 platforms/trellisboard: add SDCard PMOD pins. 2020-07-29 09:07:55 +02:00
Florent Kermarrec
5fd3e8dbcd ecpix5: add SDCard. 
Validated with Linux-on-LiteX-VexRiscv.
 2020-07-28 17:45:49 +02:00
Florent Kermarrec
760b8ff93a arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. 2020-07-24 16:29:35 +02:00
Florent Kermarrec
9730c6f722 platforms/de10nano: use additional sdram constraints required for HalfRate. 2020-07-24 12:27:36 +02:00
Florent Kermarrec
7399d13cef paltforms/de10nano/sdram: enable fast input/output on dq. 2020-07-24 11:27:25 +02:00
Florent Kermarrec
b4b1ab8621 paltforms/de10nano: simplify IO constraints (for consistency with others platforms). 2020-07-24 09:03:35 +02:00
enjoy-digital
89c5bf43cf
Merge pull request #92 from rob-ng15/master 
Enable use of HalfRateGENSDRPHY on de10nano
 2020-07-24 08:49:09 +02:00
Florent Kermarrec
1e1589a514 zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). 
This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
 2020-07-23 17:45:21 +02:00
rob-ng15
cf9839307f
Add Misc 
Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram
 2020-07-23 14:40:04 +01:00
Florent Kermarrec
8a3b453e2f add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. 2020-07-23 15:26:22 +02:00
Florent Kermarrec
e723bef49a platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). 
Also use pmod connector names in i2s_pmod and sdcard_pmod.
 2020-07-22 14:41:09 +02:00
Florent Kermarrec
19d0b95867 platforms/targets: keep in sync with litex. 2020-07-22 08:53:49 +02:00
Florent Kermarrec
0ee4b215b9 trellisboard/ulx3s: fix sdcard slewrate. 2020-07-21 15:23:08 +02:00
Florent Kermarrec
7efa1c37a1 platforms/arty: add missing pullups on sdcard. 2020-07-21 15:22:39 +02:00
Florent Kermarrec
2ce24df76d platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3). 2020-07-18 22:18:41 +02:00
Florent Kermarrec
135c387155 platforms/ulx3s: add assertion for supported devices. 2020-07-17 12:04:06 +02:00
Florent Kermarrec
851378f0a9 platforms/trellisboard: move ddram_vtt_en. 2020-07-17 12:03:37 +02:00
Vamsi K Vytla
44ad902aad platforms/kc705.py: LPC DP0_M2C/C2M diff pair 2020-07-13 10:26:17 -07:00