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f4ae21a7a2
zcu104: fix copyrights.
2020-03-09 09:24:06 +0100
5031c11d57
mercury_xu5: add missing copyrights.
2020-03-09 09:23:08 +0100
8c535d15f2
platforms/mercury_xu5: replace ' with ".
2020-03-09 09:21:27 +0100
dc1371108d
Merge pull request #52 from antmicro/jboc/mercury-xu5
2020-03-09 09:11:15 +0100
2b1b9684de
targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset.
2020-03-07 18:25:26 +0100
9416ddd84a
targets/icebreaker: simplify arguments and make it closer to others targets.
2020-03-06 15:11:33 +0100
992f7066fa
targets/icebreaker: simplify leds.
2020-03-06 13:42:26 +0100
682316214c
targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy.
2020-03-06 13:35:29 +0100
f777d4b08c
targets/icebreaker: +x
2020-03-05 23:11:35 +0100
6f517ad1d6
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 10:57:59 +0100
d002059e0b
add Enclustra Mercury XU5 board
2020-03-02 15:36:43 +0100
7776764580
Merge pull request #51 from esden/icebreaker
2020-03-05 10:35:50 +0100
745c99ba14
icebreaker: Updated to build on newer litex. Disabled bios building.
2020-03-05 00:11:19 -0800
3ac9d927a9
targets: icebreaker: Minor style fixes.
2020-02-05 14:49:05 -0800
738967176c
targets: icebreaker: set the boot address to point to SPI flash
2020-02-03 15:07:08 +0800
093e4913c4
targets: icebreaker: hack to get boot working
2020-02-03 13:33:29 +0800
77b780eb4b
targets: icebreaker: switch to single SPI
2020-02-03 13:15:41 +0800
e6dcdc31ed
targets: icebreaker: fix cpu and add spi flash
2020-02-03 13:07:56 +0800
0185095782
targets: icebreaker: fix argument parsing for cpu
2020-02-03 12:39:13 +0800
f0dd31f6c8
target: targets: add crg and begin getting it working
2020-02-03 12:32:16 +0800
ce9b67e2ee
Added icebreaker platform and target.
2020-02-02 18:27:09 -0800
fd6c555117
Merge pull request #50 from TomKeddie/tomk_20200228_colorlight_connectors
2020-02-28 19:11:30 +0100
7b4ca20ff4
platforms.colorlight_5a_75b: add J1-J8 connectors
2020-02-28 06:09:44 -0800
be5ed35871
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:46:54 +0100
b44885d222
vc707: fix copyrights (Michael Betz is the initial author)
2020-02-28 08:39:52 +0100
b89af28a05
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 12:58:39 +0100
edcc2cf63e
test_targets: add vc707, zcu104, vcu118 and colorlight_5a_75b
2020-02-27 11:17:28 +0100
aaa10c69eb
platforms/colorlight_5a_75b: add default_clk_name/period
2020-02-27 11:16:49 +0100
d8de4fbdfb
platforms/targets: keep in sync with LiteX
2020-02-27 11:06:53 +0100
18f65a7f9d
platforms/kc705: cleanup ddram.
2020-02-27 11:06:35 +0100
d4460c11a5
platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm.
2020-02-27 10:43:41 +0100
58f588f69e
platforms/zcu104/ddram: add PRE_EMPHASIS/EQUALIZATION settings
2020-02-27 10:43:01 +0100
d87b8b3c66
zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
2020-02-27 10:05:17 +0100
8ecfb13f3c
zcu104: add copyrights
2020-02-27 09:57:26 +0100
22b0449509
Merge pull request #47 from antmicro/zcu104
2020-02-27 09:51:54 +0100
608541d5b8
add ZCU104 board
2020-02-25 12:21:26 +0100
e516ff3452
vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:51 +0100
9d2ca50c5f
kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:15:12 +0100
83d2c71099
platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks
2020-02-25 18:32:42 +0100
4a84e9b08a
targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool
2020-02-25 12:47:08 +0100
f279fe9d33
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
2020-02-25 10:35:18 +0100
3581df5af6
vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported)
2020-02-25 09:41:53 +0100
88a1f80db1
vc707/vcu118: use proper copyrights
2020-02-25 09:03:52 +0100
e34654fc8c
Merge pull request #46 from fei-g/master
2020-02-25 08:46:52 +0100
373e74f435
add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
2020-02-24 14:20:47 -0500
133f735e1f
Merge pull request #45 from trabucayre/fix_colorlight5A-75B_SDRAM
2020-02-24 08:30:18 +0100
2cf4e084ec
platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
2020-02-23 10:01:41 +0100
f72e7bd314
Merge pull request #41 from lromor/fix-wrong-import
2020-02-12 18:48:13 +0700
ec30cc05c3
Changed wrong imports for fomu board.
2020-02-12 12:40:07 +0100
c94360c2e0
targets: avoid direct use of mem_decoder.
2020-02-11 21:59:42 +0100
4edf196911
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:45:35 +0100
83c48946ad
test/test_targets: make sure all platforms are tested.
2020-02-03 10:04:02 +0100
c3d8c7462d
test/test_targets: update
2020-02-03 09:44:22 +0100
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
2020-02-03 09:30:57 +0100
7a24406b2e
targets: fomu: fix compatibility for when a cpu is added
2020-02-03 08:57:56 +0800
0627f55dca
de10nano: cleanup a bit, rename SDRAMSoC to MiSTerSDRAMSoC and argument to --with-mister-sdram to make it clear that it's using the MiSTer SDRAM extension board.
2020-01-31 09:29:02 +0100
cf9a9ff91b
de10nano: update copyrights, remove trailing whitespaces
2020-01-31 09:13:36 +0100
4f85d50ff5
Merge pull request #39 from sajattack/de10nano
2020-01-31 09:08:19 +0100
36e1f1fe75
rename sw to user_sw
2020-01-30 05:01:46 -0800
1631b071c3
finish up sdram, passes memtest
2020-01-30 03:41:44 -0800
5091a1b40a
WIP sdram module option
2020-01-29 13:59:57 -0800
3a6a9258ce
add de10 nano board
2020-01-25 03:00:57 -0800
2ec6bc0bdc
colorlight_5a_75b: add disclaimer
2020-01-23 14:13:13 +0100
55c0b781e4
colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt)
2020-01-23 13:16:36 +0100
4fb89fc9c5
colorlight_5a_75b: set RGMII tx/rx_delay to 0ns in the FPGA (added by PCB/PHY)
2020-01-23 09:39:48 +0100
dcc65b347d
targets/colorlight_5a_75b: switch to SoCCore, CPU and Etherbone working :)
2020-01-22 15:56:21 +0100
c07e4a6b3a
colorlight_5a_75b: fix rst_n
2020-01-22 14:57:48 +0100
8da8ed7a0e
colorlight_5a_75b/v7.0: update eth_clocks/rx pinout, remove FIXME
2020-01-22 14:56:17 +0100
bb805999cb
platforms/colorlight_5a_75b: fix 6.1 used_led_n/user_btn_n thanks @smunaut
2020-01-22 12:43:37 +0100
43badd162e
colorlight_5a_75b/v6.1: add led/btn and remove FIXME on sdram now that clarified
2020-01-22 11:04:05 +0100
1d9e349093
partner: add colorlight_5a_75b initial support
2020-01-22 09:20:38 +0100
07067301d5
targets/linsn_rv901t: cleanup arguments
2020-01-22 09:04:28 +0100
8113b491db
aller/nereid/tagus: update litepcie
2020-01-21 21:26:23 +0100
684c1640bb
add Linsn RV901T support
2020-01-18 21:40:04 +0100
0e4569a48a
platforms/camlink_4k: remove #!/usr/bin/env python3
2020-01-18 21:35:18 +0100
e72cd1468c
platforms/ac701: fix eth indent
2020-01-18 21:34:50 +0100
908539d49f
targets/nexys4ddr: fix typo
2020-01-17 13:15:22 +0100
bb99a8dd0c
targets/kcu105: remove main_ram_size_limit
2020-01-17 12:09:53 +0100
84164f8fab
Copying .gitignore from LiteX repo.
2020-01-16 22:39:13 +1000
eca9bf10ae
mimas_v7: cleanup, make it similar to others boards
2020-01-16 11:23:30 +0100
54f39b600a
mimas_a7: fix copyrights
2020-01-16 11:02:11 +0100
8d298951a8
Merge pull request #37 from feliks-montez/master
2020-01-16 11:00:32 +0100
f9619c4a8f
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
2020-01-16 10:51:35 +0100
fd1e655700
targets: cleanup EthernetSoC
2020-01-16 10:28:09 +0100
0e6ef06494
Merge branch 'feature/add-mimas-a7-support'
2020-01-14 23:31:35 -0500
206ec34551
platforms/mimas_a7: add support
2020-01-14 23:31:03 -0500
9f1c3305b6
targets/mimas_a7: add support
2020-01-14 23:30:49 -0500
223d8d832e
test_targets: add kx2
2020-01-13 17:22:49 +0100
50d550c911
kx2: cleanup, fix copyright
2020-01-13 17:22:33 +0100
3811b58f32
Merge pull request #36 from Marrkson/master
2020-01-13 17:07:16 +0100
c109b36fb9
travis: update/fix
2020-01-13 17:00:01 +0100
028d4a78aa
targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
2020-01-13 15:20:37 +0100
13e5ca03a5
ADD: KX2 and DDR3 support
2020-01-13 14:21:54 +0100
beccf670e5
hadbadge: fix _CRG
2020-01-11 10:46:23 +0100
15f3457aea
platforms/de0nano/serial: add gpio names in comment
2020-01-10 18:53:52 +0100
94ba343daf
targets/ac701: cpu_reset is active high
2020-01-10 18:53:14 +0100
ab01f70e5c
platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq
2020-01-09 21:56:01 +0100
7afe3dc674
platforms/targets: sync with litex
2020-01-09 21:10:59 +0100
4192b20f09
targets: cleanup Altera CRGs
2020-01-09 19:46:39 +0100
9e9fc5ef78
platforms: always use 1e9/clk_freq for default_clk_period
2020-01-09 19:28:50 +0100
Florent Kermarrec
Jędrzej Boczar
Piotr Esden-Tempski
Sean Cross
Tom Keddie
Piotr Binkowski
Fei Gao
Gwenhael Goavec-Merou
Leonardo Romor
Paul Sajna
Tim 'mithro' Ansell
Feliks
Mark