Florent Kermarrec
98cf103c65
vpi: fix and simplify windows simulation (ends of msg were ignored)
2015-05-13 03:03:34 +02:00
Florent Kermarrec
88a406ebec
migen/genlib/misc: replace Timeout with WaitTimer from artiq
2015-05-12 16:14:58 +02:00
William D. Jones
fe6eef7069
Windows simulation support
2015-05-09 21:09:52 +08:00
Alain Péteut
96bff77c36
add examples tests
2015-05-01 00:50:17 +08:00
Florent Kermarrec
1cbc468bda
migen/actorlib/packet: add Packetizer and Depacketizer
2015-04-28 18:44:05 +02:00
Florent Kermarrec
0da9311d70
migen/genlib: avoid use of floating point in reverse_bytes
2015-04-27 21:04:18 +02:00
Florent Kermarrec
3ce5ff3722
migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer)
2015-04-27 15:14:38 +02:00
Florent Kermarrec
f976b1916a
migen/actorlib/misc: add BufferizeEndpoints
...
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
Florent Kermarrec
e96ba1e46f
migen/genlib/misc: add reverse_bytes
2015-04-27 15:08:10 +02:00
Florent Kermarrec
73a1687562
migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?)
2015-04-24 13:24:52 +02:00
Florent Kermarrec
67702f25ab
migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb)
2015-04-24 12:54:08 +02:00
Florent Kermarrec
bc30fc57e7
migen/fhdl: give explicit names to syntax specialization when asic_syntax is used
2015-04-24 12:14:14 +02:00
Florent Kermarrec
61c3efc5f5
migen/test: rename asic_syntax to test_syntax and simplify
2015-04-24 12:00:46 +02:00
Guy Hutchison
7ec0ecae11
test: add test for asic_syntax
2015-04-22 12:29:07 +08:00
Guy Hutchison
28dde1e38f
fhdl/verilog: add flag to produce ASIC-friendly output
2015-04-21 09:52:14 +08:00
Florent Kermarrec
3f15699964
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
2015-04-13 21:47:55 +02:00
Florent Kermarrec
d83e170872
global: more pep8
...
we will have to continue the work... volunteers are welcome :)
2015-04-13 21:33:44 +02:00
Florent Kermarrec
f97d7ff44c
global: pep8 (E261, E271)
2015-04-13 21:21:30 +02:00
Florent Kermarrec
5f225c0475
global: pep8 (E225)
2015-04-13 21:11:13 +02:00
Florent Kermarrec
37ef9b6f3a
global: pep8 (E231)
2015-04-13 20:50:03 +02:00
Florent Kermarrec
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
Florent Kermarrec
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
Florent Kermarrec
a2c17cdcef
Merge branch 'master' of https://github.com/m-labs/migen
2015-04-13 09:37:03 +02:00
Sebastien Bourdeauducq
c6904f9d63
sim: fix to support ConvOutput
2015-04-12 14:06:57 +08:00
Florent Kermarrec
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
...
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
Sebastien Bourdeauducq
a69741b24e
forgot other cordic files
2015-04-09 12:00:20 +08:00
Sebastien Bourdeauducq
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
Sebastien Bourdeauducq
90c5512b25
genlib: remove cordic (will live in pdq2)
2015-04-08 11:35:53 +08:00
Robert Jordens
25e4d2a2db
decorators: remove deprecated semantics
2015-04-05 18:47:45 +08:00
Robert Jordens
8798ee8d73
decorators: fix stacklevel, export in std
2015-04-05 18:47:45 +08:00
Robert Jordens
f26ad97624
decorators: fix ControlInserter
2015-04-05 14:44:03 +08:00
Sebastien Bourdeauducq
db76defa2a
fhdl/visit: remove TransformModule
2015-04-04 20:12:22 +08:00
Robert Jordens
e702fb7727
decorators: fix class/instance logic
2015-04-04 19:16:58 +08:00
Robert Jordens
4091af69fd
fhdl/decorators: make the transform logic more idiomatic
...
* the transformers work on classes and instances.
you can now do just do:
@ResetInserter()
@ClockDomainRenamer({"sys": "new"})
class Foo(Module):
pass
or:
a = ResetInserter()(FooModule())
* the old usage semantics still work
* the old DecorateModule is deprecated,
ModuleDecorator has been refactored into ModuleTransformer
(because it not only decorates things)
2015-04-04 19:16:50 +08:00
Florent Kermarrec
ce0ff1e341
remove use of _r prefix on CSRs
2015-04-02 12:15:56 +02:00
Florent Kermarrec
d67f24ddc7
migen/bank/description: remove support of _r prefix in CSRs
2015-04-02 12:13:22 +02:00
Sebastien Bourdeauducq
c169f0b189
Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
...
This reverts commit f03aa76292
.
2015-03-30 19:41:16 +08:00
Sebastien Bourdeauducq
dc88295338
Revert "migen/fhdl: pass fdict filename --> contents to specials"
...
This reverts commit ea04947519
.
2015-03-30 19:41:13 +08:00
Sebastien Bourdeauducq
b1c811a3d1
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
...
This reverts commit 95cfc444e6
.
2015-03-30 19:41:04 +08:00
Florent Kermarrec
95cfc444e6
migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
2015-03-30 11:37:59 +02:00
Florent Kermarrec
ea04947519
migen/fhdl: pass fdict filename --> contents to specials
2015-03-30 11:37:57 +02:00
Florent Kermarrec
f03aa76292
migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
2015-03-30 11:37:55 +02:00
Robert Jordens
14b1da4018
test_actor: add unittests for SimActor
...
* also implicitly tests for the access of signals during simulation that are
not referenced in any statements
* before, if the busy signal is never used, it is stripped
and could not be accessed in simulation
2015-03-21 10:02:10 +01:00
Robert Jordens
5f045b7649
sim: keep track of unreferenced items
...
* items that are never referenced in any statements do not end up in the
namespace or in the verilog
* this memorizes items if they can not be found in the namespace and keeps
track of their values
2015-03-21 10:02:10 +01:00
Sebastien Bourdeauducq
7fa1cd72a8
fhdl/verilog: fix dummy signal initial event
2015-03-19 00:24:30 +01:00
Florent Kermarrec
5a9afee234
fhdl/specials/memory: use $readmemh to initialize memories
2015-03-18 15:27:01 +01:00
Florent Kermarrec
c0fb0ef600
fhdl/verilog: change the way we initialize reg: reg name = init_value;
...
This allows simplifications (init in _printsync and _printinit no longer needed)
2015-03-18 15:05:26 +01:00
Florent Kermarrec
ea9c1b8e69
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
...
This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
Florent Kermarrec
2fc2f8a6c0
migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)
2015-03-18 14:41:43 +01:00
Sebastien Bourdeauducq
bdc47b205a
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
...
This breaks simulations, and we will try to use the "reg name = value" syntax instead.
This reverts commit e946f6e453
.
2015-03-18 12:08:25 +01:00
Florent Kermarrec
89fefef3f8
genlib/io: add optional external rst to CRG
2015-03-17 16:22:22 +01:00
Florent Kermarrec
b7d7fe1a4c
fhdl/special: add optional synthesis directive (needed by Synplify Pro)
2015-03-17 14:59:05 +01:00
Florent Kermarrec
9adf3f02f2
fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
...
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
Florent Kermarrec
e946f6e453
fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)
2015-03-16 23:47:07 +01:00
Florent Kermarrec
69ce6dd48c
migen/genlib/io: add DDRInput and DDROutput
2015-03-16 22:47:13 +01:00
Sebastien Bourdeauducq
beeaefccea
move pytholite to separate repos
2015-03-14 22:48:03 +01:00
Sebastien Bourdeauducq
c824379878
fhdl/visit: fix TransformModule
2015-03-14 17:45:11 +01:00
Sebastien Bourdeauducq
6a979a8023
mibuild: sanitize default clock management
2015-03-14 00:10:08 +01:00
Florent Kermarrec
ff266bc2ee
migen/genlib/io: add DifferentialOutput and Xilinx implementation
2015-03-12 19:30:57 +01:00
Florent Kermarrec
bf28664cb4
genlib/io.py: fix copy/paste error (thanks rjo)
2015-03-12 18:49:49 +01:00
Florent Kermarrec
c8ba8cde8e
migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild
2015-03-12 18:38:53 +01:00
Florent Kermarrec
8e09a86e4f
genlib/misc: add increment parameter to Counter
2015-03-09 20:20:25 +01:00
Florent Kermarrec
ebcea3c000
fhdl/module: use r.append() in _collect_submodules
2015-03-09 19:45:02 +01:00
Florent Kermarrec
ee1091f491
fhdl/module: avoid flushing self._submodules and create do_exit.
2015-03-09 17:17:21 +01:00
Sebastien Bourdeauducq
7b00141a0c
genlib/cordic: fix typos
2015-03-06 00:47:23 +01:00
Florent Kermarrec
06f3c46e35
genlib/misc: fix missing *args in Counter
2015-03-04 23:49:15 +01:00
Florent Kermarrec
7d68ecbd86
move dma_lasmi to MiSoC
2015-03-02 08:23:02 +01:00
Florent Kermarrec
58290f3c43
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
2015-03-01 22:04:20 +01:00
Florent Kermarrec
8f81ae6826
genlib/misc: add FlipFlop, Counter, Timeout
2015-03-01 16:33:46 +01:00
Florent Kermarrec
e82531cdf8
move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
2015-02-27 16:54:22 +01:00
Florent Kermarrec
225a2d4704
report cachesize in wishbone2lasmi
2015-02-27 14:12:13 +01:00
Florent Kermarrec
452c60e0c3
endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations)
2015-02-14 03:10:56 -08:00
Florent Kermarrec
319465445d
actorlib/structuring: fix eop generation in Pack
2015-02-14 03:07:18 -08:00
Florent Kermarrec
c7eba8f4c4
remove crc since each crc is specific. It's probably better to adapt code for each case.
2015-02-14 03:01:12 -08:00
Florent Kermarrec
7471b2a152
genlib/crc: use OrderedDict
2015-01-23 00:23:41 +08:00
Florent Kermarrec
2175a79c03
fhdl/std: add FinalizeError import
2015-01-23 00:23:41 +08:00
Florent Kermarrec
037ea05b1e
crc: modify CRCChecker to remove CRC and clean up
2014-12-21 17:24:52 +08:00
Sebastien Bourdeauducq
ae770c0f8c
bank: support direct mapping of CSRs on Wishbone
2014-11-30 22:28:39 +08:00
Yann Sionneau
ee928a8973
Wishbone DownConverter: Fix sel signal
2014-11-26 19:33:12 +08:00
Sebastien Bourdeauducq
4542de2c11
genlib/fsm: add NextValue to replace reg/reg_next/ce pattern
2014-11-25 17:16:21 +08:00
Sebastien Bourdeauducq
5801e5746b
fhdl/tools: do not attempt to rename sync clock domain if it does not exist
2014-11-21 14:51:05 -08:00
Sebastien Bourdeauducq
eb47f458dd
flow: endpoint description structure with packetized parameter
2014-11-20 22:31:56 -08:00
Sebastien Bourdeauducq
f5fc4b365f
actorlib/fifo: add buffered parameter
2014-11-20 18:46:54 -08:00
Jannis Harder
f847faf004
actorlib/fifo: fix no-op assignment due to .payload omission
2014-11-14 21:25:19 +01:00
Guy Hutchison
9f2f8d279d
add hamming-code gen/check lib
2014-11-06 18:19:59 -08:00
Sebastien Bourdeauducq
ccc9a0d334
test/test_size: fix slice comparison
2014-11-03 12:08:43 +08:00
Sebastien Bourdeauducq
dcedc4e6a5
actorlib/structuring/Pipeline: make 'busy' a signal
2014-11-01 21:48:02 +08:00
Florent Kermarrec
33c3a927c2
actorlib/structuring: add Pipeline
...
Pipeline enables easy cascading of dataflow modules.
DataFlowGraph can eventually use it to implement the
add_pipeline method to avoid duplicating things.
2014-11-01 21:47:00 +08:00
Florent Kermarrec
8db549a23d
actorlib/structuring: add Converter
...
Converter enables easy conversions of data width on dataflows.
It handles the 3 possibles cases:
- downconverter
- upconverter
- direct connection when data width are identical.
2014-11-01 21:43:52 +08:00
Sebastien Bourdeauducq
a7e4907724
Merge branch 'master' of github.com:m-labs/migen
2014-11-01 21:33:35 +08:00
Florent Kermarrec
bd1d456f5d
flow/actor, actorlib/structuring: add packet support
2014-11-01 21:22:46 +08:00
Florent Kermarrec
4d1b6da42f
bus/csr: add configurable address_width (needed more than 32 modules with CSR)
2014-11-01 21:22:11 +08:00
Florent Kermarrec
fcf2f7517c
crc: generate error asynchronously to avoid stalling the flow and simplify
2014-11-01 21:21:46 +08:00
Sebastien Bourdeauducq
a4782899f6
fhdl/verilog: fix tristate to instance connection
2014-10-29 18:18:17 +08:00
Yann Sionneau
286092b62e
Raise exception when not using correct boolean operators
2014-10-27 19:40:22 +08:00
Florent Kermarrec
86abb253c8
flow/actor/Endpoint: clean up __getattr__
2014-10-22 09:35:30 +08:00
Florent Kermarrec
37031e3a2f
DMAWriteController: fix Demultiplexer layout
2014-10-20 23:58:16 +08:00
Florent Kermarrec
07c33279c2
use new direct access on endpoints
2014-10-20 23:12:16 +08:00
Florent Kermarrec
ff688fb2f9
_Endpoint: allow direct access of payload elements
2014-10-20 23:09:56 +08:00
Florent Kermarrec
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
Florent Kermarrec
22507b117c
bank: add re to CSRStorage
...
being able to know when a register is updated is useful in many cases and avoid having to handle another register for that.
re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order.
2014-10-16 17:43:41 +08:00
Sebastien Bourdeauducq
15f67b30d0
genlib/fsm: make first fsm.act() the reset state, even when using after_*/before_* methods before fsm.act
2014-09-29 19:38:58 +08:00
Florent Kermarrec
e03091e7e2
add generic CRCEngine, CRC32, CRCInserter and CRCChecker
...
CRCEngine implements a generic and optimized CRC LFSR. It will enable generation of CRC generators and checkers.
CRC32 is an implementation of IEEE 802.3 CRC using the CRCEngine.
CRC32Inserter and CRC32Checker have been tested on an ethernet MAC.
2014-09-26 11:42:10 +08:00
Florent Kermarrec
a03570ccca
flow/actor: fix eop direction
2014-09-23 00:14:58 +08:00
Florent Kermarrec
66054af7bb
flow/actor: add packetized parameter for Sink and Source
2014-09-22 23:45:28 +08:00
Florent Kermarrec
967b73bef3
actorlib/structuring: add reverse parameter to Unpack and Pack
2014-09-22 23:41:40 +08:00
Sebastien Bourdeauducq
6c9810532b
genlib/fifo/SyncFIFOBuffered: replace not supported
2014-09-17 19:59:13 +08:00
Sebastien Bourdeauducq
4cacf97088
genlib/fifo: same 'level' semantics between SyncFIFOBuffered and FWFT SyncFIFO
2014-09-17 19:58:43 +08:00
Sebastien Bourdeauducq
264bc61e04
genlib/fifo: add replace command to sync FIFO
2014-09-10 21:19:15 +08:00
Sebastien Bourdeauducq
325ffdc6c6
actorlib/spi: remove unneeded import
2014-09-08 18:48:54 +08:00
Florent Kermarrec
c1e12c3346
actorlib/spi: remove EventManager from DMAController
2014-09-08 11:34:21 +08:00
Robert Jordens
0bac463780
sim/icarus: add vpi directory to module search path
...
This allows running the iverilog simulations from the migen top directory
without having to install the .vpi anywhere.
2014-09-07 16:49:12 +08:00
Robert Jordens
3d84a7a9de
cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic
2014-09-07 16:49:12 +08:00
Robert Jordens
11f58862db
test_cordic: stop spewing out numbers
2014-09-07 16:49:12 +08:00
Robert Jordens
4def6ec391
flow/network: replace NetworkX MultiDiGraph with simple implementation
2014-09-07 16:48:46 +08:00
Robert Jordens
683643266f
cordic: vivado is bad at inferring compact adder/subtractor logic
2014-09-04 15:25:34 +08:00
Robert Jordens
bd232f3f61
fhdl.structure: do not permit clock domain names that start with numbers
2014-08-18 11:01:56 +08:00
Robert Jordens
ac2e961618
fhdl.structure: remove unused imports
2014-08-18 11:01:56 +08:00
Robert Jordens
6036fffef2
Signal.__getitem__: raise TypeError and IndexError when appropriate
2014-08-18 11:01:56 +08:00
Robert Jordens
b3d69913cd
Signal.like: pass kwargs
2014-08-18 11:01:56 +08:00
Sebastien Bourdeauducq
60706e4b70
bus/dfi: add CKE and RESET_N
2014-08-09 10:56:08 +08:00
Sebastien Bourdeauducq
b124a98d92
genlib: add reset synchronizer
2014-08-06 19:38:37 +08:00
Sebastien Bourdeauducq
8baa957539
genlib/fifo: use synchronous memory read instead of additional register
...
The latter causes problems with InsertReset
2014-08-02 08:52:49 +08:00
Robert Jordens
44c6e524ba
migen.fhdl.structure: add Signal.like(other)
...
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
2014-07-24 23:52:59 -06:00
Florent Kermarrec
9fcea6e64a
migen/sim/generic: use kwargs to pass parameters to icarus.Runner
2014-07-24 10:17:54 -06:00
Robert Jordens
10d639d313
flow.plumbing: spelling
2014-07-19 14:29:51 -06:00
Robert Jordens
9266e10cae
flow.plumbing: make argument order consistent
2014-07-19 14:29:50 -06:00
Sebastien Bourdeauducq
ff1d105c7e
genlib/SyncFIFO: remove flush signal (use InsertReset instead)
2014-07-17 19:15:45 -06:00
Florent Kermarrec
ea0f4706f5
fsm: set reset_state as default state
2014-06-22 15:21:22 +02:00
Florent Kermarrec
4c426b36f3
fifo: add support for depth=2
2014-06-15 23:58:46 +02:00
Florent Kermarrec
70a2ee4368
migen/bank/description: add reset parameter to CSRStatus
2014-06-15 23:54:38 +02:00
Florent Kermarrec
9c1d95f6a4
wishbone2lasmi: fix wordbits computation
2014-05-01 13:32:18 +02:00
Sebastien Bourdeauducq
29ed3918cc
fhdl: forbid zero-length signals
2014-04-18 15:01:50 +02:00
Florent Kermarrec
86f852a5f1
wishbone2lasmi: support lasmim data_width < wishbone data_width
2014-04-18 15:00:53 +02:00
Sebastien Bourdeauducq
a36a208dd1
sim: use (mandatory) ncycles when starting a simulation with no active functions
2014-04-13 15:16:27 +02:00
Robert Jordens
ce378f47d3
test/SyncFIFOCase: better test bench termination
2014-04-07 00:05:08 +02:00
Robert Jordens
ac1363565d
genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered
2014-04-05 12:15:14 +02:00
Robert Jordens
9deddbdfbc
test/test_cordic: fix for new Simulation API
2014-03-24 15:01:44 -07:00
Robert Jordens
7649028bdc
test/support: fix default ncycles
2014-03-24 15:01:44 -07:00
Robert Jordens
0023b742e4
genlib/coding: gracefully handle flen(i) < 2
2014-03-19 18:12:27 -07:00
Robert Jordens
0836f2814a
bus/csr: new simulation api
2014-03-19 18:12:27 -07:00
Robert Jordens
b03d9f4c14
genlib/fifo: add flush, expose level in SyncFIFO
...
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.
Signed-off-by: Robert Jordens <jordens@gmail.com>
2014-03-15 23:10:46 -07:00
Sebastien Bourdeauducq
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
Sebastien Bourdeauducq
90f0dfad63
Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator
2014-01-27 23:58:46 +01:00
Sebastien Bourdeauducq
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
Sebastien Bourdeauducq
8f69d9b669
bank/eventmanager: add SharedIRQ
2014-01-06 22:13:06 +01:00
Robert Jordens
be1c8551d2
migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime)
2013-12-17 18:40:49 +01:00
Sebastien Bourdeauducq
a20688f777
fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems
2013-12-13 00:02:50 +01:00
Sebastien Bourdeauducq
adda930c68
fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
2013-12-12 17:37:31 +01:00
Sebastien Bourdeauducq
adffec35f6
utils/misc: add gcd_multiple function to compute GCD or any number of integers
2013-12-12 17:36:50 +01:00