Commit Graph

1349 Commits

Author SHA1 Message Date
Dolu1990 4dd650736f verilator++ 2022-02-04 16:36:11 +01:00
Dolu1990 378c0f8723 verilator++ 2022-02-04 16:20:43 +01:00
Dolu1990 8b2f107d46 verilator++ 2022-02-04 15:10:57 +01:00
Dolu1990 9c34a1fd2e updated related to JtagInstructionWrapper.ignoreWidth 2022-01-14 09:59:24 +01:00
Dolu1990 b8e904e43f syncronize golden model with dut for lrsc reservation 2022-01-10 19:55:28 +01:00
Dolu1990 6e77f32087 sim golden model lrsc reservation sync 2022-01-10 16:08:38 +01:00
Dolu1990 da53de360f Fix lrsc from last commit 2022-01-10 14:21:20 +01:00
Dolu1990 f46ad43f39
DataCache.withInternalLrSc reserved clearing fix 2022-01-10 13:39:41 +01:00
Dolu1990 34e5cafb75 Enable scala 2.13 compatibility 2021-12-20 09:38:35 +01:00
Dolu1990 a340798840
Update build.properties 2021-12-18 09:11:08 +01:00
Dolu1990 0539dd7110
SpinalHDL 1.6.2 2021-12-08 23:45:05 +01:00
Dolu1990 6c5908f7a3
Merge pull request #220 from BLangOS/patch-1
Update DebugPlugin.scala: Add optional readback of hardware breakpoint values
2021-11-15 09:25:00 +01:00
B.Lang 411d946a58
Update DebugPlugin.scala
Add readback of the hardware breakpoint values.
A new parameter is added to the plugin to switch readback on and off.
2021-11-11 12:12:23 +01:00
Dolu1990 acf14385d8 #213 disable pmp test with region overlapping 2021-10-22 17:24:51 +02:00
Dolu1990 9df704cad9
Merge pull request #213 from occheung/pmp-fix
PMP Plugin: Fix PMP region size & priority
2021-10-21 10:13:21 +02:00
occheung a3807660e3 pmp perm: revert to mux for priority 2021-10-19 11:40:39 +08:00
occheung df03c99ab2 pmp_setter: fix mask generation 2021-10-19 11:39:25 +08:00
Dolu1990 c3c3a94c5d IBusSimplePlugin can now use a Vec based buffer 2021-10-13 16:26:16 +02:00
Dolu1990 97a3c1955b VexRiscvSmpCluster add d$ i$ less arg 2021-10-11 11:57:39 +02:00
Dolu1990 35754a0709 Fix BrieySim (SpinalSim) 2021-09-25 13:28:37 +02:00
Dolu1990 8c0fbcadac Add BrieySim (SpinalSim) 2021-09-25 13:18:55 +02:00
Dolu1990 5f5f4afbf2 Briey revert RVC unwanted addition 2021-09-22 15:01:08 +02:00
Dolu1990 b807254759 Briey and Murax verilators now use FST instead of VCD 2021-09-22 12:57:27 +02:00
Dolu1990 65cda95176 Fix wishbone bridges with datawidth > 32 2021-09-17 09:43:30 +02:00
Dolu1990 c1481ae244 update ScopeProperty usages 2021-09-16 19:08:41 +02:00
Dolu1990 42bb1ab591 d$ / i$ toWishbone bridges can now be bigger than 32 bits
https://github.com/m-labs/VexRiscv-verilog/pull/12
2021-09-15 11:36:51 +02:00
Dolu1990 efd3cd4737 Merge branch 'master' into dev 2021-09-02 14:16:07 +02:00
Dolu1990 cc9f3e753a Fix d$ toAxi bridge 2021-09-02 14:14:42 +02:00
Dolu1990 bc561c30eb Add PmpPluginOld (support TOR) 2021-09-01 11:27:12 +02:00
Dolu1990 5c7e4a0294 #170 wishbone example now set dBusCmdMasterPipe 2021-08-24 23:24:29 +02:00
Dolu1990 3deeab42fd VexRiscvSmpCluster config fix 2021-08-10 12:14:42 +02:00
Dolu1990 805bd56077 Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value 2021-07-30 16:51:07 +02:00
Dolu1990 671bd30953 Update Bmb invalidate/sync parameters 2021-07-28 13:44:04 +02:00
Dolu1990 ba8f5f966a Vfu typo 2021-07-26 15:27:20 +02:00
Dolu1990 b717f228d6 VfuPlugin wip 2021-07-26 15:17:06 +02:00
Dolu1990 c242744d02 CfuPlugin now only fork when the rest of the pipeline is hazard free 2021-07-26 14:45:54 +02:00
Dolu1990 f3f9b79f9a VexRiscvSmpCluster earlyShifterInjection added 2021-07-21 18:34:57 +02:00
Dolu1990 5fc4125763 Merge branch 'dev' 2021-07-20 11:21:11 +02:00
Dolu1990 3028c19389 Fix #191 (data cache toAxi bridge) 2021-07-20 11:20:53 +02:00
Dolu1990 5f2fcc7d0f Merge branch 'dev'
(SpinalHDL 1.6.0)
2021-07-20 10:39:09 +02:00
Dolu1990 66bcd7fca7 readme: add the tom link about JTAG and GDB 2021-07-20 10:14:54 +02:00
Dolu1990 0cdad37fff VexRiscvSmpClusterGen now implement ebreak 2021-07-11 21:55:33 +02:00
Dolu1990 91b3e79485 SpinalHDL version++ 2021-07-11 21:55:13 +02:00
Dolu1990 a4c86130cc Update README.md 2021-07-09 09:35:49 +02:00
Dolu1990 9bc7dce857
Update README.md 2021-07-08 09:47:54 +02:00
Dolu1990 28a75afe7a reduce regression time 2021-07-05 14:17:59 +02:00
Dolu1990 c79357d1b2 VexRiscvSmpClusterGen no support atomic less configs 2021-07-05 12:38:54 +02:00
Dolu1990 a380c3a36c Merge branch 'spinal_1.4.4' into dev 2021-07-05 11:37:53 +02:00
Dolu1990 551e76d244 VexRiscvSmpCluster add a few options 2021-07-02 19:04:30 +02:00
Dolu1990 3702ea03c0 Fix github actions 2021-06-23 11:48:53 +02:00