8e7e736e3e
Merge branch 'dev' into fpu
...
# Conflicts:
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/fpu/FpuCore.scala
# src/main/scala/vexriscv/ip/fpu/Interface.scala
# src/test/scala/vexriscv/ip/fpu/FpuTest.scala
2021-02-03 16:06:17 +01:00
8eb8356dea
fpu wip
2021-02-03 14:28:02 +01:00
1d0eecdcb0
fpu f2i rounding ok and full shifter
2021-02-03 14:27:52 +01:00
ef011fa0d4
fpu moved 1 bit from round to mantissa
2021-02-02 11:29:35 +01:00
a87cb202b1
fpu i2f rounding ok
2021-02-01 16:12:38 +01:00
6aa6191240
Merge branch 'master' into dev
...
# Conflicts:
# build.sbt
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/DataCache.scala
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/MmuPlugin.scala
# src/test/cpp/regression/makefile
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2021-01-30 20:30:21 +01:00
c51b0fcafe
fpu mul now pass all roundings
2021-01-29 22:30:19 +01:00
0997592768
fpu mul sems all good excepted subnormal rounding
2021-01-29 16:13:49 +01:00
3c4df1e963
fpu moved overflow rounding to writeback
2021-01-29 14:37:52 +01:00
fc3e6a6d0a
fpu add rounding is ok excepted infinity result
2021-01-28 20:26:43 +01:00
1ae84ea83b
fpu added proper rounding for add (need to manage substraction)
2021-01-28 00:25:16 +01:00
195e4c422d
fpu now integrate f2i shifter withing the subnormal shifter
2021-01-27 12:11:30 +01:00
444bcdba0a
fpu merged i2f with load pipeline
2021-01-26 15:28:09 +01:00
3334364f5f
fpu added more tests for min max sqrt div
2021-01-26 12:50:23 +01:00
f818fb3ba4
fpu got proper subnormal support, pass add/mul
2021-01-26 10:49:53 +01:00
d6e8a5ef22
VexRiscvSmpLitex options refractoring
2021-01-23 20:16:58 +01:00
ce143e06f2
VexRiscvSmpLitex --in-order-decoder --wishbone-memory added
2021-01-23 17:48:34 +01:00
bdb5bc1180
fpu div implement some special values handeling
2021-01-22 20:47:31 +01:00
7d79685fe2
fpu mul now support special floats values and better rounding
2021-01-22 18:15:45 +01:00
4bd637cf88
fpu add now support special floats values and better rounding
2021-01-22 14:55:37 +01:00
bcd140fc42
Add vexRiscvConfig.withMmu option
2021-01-21 13:28:09 +01:00
ccd13b7e9e
fpu zero/nan wip
2021-01-21 12:13:25 +01:00
6c13e6458f
Remove registers storing PMP region bounds
2021-01-20 14:27:38 +01:00
ac5844f393
fpu add signed i2f/f2i
2021-01-20 13:15:29 +01:00
15d79ef330
fpu implement fclass and args for sub, fma, max, fcmp, fsgnj
2021-01-20 12:01:08 +01:00
828ea96006
PMP registers are now WARL
2021-01-20 09:27:35 +01:00
11349a71fa
fpu FpuPlugin now implement all instructions.
...
Remains the FPuCore to implement cmd.arg and floating point corner cases
2021-01-19 17:57:41 +01:00
9f18045329
fpu add sstatus.fs
2021-01-19 16:06:16 +01:00
a7d148d0ff
fpu add vex csr
2021-01-19 15:53:11 +01:00
f826a2ce51
fpu completion interface added + refractoring
2021-01-19 15:13:13 +01:00
8c4fae8bf2
fpu add min/sgnj/fmv
2021-01-19 13:27:42 +01:00
d7220031d4
fpu vex i2f works
2021-01-18 17:18:01 +01:00
d4b877d415
fpu vex cmp/fle works
2021-01-18 15:09:30 +01:00
6cb498cdb2
fpu merge load/commit
2021-01-18 13:09:08 +01:00
a9d8c0a19f
fpu wip
2021-01-18 11:38:26 +01:00
3cda7c1f1b
fpu wip
2021-01-15 14:03:37 +01:00
04499c0b76
FPU sqrt functional
2021-01-14 18:33:24 +01:00
85dd5dbf8e
fpu div functional, sqrt wip
2021-01-14 15:56:56 +01:00
5e6c645461
Distinguish between page faults from MMU and access faults from PMP
2021-01-14 09:45:38 +01:00
8761d0d9ee
FpuCore can add/mul/fma/store/load
2021-01-13 18:28:26 +01:00
6e0be6e18c
Cfu add state index and cfu index
2021-01-11 13:44:04 +01:00
930bdf9dda
DataCache increase syncPendingMax to 32 and use a sync queue instead of async one
2021-01-04 10:59:21 +01:00
780ad01ac0
Add AES-instruction support
2020-12-21 11:52:55 +01:00
c59499ec03
typo
2020-12-11 14:13:33 +01:00
eaff52b264
Add comments to the AesPlugin
2020-12-11 13:51:10 +01:00
6da09967f8
Add comments to the AesPlugin
2020-12-11 13:46:55 +01:00
7d699dcc13
Remove PMP from MachineOs test defaults
2020-12-10 09:42:27 +01:00
f2ce2eab00
PMP plugin passes regression tests
2020-12-07 12:04:45 +01:00
763eebeeba
Add TOR support, tests pass on GenZephyr
2020-12-04 17:13:31 +01:00
5cb5061d9b
PMP passes test with GenZephyr, but pipeline flushes have been disabled
2020-12-03 17:29:31 +01:00
9a6931a54c
CfuPlugin improve writeback buffering
2020-12-03 16:21:52 +01:00
987de8fb6a
Lock PMP address registers in golden model
2020-12-02 14:18:17 +01:00
14c39a0070
Merge remote-tracking branch 'upstream/master' into pmp
2020-12-02 14:08:32 +01:00
872aa19d83
Add PMP to golden model
2020-12-02 12:27:26 +01:00
d5b1a8f565
Add PMP test to regression suite
2020-12-01 18:38:06 +01:00
45ff78d068
VexRiscvSmpClusterGen.dBusCmdMasterPipe option added
2020-12-01 13:51:10 +01:00
c5023ad973
Add PMP regression test
2020-12-01 09:10:24 +01:00
2d0ebf1ef5
Flush pipeline after PMP CSR writes
2020-11-25 15:38:34 +01:00
e0ae46e794
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
...
# Conflicts:
# src/main/scala/vexriscv/plugin/CsrPlugin.scala
2020-11-18 14:43:24 +01:00
832218dbec
DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context
2020-11-16 12:38:29 +01:00
ba523c627a
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
2020-11-16 12:37:48 +01:00
c1b0869c21
AesPlugin is now little endian
2020-11-12 15:07:27 +01:00
1b2a2ebaca
DBusCachedPlugin miss decoded aquire fix
2020-11-12 15:07:07 +01:00
05e725174c
AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal)
2020-11-02 17:14:52 +01:00
9abe19317d
RegFilePlugin.x0Init do less assumption on other plugin behaviour
2020-11-02 17:01:17 +01:00
97fe279f7b
Enable PMP register lock
2020-10-29 13:37:21 +01:00
dc9246715d
Do not allow jtag ebreak outside machine mode
2020-10-28 13:00:16 +01:00
4209dc2792
Fix CsrPlugin privilege crossing
2020-10-28 13:00:15 +01:00
576e21d75d
Do not allow jtag ebreak outside machine mode
2020-10-28 12:58:24 +01:00
abebeaea1f
Fix CsrPlugin privilege crossing
2020-10-28 12:57:20 +01:00
fc2c8a7c37
Initial commit of PMP plugin
2020-10-27 09:38:58 +01:00
fe342c347c
CfuBusParameter has now a few default values
2020-10-23 11:06:24 +02:00
6c8e97f825
Update big endian instruction encoding
...
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.
Update the big endian instruction pipe to reflect the newer requirement.
2020-10-20 18:05:31 +02:00
4ece59385d
DataCache split redo / refilling execute stage halt
2020-10-19 18:12:20 +02:00
ec55187033
improve LightShifterPlugin arbitration halt timings
2020-10-09 11:37:48 +02:00
bbaa0520c0
Fix UserInterruptPlugin interrupt enable
2020-10-09 10:45:23 +02:00
72f85ef6c0
Merge remote-tracking branch 'origin/dev' into dev-asid
2020-10-04 19:53:29 +08:00
65e6f6054b
Add ASID field to SATP
...
ASID field is missing from the SATP which causes compatibility
issues with Xous.
While this patch resolves the Xous issue, it has not been tested
on Linux.
2020-10-04 15:34:58 +08:00
98de02051e
Merge pull request #135 from zeldin/bigendian
...
Add support for big endian byte ordering
2020-10-01 16:43:00 +02:00
3f5e771a5c
dbus mmu access improvement
2020-09-17 22:06:29 +02:00
de820daf74
add earlyBranch option to Smp config
2020-09-13 18:33:06 +02:00
49488d19af
pipeline data cache unaligned access check
2020-09-07 12:01:11 +02:00
8e466dd13c
Add support for RV32E in RegFilePlugin
...
The RV32E extension removes registers x16-x31 from the ISA. This
is useful when compiling with -mem2reg to save on BRAMs. On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.
Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
2020-09-06 17:05:31 +02:00
4c3cad97d3
fix CfuPlugin generation
2020-09-04 10:36:12 +02:00
c489143442
Add support for big endian byte ordering
2020-08-30 15:17:09 +02:00
7dcaa0c390
VexRiscvSmpCluster now avoid useless decoder for plic/clint
2020-08-13 11:26:11 +02:00
69d5ba239a
Smp config now initialise regfile using logic
2020-07-28 16:15:17 +02:00
cc423cbe49
Litex cluster add DMA sel feature
2020-07-21 19:42:27 +02:00
15bda15bc9
Litex cluster can now set cache layout
2020-07-21 19:35:56 +02:00
9f62f37538
improve LitexCluster area for single core configuration
2020-07-21 15:45:02 +02:00
da666ade49
Add VexRiscvLitexSmpClusterCmdGen
2020-07-21 15:07:32 +02:00
fe5401f835
BmbGenerators refractoring (bus -> ctrl)
2020-07-16 13:04:25 +02:00
da73317912
Cleanup BmbGenerators
2020-07-15 20:51:46 +02:00
5f0aec7570
BmbInterconnectGenerator refractoring
2020-07-15 17:03:05 +02:00
d0a572de98
Add openroad config
2020-07-08 01:37:10 +02:00
32f778613f
DBusCachedPlugin now support asyncTagMemory
2020-07-08 01:36:58 +02:00
60ee7e2b4c
Better VexRiscvSmpCluster config
2020-07-08 01:36:40 +02:00
51070d0e69
Fix MmuPlugin when used in multi stage config
2020-07-05 13:17:39 +02:00
06584518da
Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck
2020-07-05 13:17:07 +02:00
a404078117
Few fixes
2020-07-05 13:16:39 +02:00
Dolu1990
Samuel Lindemer
Marcus Comstedt
bunnie