dc0da9662a
Update SMP fence (final)
2020-05-01 11:14:11 +02:00
7c50fa6d55
SmpCluster now use i$ line of 64 bytes
2020-04-29 14:03:00 +02:00
9e9d28bfa6
d$ now implement consistancy hazard by using writeback redo
2020-04-29 14:02:41 +02:00
86e0cbc1f3
I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage
2020-04-29 13:59:43 +02:00
7b80e1fc30
Set SMP workspace to use i$ memDataWidth of 128 bits
2020-04-28 22:11:41 +02:00
eee9927baf
IBusCachedPlugin now support memory data width multiple of 32
2020-04-28 22:10:56 +02:00
03a0445775
Fix SMP for configuration without writeback stage.
...
Include SMP core into the single core tests regressions
2020-04-28 15:50:20 +02:00
4a49b23636
Fix regression
2020-04-28 14:38:27 +02:00
3ba509931c
Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
2020-04-27 17:38:06 +02:00
5fd0b220cd
CsrPlugin add openSbi config
2020-04-27 17:37:30 +02:00
0c59dd9ed3
SMP fence now ensure ordering for all kinds of memory transfers
2020-04-27 17:37:15 +02:00
3fb123a64a
fix withStall
2020-04-21 21:20:54 +02:00
3885e52bb7
Merge remote-tracking branch 'origin/dev' into smp
2020-04-21 17:21:48 +02:00
056bf63866
Add more consistancy tests
2020-04-21 16:03:03 +02:00
b389878d23
Add smp consistency check, fix VexRiscv invalidation read during write hazard logic
2020-04-21 12:18:10 +02:00
0e55caacab
deduplicae VexRiscv wishbone
2020-04-21 10:33:51 +02:00
b383b4b98b
Add commented usage of fromXilinxBscane2
2020-04-20 12:13:12 +02:00
8e8b64feaa
Got full linux / buildroot to boot in 4 cpu config
2020-04-19 19:49:26 +02:00
a1b6353d6b
workaround AMO LR/SC consistancy issue, but that need a proper fix
2020-04-19 19:48:57 +02:00
ad2d2e411a
Add tap less debug plugin bridges
2020-04-19 17:56:33 +02:00
af128ec9eb
revert to 4 cpu
2020-04-18 01:27:35 +02:00
4a49e6d91f
initialize the clint in sim
2020-04-18 01:26:31 +02:00
befecc7ed6
cleaning
2020-04-18 00:51:57 +02:00
8c0e534c6b
Add openSBI test, seem to work fine
2020-04-18 00:51:47 +02:00
d5a52caab8
fix smp test barrier
2020-04-16 17:27:27 +02:00
d88d04dbc4
More SMP tests (barrier via AMO and LRSC)
2020-04-16 15:23:25 +02:00
fd52f9ba50
Add smp.bin
2020-04-16 02:22:18 +02:00
73c21177e5
Add VexRiscvSmpCluster, seem to work on simple case
2020-04-16 01:30:03 +02:00
b9ceabf128
few fixes
2020-04-16 01:29:13 +02:00
46207abbc4
dataCache now implement invalidation sync
2020-04-16 01:28:38 +02:00
a00605b10c
fix Briey verilator
2020-04-13 13:01:12 +02:00
467a2bc488
refactor DBus invalidation, and add invalidation enable
2020-04-11 19:06:22 +02:00
abbfaf6bcf
regression : restore normal invalidation setup
2020-04-10 18:58:03 +02:00
4a9b8c1f72
improve invalidation read during write hazard logic
2020-04-10 14:44:28 +02:00
0ad0f5ed3f
Add d$ invalidation tests
...
fix d$ invalidation, linux OK
2020-04-10 14:28:16 +02:00
f71f360e32
Add SMP synthesis
2020-04-10 14:27:39 +02:00
296cb44bc4
Add hardware AMO support using LR/SC exclusive
2020-04-09 20:12:37 +02:00
1d0e180e1d
Add GenTwoStage config and UltraScale synthesis
2020-04-09 20:11:56 +02:00
861df664cf
clean some AMO stuff
2020-04-08 18:48:01 +02:00
6922f80a87
DataCache now implement fence operations
2020-04-08 18:12:13 +02:00
9e1817a280
fix DataCache for config without invalidation
2020-04-07 20:05:24 +02:00
0c8ea4a368
DataCache add invalidation feature
2020-04-07 19:18:20 +02:00
1ef099e308
Merge branch 'dev' into smp
2020-04-07 12:29:58 +02:00
f20eb4d541
Merge pull request #115 from antmicro/fix_emulator
...
emulator: Use external hw/common.h from LiteX
2020-04-07 12:29:40 +02:00
ddc59bc404
Fix DebugPlugin step by step
2020-04-07 12:27:52 +02:00
5aa0b86d96
Fix DebugPlugin step by step
2020-04-07 12:13:40 +02:00
a52b833727
fix weird regression testbench memory bug
2020-04-06 21:42:44 +02:00
a107e45116
fix non smp regression
2020-04-06 06:43:28 +02:00
ca72a421be
LrSc align software model to the hardware. Linux OK
2020-04-05 21:45:45 +02:00
2eec18de65
LrSc SMP, linux crash in userspace
2020-04-05 16:28:46 +02:00
f2ef8e95ab
Implement external LrSc
2020-04-05 11:38:57 +02:00
ff074459ad
Fix LrSc for configs without mmu
2020-04-04 22:54:35 +02:00
c9bbf0d12a
update LrSc reservation logic to match the spec
2020-04-04 21:21:35 +02:00
2dac7dae32
Fix BranchPlugin.jumpInterface priority to avoid conflicts with other instructions on DYNAMIC_TARGET missprediction
2020-03-28 14:36:06 +01:00
b3215e8beb
Make things generated in a deterministic order
2020-03-24 13:11:07 +01:00
97258c214a
Merge pull request #115 from antmicro/fix_emulator
...
emulator: Use external hw/common.h from LiteX
2020-03-18 12:02:27 +01:00
defe3c5558
DataCache relax flush timings
2020-03-08 12:35:24 +01:00
97db4f02a0
Merge branch 'rework_fetch' into dev
2020-03-07 18:22:46 +01:00
44005ebf31
update Synthesis results
2020-03-07 18:22:01 +01:00
58af94269e
add CsrPlugin.csrOhDecoder
2020-03-05 00:13:04 +01:00
505d0b700a
MulDivPlugin now give names to div stages
2020-03-04 19:58:54 +01:00
0a212c91fd
update synthesisBench paths
2020-03-04 18:13:56 +01:00
ff5cfc0dde
Fix DebugPlugin step
2020-03-03 18:27:53 +01:00
12463e40a4
improve debugPlugin step logic
2020-03-03 15:59:30 +01:00
ef5398ce21
Fix #117 DataCache mem blackboxing
2020-03-02 14:24:27 +01:00
54581f6d9e
Fix #117 DataCache mem blackboxing
2020-03-02 14:23:59 +01:00
78d4660282
Merge branch 'dev' into rework_fetch
...
# Conflicts:
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2020-03-01 22:58:25 +01:00
ea5464ea26
TestIndividualFeatures is now multithreaded
2020-03-01 21:40:53 +01:00
559260020b
Improve testing infrastructure with more options and better readme
...
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
2020-03-01 13:02:08 +01:00
25d880f6c7
Fix synthesis bench
2020-02-28 18:20:08 +01:00
c94d8f1c6c
Fetcher and IBusSimplePlugin flush reworked
2020-02-28 17:23:44 +01:00
492310e6fa
DBusCachedPlugin fix noWriteBack redo priority
2020-02-28 17:21:59 +01:00
76d063f20a
Fix MulPlugin keep attribute
2020-02-24 22:43:08 +01:00
f88b259eba
emulator: Use external hw/common.h from LiteX
...
Remove code copied from `hw/common.h` and use
the header from the LiteX repository provided
using `LITEX_BASE` environment variable.
Content of `common.h` is now evolving (new functions
are added, some are removed) and syncing it
between repos would be cumbersome.
2020-02-24 14:27:45 +01:00
485b4a5838
Improve maxPerf configs
2020-02-23 23:52:43 +01:00
fad09e805f
Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns
2020-02-23 23:18:27 +01:00
67d2071a32
typo
2020-02-23 23:17:02 +01:00
c8016e90a4
MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP
2020-02-23 20:25:31 +01:00
01e5112680
Fetcher RVC ensure redo keep PC(1)
...
Fix BranchTarget RVC inibition
2020-02-23 10:44:44 +01:00
5ea0b57d1b
Fix BRANCH_TARGET with RVC patch
2020-02-22 11:53:47 +01:00
41008551c1
CsrPlugin redo interface do not need next pc calculation
2020-02-21 20:01:35 +01:00
4ad1215873
Fix iBusSimplePlugin MMU integration
2020-02-21 13:28:42 +01:00
befc54a444
No more Fetcher flush() API as it can now be done via the decoder.flushNext
2020-02-21 13:28:29 +01:00
32fade50e5
Fix fetcher decompressor when driving decode stage
2020-02-21 02:03:29 +01:00
59508d5b57
Fix target branch prediction for RVC, all default configs pass dhrystone
2020-02-20 02:27:57 +01:00
a684d5e4d1
Rework/clean decompressor logic
2020-02-19 01:20:52 +01:00
a7440426fd
Fix FetchPlugin redo gen condition
...
Fix injectorFailure reset
2020-02-18 01:00:11 +01:00
f63c4db469
Fix CsrPlugin pipeline liberator
2020-02-18 00:59:39 +01:00
53a29e35e9
fix deleg external interrupt propagation time failure
2020-02-17 23:27:17 +01:00
e0cd9a6e06
clean iBusRsp redo
2020-02-17 22:45:34 +01:00
0e0a568743
Apply DYNAMIC_TARGET correction all the time
2020-02-17 21:43:02 +01:00
e23295f06e
Fix Fetcher pcValid pipeline
2020-02-17 19:29:41 +01:00
9e75e2cb58
IBusFetcher disable pcRegReusedForSecondStage when using fetch prediction.
...
Fix some fetch flush
DYNAMIC_PREDICTION start to work again
2020-02-17 14:36:08 +01:00
8be50b8e3d
IBusFetcher now support proper iBusRsp.redo/flush
2020-02-17 12:50:12 +01:00
ebfa9e6577
Merge branch 'dev' into rework_fetch
2020-02-16 18:52:31 +01:00
29f85a7ae2
Remove INSTRUCTION_READY
...
Add proper Fetcher.ibusRsp.flush
prediction are disabled yet
much is broken for sure, WIP
2020-02-16 18:44:10 +01:00
3d34d754a9
Remove usages of implicit string to B/U/S
2020-02-15 10:11:00 +01:00
5b8febb977
Revert "Revert "Merge branch 'master' into dev""
...
This reverts commit c01c256757
2020-01-29 22:37:09 +01:00
c01c256757
Revert "Merge branch 'master' into dev"
...
This reverts commit b5374433a5f01da9c73b
2020-01-29 15:20:13 +01:00
b5374433a5
Merge branch 'master' into dev
2020-01-29 12:50:41 +01:00
badc38d645
Merge remote-tracking branch 'origin/master' into arty
2020-01-17 00:54:19 +01:00
1fb1e358bb
fix makefile clean target
2020-01-17 00:49:35 +01:00
97b2838d18
Murax on Digilent Arty A7-35
2020-01-16 21:58:55 +01:00
de9f704de2
better pin names in scala, bootloader without magic word
2020-01-13 21:58:08 +01:00
f01da9c73b
CsrPlugin add printCsr
2020-01-13 20:44:55 +01:00
b866dcb07f
XIP on Murax improvements
2020-01-12 16:08:14 +01:00
4c7025b964
Fix xtval when no exception and read_only
2020-01-06 20:07:23 +01:00
2a06907902
fix compilation
2019-12-24 01:09:55 +01:00
3b494e97cd
Moved KeepAttribute to spinal.lib
2019-12-24 00:43:36 +01:00
052c8dd602
Fix inWfi naming, fix regressions
2019-12-20 00:21:55 +01:00
0702f97806
CsrPlugin add wfiOutput
2019-12-19 22:55:17 +01:00
e25dfb4fbf
CsrPlugin now make SATP write rescheduling the next instruction
2019-12-09 22:23:07 +01:00
744b040c70
Sync CFU progress
2019-11-29 11:50:00 +01:00
7ae218704e
CsrPlugin now implement a IWake interface
...
DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
2019-11-19 18:36:53 +01:00
6d0d70364c
Add BranchPlugin.decodeBranchSrc2 for branch target configs
2019-11-08 14:01:53 +01:00
4fe7fa56c7
GenCustomInterrupt demo now enabled vectored interrupt
2019-11-07 19:55:26 +01:00
bb405e705b
Add UserInterruptPlugin
2019-11-07 19:52:45 +01:00
8839f8a8e9
Fix DBus AXI bridges from writePending counter deadlock
2019-11-03 16:45:24 +01:00
2bf6a536c9
Fix DBus AXI bridges from writePending counter deadlock
2019-11-03 16:44:09 +01:00
bd2787b562
RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot
2019-11-01 16:24:07 +01:00
bb9261773b
Fix MulDiveIterative plugin when RSx have hazard in the execute stage
2019-10-23 00:02:08 +02:00
67028cdb48
Add Mul16Plugin to regression tests
...
Fix missing MulSimplePlugin in regressions tests
2019-10-21 12:53:53 +02:00
8091a872f3
Fix muldiv plugin for CPU configs without memory/writeback stages
2019-10-21 12:53:03 +02:00
2d56c6738c
Multiplication Plugin using 16-bit DSPs
2019-10-20 22:24:19 +02:00
b4c75d4898
Merge remote-tracking branch 'origin/dev' into dev
2019-10-11 00:25:37 +02:00
a2b49ae000
Fix CFU arbitration, add CFU decoder, CFU now redirect custom-0 with func3
2019-10-11 00:25:22 +02:00
310c325eaa
IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect
2019-10-11 00:24:21 +02:00
711eed1e77
MulPlugin add withInputBuffer feature and now use RSx instead of SRCx
2019-10-11 00:23:29 +02:00
3fc0a74102
Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature
2019-10-11 00:22:44 +02:00
51d22d4a8c
Merge remote-tracking branch 'origin/cfu' into dev
2019-10-10 15:00:43 +02:00
5df56bea79
Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register
...
(used to inject instruction from the debug plugin)
2019-10-03 00:20:33 +02:00
49944643d2
Add regression for data cache without writeback stage, seem to pass tests, including linux ones
2019-09-23 15:20:51 +02:00
bf82829e9e
Data cache can now be used without writeback stage
2019-09-23 15:20:20 +02:00
ace963b542
Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one
2019-09-21 14:13:28 +02:00
e1795e59d5
Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages
2019-09-21 13:00:54 +02:00
e8236dfebe
Add MulSimplePlugin regressions
2019-09-21 12:49:46 +02:00
b8b053e706
muldiviterative: fix build for short pipelines
...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 08:36:01 +08:00
fdc95debef
dbuscached: fix build for short pipelines
...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 08:35:49 +08:00
0b79c637b6
mulsimpleplugin: fix build for short pipelines
...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 08:35:23 +08:00
6ed41f7361
Improve CSR FMax
2019-09-16 13:53:55 +02:00
d94cee13f0
Add dummy decoding, exception code/tval
...
Add Cpu generation code
Add support for always ready rsp
2019-09-05 19:06:28 +02:00
5ac443b745
Manage cases where a rsp buffer is required
2019-09-05 10:41:45 +02:00
6951f5b8e6
CfuPlugin addition
2019-09-05 10:41:45 +02:00
86f5af5ca9
Fix handling LiteX uart and timer.
2019-09-05 10:41:45 +02:00
8813e071bc
Add `litex` target
...
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
2019-09-05 10:41:45 +02:00
64a2815544
Create makefile targets
...
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
2019-09-05 10:41:45 +02:00
e76435c6c6
Allow to set custom DTB/OS_CALL addresses
...
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
2019-09-05 10:41:45 +02:00
c8280a9a88
Allow to set custom RAM base address for emulator
...
This is needed when loading the emulator to RAM
with an offset.
2019-09-05 10:41:45 +02:00
b65ef189eb
sync with SpinalHDL SDRAM changes
2019-08-29 16:03:20 +02:00
5085877eed
Fix handling LiteX uart and timer.
2019-07-24 16:09:21 +02:00
6a2584b840
Add `litex` target
...
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
2019-07-11 15:56:48 +02:00
39c3f408e5
Create makefile targets
...
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
2019-07-11 15:50:15 +02:00
423355ecbf
Allow to set custom DTB/OS_CALL addresses
...
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
2019-07-11 14:09:06 +02:00
28a11976da
Allow to set custom RAM base address for emulator
...
This is needed when loading the emulator to RAM
with an offset.
2019-07-11 14:06:24 +02:00
a2569e76c0
Update sdram ctrl package
2019-07-08 11:23:48 +02:00
624c641af5
xip refractoring
2019-06-28 10:23:39 +02:00
1257b056dc
Revert "test only dynamic_target for intensive test"
...
This reverts commit 635ef51f82
2019-06-16 18:24:59 +02:00
635ef51f82
test only dynamic_target for intensive test
2019-06-16 17:43:07 +02:00
9656604848
rework dynamic_target failure correction
2019-06-16 17:42:39 +02:00
60c9c094a7
Merge remote-tracking branch 'origin/rework_jump_flush' into dev
2019-06-15 18:09:38 +02:00
a3a0c402bc
Remove broken freertos test and add zephyr instead
2019-06-15 10:46:10 +02:00
617f4742cd
Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch
2019-06-14 08:13:22 +02:00
d603de1bfe
Fix recent changes
2019-06-13 16:55:24 +02:00
c8ab99cd0b
Cleaning and remove BlockQ regression
2019-06-12 00:00:38 +02:00
21ec368927
Fix DYNAMIC_TARGET by fixing decode PC updates
2019-06-11 19:56:33 +02:00
afbf0ea777
Fix regression makefile
2019-06-11 01:05:49 +02:00
066ddc23e6
Add regression concurrent os executions flag to avoid running debug plugin tests
2019-06-11 00:22:38 +02:00
21c8933bbb
Fix DYNAMIC_TARGET prediction correction in BranchPlugin
2019-06-11 00:12:29 +02:00
5b53440d27
DYNAMIC_TARGET prediction datapath/control path are now splited
2019-06-10 22:20:32 +02:00
0e95154869
individual regression : more env control
2019-06-10 21:01:41 +02:00
bd46dd88aa
Fix RVC fetcher pc branches
2019-06-10 20:48:04 +02:00
24e1e3018c
Fix exception handeling
2019-06-09 23:40:37 +02:00
5243e46ffb
Fix BranchPlugin when SRC can have hazard in execute stage
2019-06-09 20:15:36 +02:00
af0755d8cf
rework flush with flushNext and flushIt
...
static branch prediction jump do not depend on stage fireing anymore
2019-06-09 15:44:05 +02:00
357681a5c6
csrPlugin add pipelinedInterrupt, set by default
2019-06-08 22:22:16 +02:00
0df4ec45ad
Merge remote-tracking branch 'origin/master' into dev
...
# Conflicts:
# build.sbt
2019-06-05 00:35:41 +02:00
56f7c27d18
Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege
2019-06-05 00:32:38 +02:00
38a464a829
DataCache now allocate ways randomly
2019-05-25 00:28:30 +02:00
4a40184b35
Add cache Bandwidth counter, previous commit was about random instruction cache way allocation
2019-05-25 00:22:27 +02:00
94606d38e2
Add cache bandwidth counter
2019-05-25 00:21:48 +02:00
206c7ca638
Fix Bmb datacache bridge
2019-05-24 00:22:58 +02:00
f6f94ad7c1
Fix InstructionCache Bmb bridge
2019-05-22 19:03:26 +02:00
9b49638654
Allow CsrPlugin config access
2019-05-22 17:27:47 +02:00
8abc06c8f2
Add Bmb support for i$/d$
2019-05-22 17:04:36 +02:00
49b4b61a1a
Update Bmb bridges
2019-05-20 14:14:42 +02:00
0301ced000
Fix dBusSimplePlugin to bmb bridge
2019-05-16 19:49:13 +02:00
3753f64429
Fix Bmb compilation
2019-05-13 23:44:20 +02:00
abb7bd99ab
Merge pull request #75 from SpinalHDL/dev
...
Merge dev (SpinalHDL 1.3.4)
2019-05-10 17:28:09 +02:00
db307075cf
Merge branch 'AHB' into dev
...
# Conflicts:
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
2019-05-07 17:21:52 +02:00
01db217ab9
Add supervisor support in the ExternalInterruptArrayPlugin
2019-05-06 16:23:43 +02:00
d27fa4766d
DBusCachedPlugin add earlyWaysHits in regressions
2019-05-06 00:05:40 +02:00
d12decde80
Remove test which had issues with the testbench ref checks because of getting passed delayed
2019-05-05 22:46:46 +02:00
5f18705358
Add DBusCachedPlugin.relaxedMemoryTranslationRegister option
2019-05-05 21:19:48 +02:00
c738246610
Remove the legacy pipelining from Axi4 cacheless bridges
2019-05-01 12:03:01 +02:00
d1e215e312
caches: work without writeBack stage
...
In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.
Place the retry branch port into the correct stage.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:02:43 +08:00
b2f387ccac
MmuPlugin: fix generation without writeBack stage
...
If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.
Instead, pull from the most recent stage, which is where MMU access
should reside.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:01:35 +08:00
d64589cc48
Add configs without memory/writeback stages in regressions
...
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
2019-04-25 17:36:13 +02:00
74e5cc49f9
Add the linux config into the synthesis bench
2019-04-24 12:32:37 +02:00
a331f35724
Icestorm flow now use nextpnr
2019-04-24 12:32:24 +02:00
b654d824ad
remove DebugPlugin from linux.scala, and set static branch prediction
2019-04-23 21:55:54 +02:00
266bdccc2e
update Riscv software model lrsc implementation
2019-04-23 21:55:54 +02:00
4078f84e8f
Dhrystone regression now also run coremark
2019-04-23 21:55:54 +02:00
c6dbaa52f6
Longer linux regression timeout for very slow configs
2019-04-21 22:16:42 +02:00
14efe6ffda
Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes
2019-04-21 20:01:39 +02:00
d7ca153c8b
remove interrupt assertion
2019-04-21 19:45:24 +02:00
0e10c460c3
Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long
2019-04-21 17:58:42 +02:00
4cbb93cfc8
Look like zephyr mem_pool_threadsafe is a broken test
2019-04-21 17:48:08 +02:00
1c86bf7514
Increase liveness trigger to allow large instruction cache flush
2019-04-21 15:25:39 +02:00
963805ad48
Bring freertos back in tests
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Better travis test range
2019-04-21 12:50:28 +02:00
edde3e3011
Add zephyr tests
2019-04-21 02:56:44 +02:00
3b0f2e9551
better travis timings
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travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
2019-04-20 14:56:56 +02:00
b49076ecab
add missing coremark patch
2019-04-19 19:41:05 +02:00
728a5ff20f
Fix coremark binaries (no csr)
2019-04-19 18:28:46 +02:00
e47b76fa67
#60 Added automated linux regression in travis
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Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage
Fix IBusSimplePlugin issues with used with non regular configs + MMU
Bring back the LinuxGen config into a light one
2019-04-19 17:35:48 +02:00
2810ff05b0
Fix emulator instruction emulation trap redirection to supervisor.
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Impact only AMO less configs
2019-04-19 02:31:39 +02:00
b79b02152b
#60 Fix SFENCE_VMA deadlock
2019-04-18 18:33:06 +02:00
d2b324e32b
Add jtag and vhdl option
2019-04-15 11:01:51 +02:00
6f04c02cd2
TestInduvidualFeatures now use the linux config + MMU
2019-04-14 23:06:04 +02:00
8c7407967e
Fix non RVC fetcher exception PC capture
2019-04-14 23:04:30 +02:00
61d25e931e
#60 Add sim error message on RVC instruction without RVC capabilities
2019-04-13 10:44:06 +02:00
5d1ec604b2
Make regression sim great again
2019-04-13 10:41:15 +02:00
9ac1d3d59e
riscv software model without RVC now trap on RVC instruction before pcWrite + 2
2019-04-13 10:40:53 +02:00
3301a1b364
Add CsrPlugin.userGen option which now remove privilegeReg when not set
2019-04-12 16:37:34 +02:00
d5723968da
Merge remote-tracking branch 'origin/master' into linux
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# Conflicts:
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
# src/test/cpp/regression/main.cpp
2019-04-12 16:26:08 +02:00
8421328ee1
restore freertos tests
2019-04-12 16:09:20 +02:00
13b774b535
#69 Relax address calculation of decode branch predictor by adding KEEP synthesis attribut
2019-04-12 15:56:22 +02:00
41ff87f83b
Remove jalr from decode branch prediction missaligned inibition
2019-04-12 15:27:10 +02:00
63cd5f42af
Fix #69 discoverd fmax issue with decode stage branch predictions
2019-04-12 15:24:33 +02:00
b329ee85ad
#60 Fix missing ecallGen flag
2019-04-11 15:30:54 +02:00
ece1e73547
Default linux config is now without RVC
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Remove all linux usless CSR from the config
Remove verilator instruction fetch check
2019-04-11 01:18:15 +02:00
caa37a8028
Reduce machine mode emulator CSR requirements and emulate more CSR (in the case they aren't supporter in hardware)
2019-04-10 19:04:52 +02:00
6b22594961
Flush MMU line with exception on context switching instead than on cmd fire
2019-04-10 15:42:39 +02:00
926b74a203
shorter coremark
2019-04-10 15:41:58 +02:00
189cadfbb3
Add coremark
2019-04-10 15:41:38 +02:00
d7f6c18c0a
Fix DebugPlugin -> force machine mode, force uncached memory load
2019-04-10 00:35:15 +02:00
9b6b65b8b4
Fix icache test when dynamic target branch prediction is enabled
2019-04-09 19:37:18 +02:00
a6dc530441
Added lrsc/amo tests
2019-04-09 19:27:42 +02:00
fd42e7701e
Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala
2019-04-09 01:22:32 +02:00
21cb8615fd
Clean and fix things to get all the non-linux configs and machine only configs working
2019-04-08 16:06:05 +02:00
32921491b8
#60 Fix instruction cache refill
2019-04-08 14:24:37 +02:00
fd15a938c5
#60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only.
2019-04-08 13:20:56 +02:00
c2595273ec
Add a busy flag from MMU ports
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iBus/dBus now halt on MMU busy, which avoid looping forever on page fault
2019-04-08 11:38:40 +02:00
f89ee0d422
#60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so.
2019-04-07 15:44:25 +02:00
4fd36454d7
Complain about wrong earlyBranch settings.
2019-04-06 12:58:19 -07:00
39a4aa5e26
GenMicroNoCsr: no memory stage, no write-back stage
2019-04-06 12:38:54 -07:00
6df3e57843
workaround Verilator comparaison linting
2019-04-06 02:00:47 +02:00
21b4ae8f2f
update todo, nothing todo ? everything done ?
2019-04-06 01:42:01 +02:00
e7f3dd5553
Rework CsrPlugin exception delegation
2019-04-05 23:40:39 +02:00
ddf0f06834
Add more delegation tests
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Reduce dcache test duration
2019-04-05 22:56:12 +02:00
acaa931e11
Rework CsrPlugin interrupt delegation
2019-04-05 22:55:42 +02:00
Dolu1990
Mateusz Holenko
sebastien-riou
Richard Petri
Sean Cross
Tom Verbeure