e3e21994b4
use SpinalHDL "dev"
2022-07-22 09:33:19 +02:00
54412bde30
getDrivingReg() update
2022-07-21 09:10:26 +02:00
a650000f0b
SpinalHDL 1.7.2
2022-07-11 12:03:06 +02:00
b1252f47de
csr opensbi now enable ebreak
2022-06-13 16:34:49 +02:00
1303c0ca7c
CfuPlugin.withEnable added
2022-06-09 17:57:31 +02:00
1ce4c6e493
fix VexRiscvRegressionData url
2022-06-01 09:54:11 +02:00
0f6d0f022c
VexRiscvBmbGenerator now also report bytesPerLine
2022-05-24 12:37:31 +02:00
771eaf431e
Better cache invalidation doc
2022-05-24 12:15:57 +02:00
e6dfcac0be
Add D$ single line flush support
2022-05-24 12:13:37 +02:00
4c4913c703
Fix MPP to only retain legal values
2022-05-24 11:14:34 +02:00
209fc719e8
VexRiscvBmbGenerator export more info
2022-05-24 10:19:35 +02:00
48cf4120f2
Add VexRiscvSmpCluster forceMisa/forceMscratch
2022-05-23 15:49:32 +02:00
0872852387
Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254
2022-05-17 20:44:17 +02:00
a553d3b476
Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254
2022-05-17 15:27:50 +02:00
78f0a7f13e
Fix CfuPlugin/VfuPlugin fork duplication
...
https://github.com/google/CFU-Playground/issues/582
2022-05-16 10:36:21 +02:00
8df2dcbd40
Fix RVC step by step triggering next instruction branch predictor
2022-05-11 14:10:32 +02:00
6326736401
Update build.sbt
2022-05-04 00:03:54 +02:00
27772a65dd
SpinalHDL 1.7.1
2022-04-29 15:22:34 +02:00
9506b0b8f1
SpianlHDL 1.7.0
2022-04-29 14:16:41 +02:00
8a8e976493
Merge pull request #248 from dnltz/WIP/dnltz/fix-reg
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plugin: caches: Fix "Can't resolve the literal value of"
2022-04-22 11:12:26 +02:00
ea7a18c7f4
plugin: caches: Fix "Can't resolve the literal value of"
...
Both registers were initialized with unsigned integers without a value.
This triggered:
[error] Exception in thread "main" spinal.core.SpinalExit:
[error] Can't resolve the literal value of (..._rspCounter : UInt[32 bits])
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
2022-04-20 11:19:34 +02:00
3b8270b82b
#241 Fix Murax/Briey TB timeouts
2022-04-11 11:59:41 +02:00
db34033593
#240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust
2022-04-08 11:09:14 +02:00
e6c21996a4
Merge pull request #243 from andreasWallner/fix_gen_simd_add_resetvector
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Fix reset vector of GenCustomSimdAdd
2022-04-04 10:16:50 +02:00
2d2017465e
Fix reset vector of GenCustomSimdAdd
...
With the old reset vector half of the tests fail since
they expect the CPU to start at 0x80000000.
(e.g. I-IO, I-NOP, I-LUI, etc.)
2022-04-03 02:55:42 +02:00
ccff48f872
deprecated Data.keep
2022-03-30 16:17:57 +02:00
4bddb091ae
Update CFU example
2022-03-23 18:58:18 +01:00
5dc91a8be4
Add MuraxCfu
2022-03-23 18:54:18 +01:00
b2e61caf9e
CfuPlugin now implement upstream spec
2022-03-23 18:54:07 +01:00
9149c42065
DecoderPlugin now implement forceIllegal API
2022-03-23 18:53:43 +01:00
51b8865b66
Fix VexRiscvSmpClusterGen linux less mhartid
2022-03-18 12:36:05 +01:00
e558b79582
Fix Briey simulation floating rxd blocking the uart #238
2022-02-22 16:15:14 +01:00
9d3b83366c
Merge branch 'master' into dev
2022-02-17 16:27:26 +01:00
36f57d5eb7
Merge pull request #236 from dnltz/WIP/dnltz/remove-assert
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plugin: DBusSimplePlugin: Remove assert
2022-02-17 16:25:45 +01:00
5b45ddab1b
SpinalHDL 1.6.4
2022-02-16 14:26:58 +01:00
e4fde184d9
SpinalHDL 1.6.5
2022-02-16 14:12:00 +01:00
807aa98d37
plugin: DBusSimplePlugin: Remove assert
...
This assert triggered sometimes at the beginning of a simulation.
Since it's not really needed anymore, we can remove it.
Signed-off-by: Daniel Schultz <daniel.schultz@aesc-silicon.de>
2022-02-10 19:55:08 +01:00
77e361e91e
Merge branch 'dev'
2022-02-05 12:08:43 +01:00
5714680278
Merge branch 'master' into dev
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# Conflicts:
# build.sbt
2022-02-05 11:32:40 +01:00
62c07670af
version++
2022-02-05 11:31:04 +01:00
4dd650736f
verilator++
2022-02-04 16:36:11 +01:00
378c0f8723
verilator++
2022-02-04 16:20:43 +01:00
8b2f107d46
verilator++
2022-02-04 15:10:57 +01:00
7d9a50357f
Merge pull request #233 from dnltz/WIP/dnltz/csr-registers
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plugin: CsrPlugin: Init cycle and instret registers
2022-01-27 12:05:43 +01:00
57dd80a566
plugin: CsrPlugin: Init cycle and instret registers
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Both counters are initialized with "randBoot()". This is fine for FPGA
designs because the registers can be loaded with default values but
ASIC designs require to load the value during a reset.
Since both counters require to start at 0 (read-only CSR registers),
change both registers from "randBoot()" to "init(0)".
Error:
reg [63:0] CsrPlugin_mcycle = 64'b0000000...00000000000;
|
Warning : Ignoring unsynthesizable construct. [VLOGPT-37]
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2022-01-26 08:59:03 +01:00
9c34a1fd2e
updated related to JtagInstructionWrapper.ignoreWidth
2022-01-14 09:59:24 +01:00
b8e904e43f
syncronize golden model with dut for lrsc reservation
2022-01-10 19:55:28 +01:00
6e77f32087
sim golden model lrsc reservation sync
2022-01-10 16:08:38 +01:00
da53de360f
Fix lrsc from last commit
2022-01-10 14:21:20 +01:00
f46ad43f39
DataCache.withInternalLrSc reserved clearing fix
2022-01-10 13:39:41 +01:00
Dolu1990
Daniel Schultz
Andreas Wallner
Daniel Schultz
Daniel Schultz