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331 Commits

Author SHA1 Message Date
Jędrzej Boczar 7f36717516 test: add LiteDRAMNativePortCDC tests 2020-03-24 11:55:24 +01:00
Jędrzej Boczar 1f8868e6e9 test: add frontend.adaptation tests for different conversion ratios 2020-03-24 11:12:11 +01:00
Jędrzej Boczar f19d92b67f test: add wishbone tests with data width mismatch 2020-03-20 14:48:50 +01:00
Jędrzej Boczar 7996ee5143 test: add missing write-enable handling 2020-03-20 14:48:50 +01:00
Jędrzej Boczar 3c0fdf0710 test: handle 'we' in DRAMMemory, add memory debug messages 2020-03-20 14:48:39 +01:00
Jędrzej Boczar e8558f6f9f test: fix bits formatting 2020-03-20 13:18:24 +01:00
Jędrzej Boczar 7593b2d9b9 test: add basic wishbone test 2020-03-20 09:30:33 +01:00
enjoy-digital 060d1807ad
Merge pull request #168 from antmicro/jboc/unit-tests-ecc 
Add unit tests for ECC
 2020-03-19 18:24:43 +01:00
Jędrzej Boczar 68d078cc78 test: add tests for LiteDRAMNativePortECCW/LiteDRAMNativePortECCR 2020-03-19 10:57:54 +01:00
Jędrzej Boczar 03f93998b5 test: move DMA specific tests to test_dma.py 2020-03-19 09:13:28 +01:00
Jędrzej Boczar 1b4647b2e1 test: add tests for LiteDRAMNativePortECC 2020-03-18 15:43:49 +01:00
Jędrzej Boczar 36d5b42aa0 test: correct DMAReaderDriver/DMAWriterDriver logic 2020-03-17 15:37:50 +01:00
Jędrzej Boczar 6ef623efae test: cleanup test_bist.py code style 2020-03-17 14:23:08 +01:00
Jędrzej Boczar a883f88cca test: add LiteDRAMDMAReader tests 2020-03-17 14:12:09 +01:00
Jędrzej Boczar d86ebd7e9d test: add LiteDRAMDMAWriter tests 2020-03-17 12:39:10 +01:00
Jędrzej Boczar 5618d2a54c test: fix quotes 2020-03-17 09:45:28 +01:00
Jędrzej Boczar ef9b13d7e8 test: add tests for BIST modules with clock domain crossing 2020-03-16 16:38:58 +01:00
Jędrzej Boczar a00c8b7940 test: unify BIST tests, factor out repetitive code 2020-03-16 09:23:45 +01:00
Jędrzej Boczar 13aeb3fd65 test: add _LiteDRAMBISTChecker/_LiteDRAMPatternChecker tests 2020-03-16 09:11:37 +01:00
Jędrzej Boczar ba83e5645c test: add some more verbose _LiteDRAMBISTGenerator tests 2020-03-16 09:11:37 +01:00
Jędrzej Boczar 239859d95b test: add tests for _LiteDRAMPatternGenerator 2020-03-16 09:11:37 +01:00
Jędrzej Boczar ac06382b5a test: split GenCheckDriver run into configure/run 2020-03-16 09:11:37 +01:00
Jędrzej Boczar c8423a08a3 test: exit with failure when no benchmarks succeeded 2020-03-12 14:16:21 +01:00
Jędrzej Boczar 92daf53ea2 test: fix with_uart parameter (see litex/b29f443f) 2020-03-12 14:16:21 +01:00
Jędrzej Boczar b89ecdf919 test: add _LiteDRAMBISTGenerator tests 2020-03-11 15:38:13 +01:00
Karol Gugala 2ce64bd5fb Fix copyrights 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
 2020-03-05 17:40:21 +01:00
Florent Kermarrec 8fee3c7edf test/reference: update kc705 ddr3_init.h. 2020-03-05 11:35:12 +01:00
enjoy-digital 87578dd2e3
Merge pull request #153 from antmicro/jboc/issue-151 
test/benchmarks: add memtype to summary (#151)
 2020-02-20 14:00:27 +01:00
enjoy-digital 4f9d6e413f
Merge pull request #152 from antmicro/jboc/benchmark 
Benchmarks: add timeout parameter
 2020-02-20 14:00:06 +01:00
Jędrzej Boczar 19cbf7d967 test/benchmarks: add memtype to summary (#151) 2020-02-20 13:36:49 +01:00
Jędrzej Boczar a5d2c09e8f test: add benchmark timeout parameter 2020-02-20 09:33:09 +01:00
Jędrzej Boczar 247722d97e test: fix wrong sorting in benchmarks summary 2020-02-20 09:20:38 +01:00
Jędrzej Boczar a27841199b test: option to print heartbeat during benchmarks to avoid Travis timeouts 2020-02-19 13:08:04 +01:00
enjoy-digital 5fb2b011d8
Merge pull request #146 from antmicro/jboc/benchmark 
Benchmarks: Generate HTML summary and deploy it from Travis
 2020-02-18 13:26:20 +01:00
Jędrzej Boczar d14254124a test: run benchmarks in Travis CI and deploy the results 2020-02-17 14:46:50 +01:00
Piotr Binkowski f0be039a34 test: add option to use sdram timing verifier in benchmarks 2020-02-17 14:35:15 +01:00
Jędrzej Boczar b7ed91d9f0 test: suppress info log messages in benchmark runner 2020-02-17 13:14:52 +01:00
Jędrzej Boczar c6cc0e068d test: keep benchmark failures in data frame and filter out when needed 2020-02-17 09:07:13 +01:00
Jędrzej Boczar bba49f2df8 test: add generation of html benchmarks summary 2020-02-17 09:07:13 +01:00
Jędrzej Boczar dd12a78587 test: reduce disk usage when running benchmarks in parallel 2020-02-13 10:30:48 +01:00
Jędrzej Boczar 5cd33f490f test: update benchmark configuration generator 2020-02-12 15:42:50 +01:00
Jędrzej Boczar 4f613b5b00 test: add number of generators/checkers to benchmark runner, update metrics 2020-02-12 14:40:33 +01:00
Jędrzej Boczar edf4ddb2f2 test: add option to use multiple BIST generators/checkers 2020-02-12 14:40:33 +01:00
Jędrzej Boczar 45633e55b5 test: update BIST generator and checker tests 2020-02-11 14:24:02 +01:00
Jędrzej Boczar 409b9922ea test: add random address generation in benchmarks 2020-02-11 13:11:06 +01:00
Jędrzej Boczar 6744cf649c test: add handling of alternating write/read to benchmark runner 2020-02-11 13:10:04 +01:00
Jędrzej Boczar e16118abfd test: fix: use of undeclared variable 2020-02-11 12:13:37 +01:00
Jędrzej Boczar ff435fd26e test: add option to run benchmarks with alternating write/read 2020-02-11 12:06:45 +01:00
Jędrzej Boczar 9148400ef5 test: fix typo, add note about limitations 2020-02-07 12:20:43 +01:00
Jędrzej Boczar 2825c080a9 test: fix problem with plot labels overlapping for large number of benchmarks 2020-02-07 09:52:31 +01:00
Jędrzej Boczar 77541c3670 test: avoid instantiating LiteDRAMBenchmarkSoC to speed up summary generation 2020-02-06 15:08:01 +01:00
Jędrzej Boczar 027034db49 test: add option to run benchmarks as parallel jobs 2020-02-06 15:07:55 +01:00
Jędrzej Boczar 62a5473ecd test: update script for generating benchmark configurations 2020-02-06 13:35:34 +01:00
Jędrzej Boczar 8ba3cced60 test: add new benchmark configuratiosns to example configuration file 2020-02-05 18:58:49 +01:00
Jędrzej Boczar 1702e2ad7c test: update summary to work for all configurations (use pandas) 2020-02-05 18:39:06 +01:00
Jędrzej Boczar f9f86d507f test: update benchmark configuration to account for access pattern 2020-02-05 12:54:33 +01:00
Jędrzej Boczar 7e0515c477 test: fix problem with helper scripts being executed by `setup.py test` 2020-02-04 16:37:26 +01:00
Jędrzej Boczar fcd3d4ff6c test: helper scripts for generating benchmark configurations/access patterns 2020-02-04 16:26:57 +01:00
Jędrzej Boczar fcbcd4d3fe test: add option to benchmark predefined access patterns 2020-02-04 16:26:57 +01:00
Jędrzej Boczar bae046f143 test: add read/write latency benchmarks 2020-02-03 16:59:12 +01:00
Jędrzej Boczar a584923f1c test: use JSON instead of pickle for storing benchmarks cache 2020-02-03 12:17:41 +01:00
Florent Kermarrec 736723cc98 test/run_benchmarks: change YAML config file argument 2020-02-03 10:38:10 +01:00
Florent Kermarrec 7e95ecc9a9 test/run_benchmark: avoid Python 3.7+ dependency 2020-02-03 10:37:10 +01:00
Jędrzej Boczar 811c73254b test: benchmark script exits with error on any checker error 2020-01-31 15:16:37 +01:00
Jędrzej Boczar 1a517a308d test: cache benchmark results to be able to produce multiple summaries 2020-01-31 14:39:41 +01:00
Jędrzej Boczar a40817f3a8 test: add plotting of benchmark results 2020-01-31 14:39:41 +01:00
Jędrzej Boczar f6973aa9d7 test: load benchmark configurations from YAML file 2020-01-30 15:39:29 +01:00
Jędrzej Boczar 096de78c63 test: fix `setup.py test` failing due to import error 
because of relative import the script has to be run as:
    python -m test.run_benchmarks
 2020-01-30 14:11:52 +01:00
Jędrzej Boczar bb4f6106ee test: print benchmarks summary 2020-01-30 10:50:08 +01:00
Jędrzej Boczar e822e6be9f test: calculate benchmark bandwidth and efficiency 2020-01-30 10:19:17 +01:00
Jędrzej Boczar 804a9b3727 test: add script for running multiple benchmarks and parsing results 2020-01-29 17:03:20 +01:00
Jędrzej Boczar 502e6c663c test: add command line arguments for BIST base/length/random 2020-01-28 15:03:36 +01:00
Florent Kermarrec 586eb39b1d test: add initial benchmark test 2020-01-28 12:07:22 +01:00
Florent Kermarrec bb1b431184 test/test_init: use max_sdram_size of 1GB 2020-01-24 10:46:29 +01:00
Florent Kermarrec 1d2bc922b8 frontend/fifo: get back to original simple design and add test 2020-01-07 15:40:09 +01:00
Florent Kermarrec ac4b339a6f test/reference: update init headers 2019-11-15 19:45:39 +01:00
Florent Kermarrec f861d99903 core/refresher: improve naming/parameters of refresh postponing 2019-09-11 08:38:22 +02:00
Florent Kermarrec 40b4c62889 test/test_init: fix 2019-09-09 15:17:43 +02:00
Florent Kermarrec 5b48eb278a test/test_init: delete generated file 2019-09-09 15:08:01 +02:00
Florent Kermarrec 188b6a8feb add ZQ periodic short calibration support (default to 1s) 2019-09-09 15:07:38 +02:00
Florent Kermarrec 0b24b817e3 test: add test_init with sdr/ddr3/ddr4 references 2019-09-09 11:45:10 +02:00
Florent Kermarrec a782eb5aa8 test/test_examples: adapt for travis 2019-08-31 14:55:14 +02:00
Florent Kermarrec 2bdeda021b move standalone core generation to litedram package and make it usable externally 
When LiteDRAM is installed, standalone core can now be generated with "litedram_gen config.yml"
 2019-08-28 07:19:30 +02:00
Florent Kermarrec 602ff8be81 examples: switch to YAML config files 2019-08-28 07:08:10 +02:00
Florent Kermarrec 338d18dba0 core/refresher: add capability to accumulate N refreshs and execute the N refreshs together 
Being able to accumulate refreshs allow reducing the number of interruptions to the Controller from 1 every tREFI cycles to 1 every N*tREFI cycles.
 2019-08-14 09:57:24 +02:00
Florent Kermarrec de38b52eb6 core/refresher: rename RefreshGenerator to RefreshSequencer and simplify 2019-08-14 08:08:30 +02:00
Florent Kermarrec 6c53996a70 core/refresher: reduce refresh period by one cycle 2019-07-24 08:18:04 +02:00
Florent Kermarrec afb6d0a15e core/refresher: reduce RefreshGenerator start delay by 1 cycle 2019-07-24 08:01:54 +02:00
Florent Kermarrec b543286d06 test/test_refresh: add Refresher test 2019-07-23 22:31:27 +02:00
Florent Kermarrec 7daf3551f6 test/test_bist: remove vcd generation (only useful for debug) 2019-07-23 21:46:03 +02:00
Florent Kermarrec b4125fa50f test/test_refresh: add RefreshTimer test 2019-07-23 21:44:09 +02:00
Florent Kermarrec 9584c2fe88 test: remove use of rand_wait, rename rand_level to random 2019-07-23 21:14:17 +02:00
Florent Kermarrec 0eef5d4d55 test: add test_refresh with simple RefreshGenerator test 2019-07-23 16:36:21 +02:00
Florent Kermarrec 93488009c9 test: rename test_timing_controllers to test_timing 2019-07-23 16:05:31 +02:00
Florent Kermarrec 8cf561d620 test/test_timing_controllers: add simple tFAWController tests 2019-07-23 15:58:26 +02:00
Florent Kermarrec 3ae666d015 test/test_timing_controllers: add simple tXXDController tests 2019-07-23 15:48:32 +02:00
Florent Kermarrec 394a49a759 test: add test_timing_controllers with tXXDController test 2019-07-23 12:40:40 +02:00
Florent Kermarrec 54cdc7f4cb test: -x on tests 2019-07-23 12:16:44 +02:00
Florent Kermarrec 2ecb0534ec frontend/ecc: move generic part of ECC to LiteX 2019-07-13 11:47:13 +02:00
Florent Kermarrec 8646b2e2c4 test/test_adaption: use same DUT for up/down converter tests 2019-07-13 10:52:41 +02:00
Florent Kermarrec 9f9fed02f6 test: merge test_downconverter/test_upconverter in a single test_adaptation file 2019-07-13 10:31:30 +02:00
Florent Kermarrec f018c9e268 add CONTRIBUTORS file and add copyright header to all files. 2019-06-23 23:59:10 +02:00
Florent Kermarrec fef530366a test: clean test_downconverter/test_upconverter (thanks sb0) 2019-06-13 09:15:09 +02:00
Florent Kermarrec e824288924 frontend/axi: move AXIBurst2Beat to LiteX 
Will be useful for others purposes.
 2019-04-19 12:14:13 +02:00
Florent Kermarrec be269da3fe frontend/axi: use definitions from LiteX 
AXI definitions were not present in LiteX when AXI support was added to LiteDRAM.
 2019-04-19 11:58:05 +02:00
Florent Kermarrec 201a0e2fb4 test/test_examples: add nexys4ddr 2019-03-15 20:10:50 +01:00
Florent Kermarrec 429d3a89de test/common: set rdata_valid_rand_level default value to 0 2019-01-21 16:54:23 +01:00
Florent Kermarrec 2483d25f79 test/test_ecc: update 2019-01-04 10:43:57 +01:00
Florent Kermarrec d6350d9fec test/test_axi: reduce rand_level on writes 2018-12-05 11:44:38 +01:00
Florent Kermarrec 6778c72665 test/test_axi: cleanup, all tests passings. 2018-12-03 08:01:33 +01:00
Florent Kermarrec 7f5d749c6b test: add missing +x 2018-11-30 11:58:45 +01:00
Florent Kermarrec 7ef4869db9 test/test_axi: also add randomness on rdata.valid and wdata.ready 2018-11-30 11:22:04 +01:00
Florent Kermarrec 3db68cdd50 test/test_axi/axi2native: add tests for each randomness parameters (ease finding regressions issues) 2018-11-30 10:40:45 +01:00
Florent Kermarrec 190b1bd01f test/test_axi/axi2native: add finer control on randomness 2018-11-30 09:40:13 +01:00
Florent Kermarrec 4f137b9334 test/test_axi/axi2native: add random on len, just use writes as reads 2018-11-29 23:45:38 +01:00
Florent Kermarrec 2a799e4f1d test/test_axi: set size on axi2native test 2018-11-29 23:45:31 +01:00
Florent Kermarrec 93e8510f55 test/test_axi: add bursts to axi2native 2018-11-12 18:00:28 +01:00
Florent Kermarrec e27fbc2430 test/test_axi: move definitions to top and make Access herit from Burst 2018-11-12 13:09:05 +01:00
Florent Kermarrec 4470f32ef8 test/test_axi: change order of the tests 2018-11-12 12:59:19 +01:00
Florent Kermarrec 070cc26994 test/test_axi: use separate generator for writes cmd/data 2018-11-12 12:58:19 +01:00
Florent Kermarrec 71be616817 frontend/axi: be sure wdata is available before sending the command to the controller 2018-11-09 11:33:01 +01:00
Florent Kermarrec 9a950f051a ecc: update core/test 2018-10-12 17:13:53 +02:00
Florent Kermarrec 1bc016cf6c test: add test_examples 2018-10-01 11:29:08 +02:00
Florent Kermarrec f7f8169883 test: update downconverter/upconverter 2018-10-01 11:18:54 +02:00
Florent Kermarrec b145b0c338 frontend/axi: fix write response implementation 2018-09-18 15:24:41 +02:00
Florent Kermarrec 461b076624 frontend/ecc: add ecc adapter 2018-09-16 01:01:45 +02:00
Florent Kermarrec c84b58735a frontend: add initial ecc code (still need to be integrated) 
Works but all combinatorial, will maybe need to be pipelined
 2018-09-15 23:37:59 +02:00
Florent Kermarrec 849b1f6c35 frontend/axi: generate rlast signal 2018-09-06 11:11:17 +02:00
Florent Kermarrec 1fa73e4718 test: update 2018-09-06 11:10:45 +02:00
Florent Kermarrec f6797a16bb test/test_axi: add burst wrap test and fix code 2018-08-29 18:47:40 +02:00
Florent Kermarrec c15c47497a test/test_axi: split reads/writes generators 2018-08-28 14:09:12 +02:00
Florent Kermarrec 95cb7cdba5 test: rename read/write generators to handlers 2018-08-28 13:40:50 +02:00
Florent Kermarrec 10229d1e7d test/test_axi: improve test_axi2native 2018-08-28 13:39:11 +02:00
Florent Kermarrec 6a46ea3052 test/test_bist: add generator test, remove async test 2018-08-28 11:50:11 +02:00
Florent Kermarrec 7a5ac75e22 test/test_axi: improve test_axi2native 2018-08-27 18:39:36 +02:00
Florent Kermarrec c846b8b1c7 frontend/axi: add burst support (fixed/incr) 2018-08-27 16:21:12 +02:00
Florent Kermarrec 57157345cf frontend: add initial AXI support 2018-08-21 13:39:46 +02:00
Florent Kermarrec 2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 2018-08-21 13:21:04 +02:00
Florent Kermarrec c28a754867 test: update 2018-08-09 10:54:42 +02:00
Florent Kermarrec 697f46a97f replace litex.gen imports with migen imports 2018-02-23 13:39:23 +01:00
Felix Held 72b1b109b7 Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:22:08 +11:00
Florent Kermarrec 25d5674f33 test: remove test_bitslip (now in litex) 2017-04-24 18:49:20 +02:00
Florent Kermarrec 98d9f1ffc0 test/test_bitslip: simplify BitSlipModel 2017-02-10 13:18:11 +01:00
Florent Kermarrec 062177502b phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3) 2017-02-10 08:59:13 +01:00
Florent Kermarrec 99550968e7 test: move BISTDriver to common and use it in test_bist_async 2017-01-17 15:18:10 +01:00
Florent Kermarrec d213a628f8 test/test_bist: use generator to corrupt memory (allow testing base address on checker/generator) 2017-01-17 14:35:34 +01:00
Florent Kermarrec 40168db0b4 test/test_bist: create BISTDriver to simplify test code 2017-01-17 14:31:24 +01:00
Florent Kermarrec c56f90e865 test/test_bist: simplify and test modules directly not through CSR 2017-01-17 14:14:50 +01:00
Florent Kermarrec ad304c8997 test: convert to python unittests and some cleanup 2017-01-17 13:18:11 +01:00
Tim 'mithro' Ansell c142db3966 Creating a utility module for easily scoping the LiteDRAMBISTChecker module. 2016-12-19 17:49:24 +01:00
Florent Kermarrec aac61f346e test: start fixing bist_tb 2016-12-17 19:24:12 +01:00
Tim 'mithro' Ansell e21b45b608 Merge remote-tracking branch 'upstream/master' into bist 2016-12-17 18:15:59 +01:00
Tim 'mithro' Ansell bc75d4f3d5 bist: Reworking as suggested by Florent. 2016-12-17 17:49:47 +01:00
Tim 'mithro' Ansell f1ad8991a4 bist: Working on improving the names of things. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 8ff2f8779b bist: Adding "halt on error" functionality. 
Also include ability to see address of error and expected verse actual
data values.

Extend the test bench to test this functionality.
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell da144f41d4 bist: Refactoring test bench. 
Move a bunch of common code into common.py
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell dc14a98bf4 bist: s/shoot/start/ 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 086b905e59 bist: Improve the basic test bench a little. 2016-12-17 14:09:50 +01:00
Florent Kermarrec ad8ca86e13 frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly 
still some corner cases to manage
 2016-06-15 23:57:16 +02:00
Florent Kermarrec 5823373243 frontend: introduce mode on ports: write, read or both 2016-06-15 17:51:46 +02:00
Florent Kermarrec e2b6bda7d0 test: add random and autocheck on downconverter_tb and upconverter_tb 2016-06-08 17:33:21 +02:00
Florent Kermarrec cb69561137 phy/model: add we_granularity parameter as simulator bug workaround (to be removed) 2016-05-28 13:02:40 +02:00
Florent Kermarrec 8ee2992e5b frontend/bist: simplify and use incrementing addressing 2016-05-26 12:04:41 +02:00
Florent Kermarrec 2445758eba +x on scripts 2016-05-26 11:10:03 +02:00
Florent Kermarrec b3a11fb669 frontend: move port adaptation modules to adaptation.py and do adaptation manually (and not in get_port) 2016-05-26 11:03:55 +02:00
Florent Kermarrec 3fe3a843e0 test: also test reads on downconverter/upconverter 2016-05-24 21:40:46 +02:00
Florent Kermarrec 32a6e25021 test: add upconverter_tb and some fixes 2016-05-24 21:14:49 +02:00
Florent Kermarrec de61cefb58 test: add downconverter_tb and some fixes 2016-05-24 20:48:26 +02:00
Florent Kermarrec 6f10314d43 frontend/bist: remove cd parameter (already available with dram_port.cd) 2016-05-23 17:37:30 +02:00
Florent Kermarrec b258c9a913 test: add bist_async_tb and some fixes 2016-05-23 17:20:42 +02:00
Florent Kermarrec cb324ea47c frontend/bist: LiteDRAMBISTGenerator can now be asynchronous 2016-05-23 14:17:22 +02:00
Florent Kermarrec f36c65b66f test: move DRAMMemory model to common 2016-05-23 13:30:38 +02:00
Florent Kermarrec 94d526a78c test/bist_tb: adapt to new interface 2016-05-23 13:27:29 +02:00
Florent Kermarrec 30bacfeb1b frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests) 2016-05-13 15:27:12 +02:00
Florent Kermarrec d7458a3c34 test: remove common 2016-05-04 01:16:29 +02:00
Florent Kermarrec a40b0f760c test/bist_tb: cleanup and add error check 2016-05-03 22:22:11 +02:00
Florent Kermarrec 836a9d4f00 test: removed bank_machine_tb (should be rewritten) 2016-05-03 19:25:39 +02:00
Florent Kermarrec 812d7dd7f0 frontend/bist: reword bist, add simulation, seems to work but need more testing 2016-05-03 19:24:33 +02:00
Florent Kermarrec 0ef987dab1 bankmachine: some changes and first tests 2015-09-27 23:42:05 +02:00
Florent Kermarrec 7732ff27a6 update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
Florent Kermarrec 230bad1b23 init structure 2015-02-22 18:25:36 +01:00