Hardware/liteeth
1
0
Fork 0
mirror of https://github.com/enjoy-digital/liteeth.git synced 2025-01-03 03:43:37 -05:00
Code Issues Projects Releases Packages Wiki Activity
343 commits 6 branches 14 tags 3.8 MiB
Commit graph

226 commits

Author SHA1 Message Date
Florent Kermarrec
c6cfed6294 frontend/etherbone: expose buffer_depth to user. 2020-11-23 17:44:47 +01:00
Florent Kermarrec
291b257eb4 phy/crg: make rst_n optional on all PHYs and minor cleanup. 2020-11-23 16:24:44 +01:00
enjoy-digital
75495dd6ec
Merge pull request #54 from rprinz08/master 
Fix syntax and load error in Wireshark etherbone dissector
 2020-11-23 13:44:57 +01:00
Florent Kermarrec
5247a2008a phy/ecp5rgmii: remove p_DEL_MODE (not required since we specify DEL_VALUE). 2020-11-23 12:16:07 +01:00
rprinz08
d3bbd506ba Fix syntax and load error in Wireshark etherbone dissector 2020-11-07 10:55:21 +01:00
Florent Kermarrec
06242564f7 frontend/etherbone: simplify LiteEthEtherboneRecordReceiver. 2020-11-06 19:49:07 +01:00
Florent Kermarrec
d96fdfc5e5 frontend/etherbone: simplify LiteEthEtherboneRecordSender using combinatorial logic and fix #52. 2020-11-06 19:43:57 +01:00
enjoy-digital
0c287d07f8
Merge pull request #51 from gregdavill/ecp5rgmii_delay_fix 
phy/ecp5rgmii: Fix io delay blocks
 2020-10-12 09:17:02 +02:00
Greg Davill
6ee11edb87 phy/ecp5rgmii: Fix io delay blocks 
For correct io delays in nextpnr the DEL_VALUE parameter needs to
be an integer, instead of the "DELAY{}" string.

The use of a "DELAY{}" string appears in the Lattice primitive
manual, but appears to be incorrect. At least based of the current
nextpnr.

Because we are not making use of dynamic io delays here we can
also use the simpler DELAYG block instead of DELAYF.

Fixes #50
 2020-10-11 15:16:58 +10:30
Greg Davill
9aee36939f mac/core: Improve timing closure of core 
On ECP5 targets the core struggles to meet timing closure. This
change adds buffers to the CRC module on tx/rx paths.
This results in 20-30MHz gain to max clock rate.

This fixes #47
 2020-10-11 14:46:16 +10:30
Florent Kermarrec
54acf9fd76 phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support). 
3768f5acc1
 2020-08-24 22:14:35 +02:00
Florent Kermarrec
64b85e621e add SPDX License identifier to header and specify file is part or LiteEth. 
Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it.
 2020-08-23 16:07:12 +02:00
Florent Kermarrec
f275af8297 liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios. 2020-08-22 21:22:02 +02:00
Xiretza
6a9a5132f6
Update gen.py to work with latest LiteX in wishbone mode 
Previously, it would fail with:

$ liteeth/gen.py examples/wishbone_mii.yml
[snip]
Traceback (most recent call last):
  File "liteeth/gen.py", line 346, in <module>
    main()
  File "liteeth/gen.py", line 331, in main
    soc = MACCore(platform, core_config)
  File "liteeth/gen.py", line 244, in __init__
    self.add_wb_master(bridge.wishbone)
  File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master
    self.bus.add_master(master=wbm)
  File "[...]/litex/soc/integration/soc.py", line 347, in add_master
    master = self.add_adapter(name, master, "m2s")
  File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter
    bridge_cls = {
KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)
 2020-08-22 11:00:42 +02:00
Florent Kermarrec
792013a175 mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in #43). 2020-07-13 11:27:25 +02:00
Florent Kermarrec
1d76d02ea6 frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream). 2020-07-13 10:08:50 +02:00
Shawn Hoffman
d66d302567 mac padding: fix counter reset value 2020-06-25 03:26:37 -07:00
Florent Kermarrec
b1bcfb2073 mac/LiteEthMACCoreCrossbar: remove unnecessary fifos. 2020-06-22 14:54:26 +02:00
Florent Kermarrec
8e1185711b common: remove Port.connect and use 2 separate Record.connect. 2020-06-22 14:36:44 +02:00
Florent Kermarrec
17caf17c9e mac/LiteEthMACCoreCrossbar: remove cpu_dw. 2020-06-19 22:06:53 +02:00
Florent Kermarrec
23b420a2dd mac/LiteEthMAC: simplify hybrid mode and avoid some duplication. 2020-06-19 22:01:22 +02:00
Florent Kermarrec
51cd54602b core/mac: add missing separators, fix typos. 2020-06-19 19:59:53 +02:00
Florent Kermarrec
59d3336bec mac: add separators, improve indent, minor simplifications. 2020-06-19 19:42:25 +02:00
Florent Kermarrec
d06c7b49a2 frontend: add separators, improve indent, minor simplifications. 2020-06-19 19:21:24 +02:00
Florent Kermarrec
2d58f489ea core: improve indent. 2020-06-19 19:12:12 +02:00
Florent Kermarrec
c26281882a core: add separators. 2020-06-19 19:02:28 +02:00
Florent Kermarrec
bb29706e71 core: remove mac retro-compatibility (>6 months old). 2020-06-19 18:57:11 +02:00
Florent Kermarrec
0feed1720d phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work). 
This makes clocking more flexible and allows routing on more boards (ex: Pano Logic G2). Since TX clocking
does not need clock phase relationship with the input clock using a combinatorial path is fine.
 2020-05-29 10:39:18 +02:00
Florent Kermarrec
53c9eb91a5 core/ip: move mcase_oui/ip_mask definition to common and set target_mac with NextValue. 2020-05-19 10:13:15 +02:00
enjoy-digital
58e1681f5d
Merge pull request #41 from shuffle2/mcast 
iptx: support multicast mac and bypass arp table
 2020-05-19 09:51:11 +02:00
Florent Kermarrec
8afdec936d phy/ecp5rgmii: review/simplify inband_status integration. 
For now keep it specific to ECP5, we'll integrate this soon on the others PHYs,
but some other refactoring/merging is required before.
 2020-05-19 09:41:09 +02:00
Shawn Hoffman
6d00ec1cc4 iptx: support multicast mac and bypass arp table 2020-05-17 14:52:02 -07:00
Shawn Hoffman
26c4e41b96 ecp5rgmii: enable reading inband PHY_status 2020-05-11 03:01:50 -07:00
Florent Kermarrec
dc67e6d070 phy/ecp5rgmii: use DDROutput/DDRInput now available for ECP5. 2020-04-22 10:14:36 +02:00
Florent Kermarrec
3bd807cf8f litex.build: update from migen.genlib.io litex.build.io. 2020-04-10 09:20:41 +02:00
Florent Kermarrec
ab55304ab7 mac/sram: use reset_less on datapath/configuration CSRStorages. 2020-04-06 13:17:30 +02:00
Florent Kermarrec
fb478537e7 phy/gmii: use a BUFG between eth_rx.clk and eth_rx.clk. 
This makes it Xilinx specific, but without it ISE simplifies this as a single signal
(which is fine) but is not able to keep track of the "keep" attribute of both signals
and fails applying the constraints.
 2020-03-25 12:40:02 +01:00
enjoy-digital
8accd6740a
Merge pull request #36 from antmicro/hybrid-mac 
mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone
 2020-03-19 22:09:57 +01:00
Florent Kermarrec
ea24ff6993 liteeth_gen: improve readability and add clk_freq checks. 2020-03-19 19:58:35 +01:00
Xiretza
2e9121d330
Allow changing all SoC options through YAML config 2020-03-17 18:52:44 +01:00
Piotr Binkowski
ac9f6d9f05 mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone 2020-03-13 15:30:36 +01:00
Florent Kermarrec
32d4af1148 phy/__init__: import all phys. 2020-03-01 20:13:23 +01:00
Florent Kermarrec
b2e12724cc phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints). 2020-03-01 19:10:39 +01:00
Florent Kermarrec
466223e18d liteeth/gen: update copyrights 2020-02-12 16:50:35 +01:00
Xiretza
7a44209f77
Make memory/CSR regions customizable in config 
Also remove interrupt mapping, since it's unused without a CPU anyway.
 2020-02-12 15:55:04 +01:00
Xiretza
ca9cbd1555
Move more options to config file 2020-02-12 15:55:04 +01:00
Xiretza
eea1086654
Use builder arguments in generator 2020-02-12 15:51:53 +01:00
Xiretza
b9fb1f03ec
Remove leftover classes in generator 2020-02-12 15:51:53 +01:00
Florent Kermarrec
fcadd60cea liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe) 2020-02-12 00:18:22 +01:00
Florent Kermarrec
0954fa32b1 Merge branch 'generator-lattice' of git://github.com/ximinity/liteeth into ximinity-generator-lattice 2020-02-11 23:34:52 +01:00
Xiretza
5767dfcb6c
Honour --output-dir argument in generator 2020-02-11 22:03:12 +01:00
Xiretza
153c160670
Prioritise overridden interrupts and memory regions 2020-02-11 21:58:41 +01:00
Xiretza
ec9bc578f2
Fix MII tx_en signal width in standalone generator 2020-02-11 21:57:47 +01:00
Xiretza
42a7b6c69d
Allow little-endian interface for standalone design 2020-02-11 21:57:47 +01:00
Xiretza
a696ccddb4
Expose interrupt pin for standalone design 2020-02-11 21:57:02 +01:00
Florent Kermarrec
208bc095d9 liteeth/gen: update 2020-02-11 21:45:46 +01:00
Stefan Schrijvers
ae10eea860
gen: add lattice support 2020-02-08 16:33:03 +01:00
Florent Kermarrec
081bf46ca6 mac/sram: simplify code and improve SRAM read speed using async_read on Memory. 2020-02-07 11:40:14 +01:00
Florent Kermarrec
bf4a11ab30 mac/sram: simplify counter (use NextValue in FSM) 2020-02-07 10:57:25 +01:00
Florent Kermarrec
721238b7a8 mac/sram: cosmetic changes 2020-02-07 10:53:05 +01:00
Florent Kermarrec
f532a12b40 phy/common: use CSRField for MDIO registers 2020-01-28 10:43:33 +01:00
Florent Kermarrec
8edf4f3f9a phy/1000basex: cleanup primitive instances, use Open signal class on open ports, polish code comments 2020-01-28 10:43:08 +01:00
Florent Kermarrec
de40a66873 phy/gmii: cleanup BUFGMUX instance 2020-01-28 10:41:53 +01:00
Florent Kermarrec
983017a9ed phy/rgmii: cleanup primitive instances 2020-01-28 10:41:32 +01:00
Vamsi K Vytla
8ecaaf0546 phy/{s7,us}rgmii.py: 
Recent modification that adds S7PLL that in return adds an AsyncResetSynchronizer inside XilinxClocking.

This actually creates a multi-driven net because there is another AsyncResetSync* being added in the Phys.

This change instantiates the PLL without a reset for now, leaving the CD reset intact.
 2020-01-27 12:52:10 -08:00
Vamsi K Vytla
cd413c5c20 phy/usrgmii.py: 
IDELAYE3 requires EN_VTC to be enabled for fixed mode time delay. This eliminates implementation time CRITICAL WARNINGs and ensures generating a bitfile.
 2020-01-27 10:32:38 -08:00
Florent Kermarrec
3a54bf2b8b phy/rgmiis: uniformize a bit more 2020-01-18 00:24:40 +01:00
Florent Kermarrec
e41f06bbf2 phy: cleanup imports/dw 2020-01-17 23:19:56 +01:00
Florent Kermarrec
a48c78044e phy/s7rgmii/usrgmii: use S7PLL and USPLL 2020-01-17 23:08:38 +01:00
Vamsi K Vytla
c16e6b2d86 phy/ecp5rgmii.py: Missed moving dw as class variable here 2020-01-17 12:45:37 -08:00
Vamsi K Vytla
0a922bb2ad A few minor changes that help RGMII phy related debugging. {s6, s7, us}rgmii.py Make dw a class variable instead 2020-01-17 09:23:03 -08:00
Florent Kermarrec
17e228d4b0 phy/usrgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:24:35 +01:00
Florent Kermarrec
6270eb38d2 phy/s7rgmii: cleanup 2020-01-17 09:22:30 +01:00
Florent Kermarrec
ee4f8c0f34 phy/usrgmii: improve presentation 2020-01-17 09:15:51 +01:00
Florent Kermarrec
2bdae4e7bd phy/s7rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:13:29 +01:00
Florent Kermarrec
aea81e19e9 phy/s7rgmii: improve presentation 2020-01-17 09:05:09 +01:00
Florent Kermarrec
2748e442a9 phy/s6rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:03:34 +01:00
Florent Kermarrec
8fb0dae18a phy/s6rgmii: improve presentation 2020-01-17 08:57:52 +01:00
Florent Kermarrec
0cf9c2057d phy/ecp5rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 08:54:31 +01:00
Florent Kermarrec
e5c4ee7065 phy/ecp5rgmii: improve presentation 2020-01-17 08:35:15 +01:00
Florent Kermarrec
73bd27b506 phy/s7rgmii: add 2ns delay on ctl/data 2020-01-16 15:46:13 +01:00
Florent Kermarrec
bb01840b12 add initial LiteEth standalone core generator from examples/core.py 2019-11-24 11:22:51 +01:00
Florent Kermarrec
5a789570be mac/wishbone: remove FullMemoryWE (prevent simulation and should no longer be useful) 2019-11-23 00:12:46 +01:00
Vamsi K Vytla
57be29e68a global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links 
To support 10Gbps/25Gbps, the hardware stack will need to handle multiple bytes/clock cycle.
Pass dw to all modules to allow making use of it in the future. For now dw=8.
 2019-11-21 11:01:55 +01:00
Florent Kermarrec
ba83253ffa core/arp: fix typo 2019-11-21 11:01:53 +01:00
Florent Kermarrec
6b0a9251c0 global: keep up to date with LiteX (update stream_packet import to packet) 
Retro-compatibily was ensure by LiteX but update it.
 2019-11-21 11:01:50 +01:00
Florent Kermarrec
d2eb870445 core: allow passing ip_address as str 2019-11-07 13:23:10 +01:00
Florent Kermarrec
4d9e74f10a phy/usrgmii: cleanup (style, indent) 2019-09-28 22:16:07 +02:00
Vamsi K Vytla
59e04608a8 Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 2019-09-04 15:11:20 -07:00
Florent Kermarrec
ad187d35f2 add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
Florent Kermarrec
a170acda0f change MAC location (next to phy/core/frontend), keep import retro-compatibility 2019-06-24 11:20:46 +02:00
Florent Kermarrec
789dadd8bf liteeth/software: remove libwip/libuip examples. 
libuip integration can be found in https://github.com/timvideos/HDMI2USB-litex-firmware/tree/master/firmware
 2019-06-17 21:17:52 +02:00
Florent Kermarrec
2424e62bf9 software: also include generated/mem.h 2019-05-20 09:00:25 +02:00
Florent Kermarrec
e88fc507c8 software: remote ethmac_mem.h dependency (no longer exists in LiteX) 2019-05-19 19:29:04 +02:00
Florent Kermarrec
b318300414 phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked 2019-04-11 21:51:09 +02:00
Florent Kermarrec
e6c35cdec8 phy/ku_1000basex: incease pll_reset 2019-04-10 15:38:21 +02:00
Florent Kermarrec
816f592469 phy: add initial ECP5RGMII PHY 2019-02-25 14:45:19 +01:00
Florent Kermarrec
b4c1cfe8c5 core/icmp: fix reply checksum when request checksum >= 0xf800 
need to add +1
 2019-02-24 23:30:46 +01:00
Florent Kermarrec
77fa4bfb1e phy: add Kintex7 1000BaseX PHY 2019-01-22 19:40:32 +01:00
Florent Kermarrec
c2d8a467c9 phy: add Kintex Ultrascale PHY (copyright M-Labs Ltd) 2019-01-21 11:27:33 +01:00