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226 commits

Author SHA1 Message Date
Xiretza
5767dfcb6c
Honour --output-dir argument in generator 2020-02-11 22:03:12 +01:00
Xiretza
153c160670
Prioritise overridden interrupts and memory regions 2020-02-11 21:58:41 +01:00
Xiretza
ec9bc578f2
Fix MII tx_en signal width in standalone generator 2020-02-11 21:57:47 +01:00
Xiretza
42a7b6c69d
Allow little-endian interface for standalone design 2020-02-11 21:57:47 +01:00
Xiretza
a696ccddb4
Expose interrupt pin for standalone design 2020-02-11 21:57:02 +01:00
Florent Kermarrec
208bc095d9 liteeth/gen: update 2020-02-11 21:45:46 +01:00
Stefan Schrijvers
ae10eea860
gen: add lattice support 2020-02-08 16:33:03 +01:00
Florent Kermarrec
081bf46ca6 mac/sram: simplify code and improve SRAM read speed using async_read on Memory. 2020-02-07 11:40:14 +01:00
Florent Kermarrec
bf4a11ab30 mac/sram: simplify counter (use NextValue in FSM) 2020-02-07 10:57:25 +01:00
Florent Kermarrec
721238b7a8 mac/sram: cosmetic changes 2020-02-07 10:53:05 +01:00
Florent Kermarrec
f532a12b40 phy/common: use CSRField for MDIO registers 2020-01-28 10:43:33 +01:00
Florent Kermarrec
8edf4f3f9a phy/1000basex: cleanup primitive instances, use Open signal class on open ports, polish code comments 2020-01-28 10:43:08 +01:00
Florent Kermarrec
de40a66873 phy/gmii: cleanup BUFGMUX instance 2020-01-28 10:41:53 +01:00
Florent Kermarrec
983017a9ed phy/rgmii: cleanup primitive instances 2020-01-28 10:41:32 +01:00
Vamsi K Vytla
8ecaaf0546 phy/{s7,us}rgmii.py: 
Recent modification that adds S7PLL that in return adds an AsyncResetSynchronizer inside XilinxClocking.

This actually creates a multi-driven net because there is another AsyncResetSync* being added in the Phys.

This change instantiates the PLL without a reset for now, leaving the CD reset intact.
 2020-01-27 12:52:10 -08:00
Vamsi K Vytla
cd413c5c20 phy/usrgmii.py: 
IDELAYE3 requires EN_VTC to be enabled for fixed mode time delay. This eliminates implementation time CRITICAL WARNINGs and ensures generating a bitfile.
 2020-01-27 10:32:38 -08:00
Florent Kermarrec
3a54bf2b8b phy/rgmiis: uniformize a bit more 2020-01-18 00:24:40 +01:00
Florent Kermarrec
e41f06bbf2 phy: cleanup imports/dw 2020-01-17 23:19:56 +01:00
Florent Kermarrec
a48c78044e phy/s7rgmii/usrgmii: use S7PLL and USPLL 2020-01-17 23:08:38 +01:00
Vamsi K Vytla
c16e6b2d86 phy/ecp5rgmii.py: Missed moving dw as class variable here 2020-01-17 12:45:37 -08:00
Vamsi K Vytla
0a922bb2ad A few minor changes that help RGMII phy related debugging. {s6, s7, us}rgmii.py Make dw a class variable instead 2020-01-17 09:23:03 -08:00
Florent Kermarrec
17e228d4b0 phy/usrgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:24:35 +01:00
Florent Kermarrec
6270eb38d2 phy/s7rgmii: cleanup 2020-01-17 09:22:30 +01:00
Florent Kermarrec
ee4f8c0f34 phy/usrgmii: improve presentation 2020-01-17 09:15:51 +01:00
Florent Kermarrec
2bdae4e7bd phy/s7rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:13:29 +01:00
Florent Kermarrec
aea81e19e9 phy/s7rgmii: improve presentation 2020-01-17 09:05:09 +01:00
Florent Kermarrec
2748e442a9 phy/s6rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:03:34 +01:00
Florent Kermarrec
8fb0dae18a phy/s6rgmii: improve presentation 2020-01-17 08:57:52 +01:00
Florent Kermarrec
0cf9c2057d phy/ecp5rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 08:54:31 +01:00
Florent Kermarrec
e5c4ee7065 phy/ecp5rgmii: improve presentation 2020-01-17 08:35:15 +01:00
Florent Kermarrec
73bd27b506 phy/s7rgmii: add 2ns delay on ctl/data 2020-01-16 15:46:13 +01:00
Florent Kermarrec
bb01840b12 add initial LiteEth standalone core generator from examples/core.py 2019-11-24 11:22:51 +01:00
Florent Kermarrec
5a789570be mac/wishbone: remove FullMemoryWE (prevent simulation and should no longer be useful) 2019-11-23 00:12:46 +01:00
Vamsi K Vytla
57be29e68a global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links 
To support 10Gbps/25Gbps, the hardware stack will need to handle multiple bytes/clock cycle.
Pass dw to all modules to allow making use of it in the future. For now dw=8.
 2019-11-21 11:01:55 +01:00
Florent Kermarrec
ba83253ffa core/arp: fix typo 2019-11-21 11:01:53 +01:00
Florent Kermarrec
6b0a9251c0 global: keep up to date with LiteX (update stream_packet import to packet) 
Retro-compatibily was ensure by LiteX but update it.
 2019-11-21 11:01:50 +01:00
Florent Kermarrec
d2eb870445 core: allow passing ip_address as str 2019-11-07 13:23:10 +01:00
Florent Kermarrec
4d9e74f10a phy/usrgmii: cleanup (style, indent) 2019-09-28 22:16:07 +02:00
Vamsi K Vytla
59e04608a8 Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 2019-09-04 15:11:20 -07:00
Florent Kermarrec
ad187d35f2 add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
Florent Kermarrec
a170acda0f change MAC location (next to phy/core/frontend), keep import retro-compatibility 2019-06-24 11:20:46 +02:00
Florent Kermarrec
789dadd8bf liteeth/software: remove libwip/libuip examples. 
libuip integration can be found in https://github.com/timvideos/HDMI2USB-litex-firmware/tree/master/firmware
 2019-06-17 21:17:52 +02:00
Florent Kermarrec
2424e62bf9 software: also include generated/mem.h 2019-05-20 09:00:25 +02:00
Florent Kermarrec
e88fc507c8 software: remote ethmac_mem.h dependency (no longer exists in LiteX) 2019-05-19 19:29:04 +02:00
Florent Kermarrec
b318300414 phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked 2019-04-11 21:51:09 +02:00
Florent Kermarrec
e6c35cdec8 phy/ku_1000basex: incease pll_reset 2019-04-10 15:38:21 +02:00
Florent Kermarrec
816f592469 phy: add initial ECP5RGMII PHY 2019-02-25 14:45:19 +01:00
Florent Kermarrec
b4c1cfe8c5 core/icmp: fix reply checksum when request checksum >= 0xf800 
need to add +1
 2019-02-24 23:30:46 +01:00
Florent Kermarrec
77fa4bfb1e phy: add Kintex7 1000BaseX PHY 2019-01-22 19:40:32 +01:00
Florent Kermarrec
c2d8a467c9 phy: add Kintex Ultrascale PHY (copyright M-Labs Ltd) 2019-01-21 11:27:33 +01:00
Florent Kermarrec
d7fdcbb1dc phy: add Spartan6 RGMII PHY 2018-12-18 08:58:16 +01:00
Florent Kermarrec
52c23015b0 frontend/etherbone: reduce default buffer_depth to 4 2018-10-30 11:21:06 +01:00
Florent Kermarrec
602ddec664 common: use reverse_bytes from litex.gen 2018-10-30 11:13:09 +01:00
Florent Kermarrec
c370e9f71f phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) 2018-09-20 22:49:37 +02:00
Florent Kermarrec
3d868449e9 core/mac/sram: fix code refactoring 2018-09-17 09:10:59 +02:00
Florent Kermarrec
5106bcdc0c core/mac/sram: simplify last_be code 2018-09-07 21:14:17 +02:00
Florent Kermarrec
ce72e34f56 core/mac: pass endianness and use if for last_be gen/check 2018-09-07 10:35:27 +02:00
Florent Kermarrec
4edba99b38 phy: remove s6rgmii (not working correctly). 
Alternative is to create a wrapper around the rgmii_if from Xilinx as it's done in opsis-soc
 2018-07-18 10:09:01 +02:00
Florent Kermarrec
40d91f09c4 phy: use rx_dv instead of dv 2018-07-05 10:48:17 +02:00
Florent Kermarrec
a2dbdd6d2b phy: add a7_1000basex phy (from misoc) 2018-06-29 14:26:19 +02:00
Florent Kermarrec
95849a0fed core/icmp: use buffered=True on buffer to allow tools to use block rams 2018-05-27 07:41:32 +02:00
Florent Kermarrec
79a6ba7709 replace litex.gen imports with migen imports 2018-02-23 13:40:09 +01:00
Felix Held
9dcc7bc65e mac/crc.py: make crc calculation more pythonic 2018-02-21 23:20:03 +01:00
Felix Held
2ceaa74caf clarify the comments in mac/crc.py code 2018-02-21 23:05:32 +01:00
Felix Held
20af2bf201 Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:23:18 +11:00
Florent Kermarrec
2788294834 core/mac/sram: add csr for fifo level of sram reader (for the linux driver) 2017-12-31 07:12:55 +01:00
Florent Kermarrec
c9ec30df2f core/mac: apply changes from misoc: remove gap_checker in rx, add preamble errors, fix preamble checker 2017-12-30 18:32:50 +01:00
Florent Kermarrec
26c01a1627 core/mac/crc: fix crc_error generation 2017-11-01 23:23:02 +01:00
Florent Kermarrec
eaf4acc3f5 core/mac: apply misoc changes (72faa2c) 2017-11-01 21:11:08 +01:00
Tim Ansell
00e6ded2e9 Adding TCP port 1234 to Etherbone dissector. 
LiteEth designs seem to commonly use TCP port 1234.
 2017-09-01 23:16:09 +10:00
Florent Kermarrec
c43fb269a7 frontend/etherbone: timing optimizations 2017-07-19 12:20:17 +02:00
Florent Kermarrec
042d3aee3e frontend/etherbone: fix cd="sys case 2017-07-15 22:10:48 +02:00
Florent Kermarrec
1127e3a615 core/udp: simplify LiteEthUDPCrossbar.get_port when used with cdc 2017-07-01 13:14:13 +02:00
Florent Kermarrec
b870d13d96 global: reset_less optimizations 2017-07-01 11:22:26 +02:00
Florent Kermarrec
34460cec47 core/udp: add cdc support (untested) 2017-06-30 11:01:44 +02:00
Florent Kermarrec
e68e2ed73c frontend/etherbone: add description 2017-04-26 23:43:43 +02:00
Florent Kermarrec
42454a5448 frontend/etherbone: add wishbone slave support (allow extending wishbone bridge over ethernet between boards) 2017-03-30 14:46:30 +02:00
Florent Kermarrec
e1da2df97d core/mac/sram: fix reception of frames larger than mtu 
-use 32bits length CSR (allow software to detect frames larger than mtu)
-drop remaining bytes larger than mtu
 2016-05-01 07:37:24 +02:00
Florent Kermarrec
072969ff58 common: fix eth_mtu (1530 bytes) 2016-05-01 07:09:37 +02:00
Florent Kermarrec
33e36dc4d7 use new Record.connect omit parameter (replace leave_out) 2016-04-21 08:03:31 +02:00
Florent Kermarrec
f55ce1aac6 core/mac: simplify/improve performance of LiteEthMACSRAMReader 
now read data from sram on every clock cycle, allow lower system clock frequency (tested with 50MHz system clock / 125MHz ethernet clock)
 2016-04-03 22:53:02 +02:00
Florent Kermarrec
a189b2c195 phy/s6rgmii: fix missing last signal 2016-03-29 16:53:37 +02:00
Florent Kermarrec
657ba4cb16 global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 21:36:07 +01:00
Florent Kermarrec
9cd7dc3088 global: use SyncFIFO instead of Buffer 2016-03-16 19:45:43 +01:00
Florent Kermarrec
aff07c6809 global: use new StrideConverter 2016-03-16 17:01:13 +01:00
Florent Kermarrec
51f56e79dd global: remove use of sop 2016-03-16 16:22:00 +01:00
Florent Kermarrec
1f46aaeb55 core/mac: remove frontend directory (too much directories) and some cleanup 2016-03-15 20:09:30 +01:00
Florent Kermarrec
c3e15e7f7b core/mac: use fifo_depth of 64 for all phys 2016-03-15 19:41:53 +01:00
Florent Kermarrec
32243934fb global: use stream.Endpoint instead of Sink/Source (deprecated) 2016-03-15 16:50:00 +01:00
Florent Kermarrec
9593e29756 global: use 192.168.1.100 (remote)/ 192.168.1.50 (local) IP addresses 2016-03-15 15:40:06 +01:00
Florent Kermarrec
b7efe0fd46 phy: remove pads_register parameter (does not save enough, priority to simplicity) 2016-03-15 15:33:36 +01:00
Florent Kermarrec
5583fe5543 phy/s6rgmii: RenameClockDomains --> ClockDomainsRenamer 2016-02-24 23:51:31 +01:00
Florent Kermarrec
d38612db0c remove use of Record.connect 2015-12-27 12:26:01 +01:00
Florent Kermarrec
1f19518d63 phy/common: add LiteEthPHYHWReset and use it on phys 2015-12-09 16:57:02 +01:00
Florent Kermarrec
54d7c6620b phy: add mdio on all phys 2015-12-09 16:42:35 +01:00
Florent Kermarrec
ad0b4a165f phy: rmii refactor (tested) 2015-12-07 15:46:15 +01:00
Florent Kermarrec
17ce01b58e core/mac/core: use fifo depth of 8 for RMII phy 2015-12-04 09:38:59 +01:00
Florent Kermarrec
6006186fe0 phy/rmii: use 50MHz (instead of 100Mhz) and use DDROutput to generate ref_clk 2015-12-03 23:47:08 +01:00
Florent Kermarrec
09e6b3a8d7 phy: add s7rgmii 2015-12-01 01:34:06 +01:00
Florent Kermarrec
6b39b0f674 phy: fix clock domains renaming (ClockDomainsRenamer refactoring issue) 2015-11-30 13:04:47 +01:00
Florent Kermarrec
133cb88ead common: small cleanup 2015-11-27 19:51:26 +01:00
Florent Kermarrec
449d84bf11 remove Counter module 2015-11-24 21:02:07 +01:00
Florent Kermarrec
9a7039ef72 use mininal imports 2015-11-24 20:44:00 +01:00
Florent Kermarrec
09dad1b520 phy/rmii: adapt to new syntax and fixes 2015-11-19 15:42:51 +01:00
Florent Kermarrec
f1725d5fd1 ethetbone software is now integrated in LiteX 2015-11-17 12:04:04 +01:00
Florent Kermarrec
34b6994d3c stream/SyncFIFO now exposes fifo level 2015-11-16 16:12:41 +01:00
Florent Kermarrec
94e5c254eb fix some imports 2015-11-14 20:17:47 +01:00
Florent Kermarrec
c1d7f2d427 phy: rename sim to model and remove from autodetect 2015-11-14 03:43:27 +01:00
Florent Kermarrec
e7caf8acfb use stream_packet and stream_sim from litex 2015-11-14 00:42:33 +01:00
Florent Kermarrec
b370c8b2f5 use stream_packet and stream_sim from litex 2015-11-14 00:35:38 +01:00
Florent Kermarrec
7b9dc92b0b for now use our fork of migen 2015-11-13 14:48:53 +01:00
Florent Kermarrec
a032168997 start adapting to new migen/litex 2015-11-12 19:52:59 +01:00
Florent Kermarrec
e2292d17f8 phy/gmii: enable use of gmii phy on non Xilinx devices 2015-10-25 10:57:44 +01:00
Florent Kermarrec
2b6dfa6a7e cleanup (remove use of FlipFlop) 2015-10-24 13:28:09 +02:00
Florent Kermarrec
56773f962f identify some ressources optimization in HW icmp and etherbone 2015-10-24 12:55:49 +02:00
Florent Kermarrec
a6415c08b4 liteeth/phy/mii: use same code than liteeth_mini 2015-10-23 20:15:03 +02:00
Florent Kermarrec
57b671692d core/ip: use decorators on LiteEthIPV4Checksum (cleanup) 2015-10-21 23:39:42 +02:00
Florent Kermarrec
7321e87cbb phy: add RMII phy (not yet tested) assuming 100MHz cd_eth ClockDomain provided externally 2015-10-15 21:20:55 +02:00
Florent Kermarrec
e33937f089 move etherbone packets and record description to software 2015-10-13 21:36:37 +02:00
Florent Kermarrec
e61c229bbb simplify organization (try to regroup layers in single files) 2015-10-02 10:38:43 +02:00
Florent Kermarrec
2b84ec066a software: add uip (contiki) port (tested on lm32 and mor1kx) 2015-09-14 21:41:05 +02:00
Florent Kermarrec
0688532619 software: add lwip port (tested on lm32 and mor1kx) 2015-09-14 21:38:46 +02:00
Florent Kermarrec
58d45c873a liteeth/common: add reverse_bytes, FlipFlop, Counter (will be removed from migen) 2015-09-12 16:27:07 +02:00
Florent Kermarrec
c8545ae06e fix litescope import 2015-09-09 08:26:51 +02:00
Florent Kermarrec
306162096b fix imports 2015-09-08 09:55:43 +02:00
Florent Kermarrec
20fc519410 init repo 2015-09-07 13:29:34 +02:00