ddaab5317e
qmtech_xc7a35 set symbiflow_device, needed when using symbiflow
2021-05-08 18:01:01 +07:00
f2b51b0233
icesugar: map the usb port
2021-05-08 07:34:10 +07:00
e99272cb07
muselab_icesugar: Modify comments a bit.
2021-05-07 08:57:34 +02:00
5ae130661f
Merge pull request #213 from hansfbaier/icesugar
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muselab_icesugar: first basic version which boots
2021-05-07 08:50:50 +02:00
2c2a9db3cc
Merge pull request #212 from hansfbaier/qmtech-xc7a35t
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add QMTECH XC7A35T core board + daughter board
2021-05-07 08:32:16 +02:00
9e86c094c9
Merge pull request #211 from Acathla-fr/master
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Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
2021-05-07 08:30:01 +02:00
c2e0f6026e
muselab_icesugar: first basic version that boots
2021-05-07 11:50:28 +07:00
3bb84b0071
Add initial Blackmagic Decklink Mini 4K support (with UART, DDR3, PCIe, Video Out).
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Mini Monitor 4K and Mini Recorder 4K are almost the same hardware with just changes on
the Video In/Out. For now tests have been done on the Mini Monitor 4K, but the aim is
support both boards in the same platform/target in the future, thus the mini_4k naming.
These boards could be used as affordable Artix7 dev boards for LiteX, to run Linux with
LiteX (512MB of RAM + a Video Framebuffer) or to create custom systems like a fast software
defined signal generator/recorder directly from a PC over PCIe, custom HDMI/SDI video
cards, etc... lots of possibilities :)
2021-05-06 09:47:01 +02:00
eec1078736
add QMTECH XC7A35T core board + daughter board
2021-05-06 05:50:48 +07:00
213d100860
Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
2021-05-04 12:19:21 +02:00
7d651a9a17
siglent_sds1104xe: Switch to VideoVGAPHY and adjust timings.
2021-04-29 10:41:19 +02:00
f7ee3fa454
sds1104xe: Framebuffer fixes.
2021-04-27 19:32:03 +02:00
228a9650d4
sqrl_acorn: Add flashing/reload support when used with PCIe, fix JTAG flash.
2021-04-21 17:00:40 +02:00
443b954c0c
platforms/xilinx_kcu105: Add Pmod0/1 connectors.
2021-04-19 15:11:43 +02:00
d2eabd112d
Add E-Elements Ego1 initial board support.
2021-04-12 08:20:46 +02:00
cd3d4c826e
Add Trenz te0725 initial board support.
2021-04-12 08:16:45 +02:00
5519c931f8
xilinx_alveo_u280: Fix DDR4 (tested with 8 modules on C0 and C1).
2021-04-12 08:07:16 +02:00
d830ef8393
Merge pull request #200 from rdolbeau/wukong_ethfix_fb
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Qmtech Wukong: updates
2021-04-11 14:44:25 +02:00
bad8821c2d
platforms/ecpix5: Add ULPI signals.
2021-04-11 11:12:56 +02:00
d5318dcb03
Qmtech Wukong: updates
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fix ethernet clock (it's a GMII), add FB support over the HDMI connector (hdmi clock set from the resolution)
2021-04-10 16:26:25 +02:00
03accabc25
lpddr4_test_board: Add antmicro vendor prefix.
2021-03-31 09:48:23 +02:00
a834985e00
Add target for LPDDR4 Test Board
2021-03-30 14:50:02 +02:00
a48def1352
rhsresearchllc_litefury: Remove since already supported by ./acorn.py --variant=cle-101.
2021-03-26 23:54:56 +01:00
4329a69128
sqrl_acorn_cle_215: Rename to sqrl_acorn and add support for all variants (CLE-101, 215 and 215+).
2021-03-26 23:52:36 +01:00
52ded1c9aa
terasic_deca: Fix default_clk_name.
2021-03-26 22:43:40 +01:00
b54eed0859
terasic_sockit: Review/Cleanup for consistency with other boards.
2021-03-26 22:39:19 +01:00
53a767c85c
terasic_deca: Review/Cleanup for consistency with other boards.
2021-03-26 22:12:13 +01:00
8c0ddd140b
terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 10:46:37 +07:00
333fb362ca
Move import Compat directly to litex_boards.__init__.py and simplify.
2021-03-25 16:47:47 +01:00
062b899e29
platforms/targets: Add mode Vendor prefixes.
2021-03-25 16:19:11 +01:00
5253a3c43e
test/ci: Fix/Update.
2021-03-25 14:21:13 +01:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
cb4e00c3f2
colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-20 07:56:59 +09:00
7a1fe7a6bc
nexys4ddr: add pmod connectors, and optional sdcard on pmodd
2021-03-19 12:33:11 -04:00
6d32c76aa2
Merge pull request #188 from hansfbaier/848-deca-video-bloat
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fix #848 : allow ram initialization in bitstream to enable block ram
2021-03-19 11:11:05 +01:00
ddd46205aa
ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-18 15:06:35 +01:00
4330769add
minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY.
2021-03-18 14:10:42 +01:00
b7d86df01d
fix #848 : allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value
2021-03-18 08:41:19 +07:00
8b69ee57a6
arrow_sockit: get video terminal working on VGA
2021-03-16 12:31:41 +07:00
0e2d9a571e
alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).
2021-03-10 11:23:27 +01:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
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Alveo U280 board
2021-03-10 11:16:32 +01:00
7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x
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crosslink_nx_vip: Remove constraints for hard MIPI pins
2021-03-10 11:13:49 +01:00
47faaf20d5
deca: Integrate Video Terminal (untested, resource issue).
2021-03-09 15:02:30 +01:00
496cae54ff
crosslink_nx_vip: Remove constraint for MIPI pins
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 14:26:40 +00:00
547157c9ca
crosslink_nx_vip: Fix cam_reset IO configuration
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:26:56 +00:00
542001dddf
crosslink_nx_vip: Split camera MCLK to its own resource
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:18:37 +00:00
51a0bbfa65
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
2021-03-03 18:05:24 +01:00
3af8ec0c8d
targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal.
2021-03-03 17:10:22 +01:00
7e3b8ab3b5
icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
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Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash
https://twitter.com/enjoy_digital/status/1365324823447171074
2021-03-03 16:21:04 +01:00
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod
2021-02-25 09:37:34 +01:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
2b49082696
platforms/arty: Add numato sd card pmod
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It has a different layout.
Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817
Expansion Pin SD SPI SD Artix Arty-A7 PMOD PIN PMOD Index
2 DATA_2 D4 JD1 1 0
4 CMD MOSI D3 JD2 2 1
6 DATA_0 MISO F4 JD3 3 2
CD F3 JD4 4 3
1 DATA_3 CS_N E2 JD7 7 4
3 CLK CLK D2 JD8 8 5
5 DATA_1 H2 JD9 9 6
G2 JD10
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk
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fix vc707 default_clk_period
2021-02-23 12:17:45 +01:00
a90c0bc8f9
platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope .
2021-02-22 13:45:48 +01:00
09c3bd616b
Merge branch 'master' into vc707_clk
2021-02-19 22:49:46 -08:00
c32e790421
vc707: fix default clock frequency
2021-02-19 22:47:18 -08:00
1fcd96971d
Merge pull request #172 from hansfbaier/master
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sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
2021-02-16 22:44:52 +01:00
975150ca68
platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.
2021-02-16 17:32:41 +01:00
9baa9d5d83
platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811 ).
2021-02-12 15:23:17 +01:00
9a94e835c3
sockit: Add an option to plug in an UART via the GPIO daughter board
2021-02-10 14:52:19 +07:00
7442c2dada
vc707.py: clk156 add missing constraint
2021-02-08 19:04:01 -08:00
fef9dd036a
platforms/de0nano: directly use JP1 connector for serial pins.
2021-02-08 09:52:26 +01:00
ea58ef94a7
Merge pull request #170 from hansfbaier/master
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arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-04 16:44:58 +01:00
cdff5e3ca3
nexys_video: enable symbiflow toolchain
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Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 14:52:54 +01:00
c64e13f687
arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-03 09:37:03 +07:00
a1d830566a
added ddr4_sdram_c1 constraints
2021-02-01 12:22:41 -05:00
7c48af9b50
tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
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./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
2021-02-01 13:32:01 +01:00
6cce07d9db
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
2021-02-01 13:31:44 +01:00
0831b33285
tec0117: fix copyrights.
2021-02-01 13:31:39 +01:00
5e4b29c0b5
sockit: Fix cable name, default to jtag_atlantic
2021-02-01 11:48:06 +07:00
601c297c8f
Merge pull request #164 from rdolbeau/ztex213
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Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 21:43:07 +01:00
31df53ef0a
Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)
2021-01-30 13:19:08 +01:00
027e57b851
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 05:19:18 -05:00
abccd12058
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
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Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
2021-01-29 22:28:40 +01:00
345feddce9
ECPIX-5: ddram: Add missing address pin.
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Fixes #161
2021-01-29 16:03:43 +03:00
7525b8772f
platforms/fpc_iii: avoid dummy pin on ethernet.rst_n.
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rst_n is optional in LiteEth's PHYs.
2021-01-29 09:33:33 +01:00
19767e1a2a
platforms/fpc_iii: avoid using dummy pin on odt.
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Now possible with 2f5784432d
2021-01-29 09:30:54 +01:00
6c6d8a1393
platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance.
2021-01-29 08:41:10 +01:00
1916677dc9
use VREF constraint for DDR4 C0
2021-01-28 19:58:38 -05:00
4e5bb1bf1e
Add FPC-III board support.
...
FPC-III is the Free Permutable Computer; details on the board are
available from:
https://repo.or.cz/fpc-iii.git
2021-01-28 09:51:42 -07:00
aa20fca1f1
ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3.
2021-01-28 14:25:16 +01:00
691bfd8b70
Merge pull request #159 from euryecetelecom/master
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Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
2021-01-28 14:01:01 +01:00
bd716d956f
netv2: add device variant to allow 100T as well
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-01-28 13:19:53 +01:00
9beba7209d
Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration
2021-01-28 12:00:28 +01:00
84656a9c2e
re-compare and adjust to u250
2021-01-26 23:03:09 -05:00
c3fa0eac8b
Add colorlight i5 board support
2021-01-27 11:44:59 +09:00
537f494cbb
arrow_sockit: review/harmonize with others boards.
2021-01-25 09:14:46 +01:00
4adc1b14c4
platforms/de0nano: use separator for connectors.
2021-01-25 08:58:12 +01:00
bbaa2fdc98
Merge pull request #149 from hansfbaier/master
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Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
2021-01-25 08:55:48 +01:00
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash
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ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-24 21:22:35 +01:00
8132f9f65b
Merge pull request #154 from euryecetelecom/master
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Fix SDCard issue when no SDCard inserted in ECPIX5 board.
2021-01-24 21:14:58 +01:00
cae51c0c24
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-23 14:44:26 -06:00
aa771e9ff4
de0-nano: add connectors
2021-01-23 20:18:15 +07:00
c9f0745d54
sockit: add board definitions for Terasic SocKit
2021-01-23 20:17:38 +07:00
b386ee5059
Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence.
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https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
2021-01-20 18:02:13 +01:00
a678672fc9
ecpix5: add option to select ECP5 device
2021-01-19 01:22:52 +03:00
7a738245af
fix bitstream problem
2021-01-14 21:53:25 -05:00
5a73eb0b6d
initiate target and platform for alveo_u280 board
2021-01-14 18:35:43 -05:00
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard
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genesys2: LiteSDCard support
2021-01-07 08:12:24 +01:00
4eb0026a69
genesys2: add "rst" and "cd" signals to (spi-)sdcard records
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:10:13 -05:00
Hans Baier
Florent Kermarrec
Fabien
Shinken Sanada
Sergiu Mosanu
Vegard Storheil Eriksen
Romain Dolbeau
Jędrzej Boczar
Kaz Kojima
Gabriel Somlo
gatecat
Joel Stanley
Michael Betz
Jan Kowalewski
Guillaume REMBERT
Vadzim Dambrouski
Gary Wong
Alessandro Comodi
Blake Smith
Vadim Kaushan