d87b8b3c66
zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
...
Ease switching between ddram_32 and ddram_64.
2020-02-27 10:05:17 +01:00
8ecfb13f3c
zcu104: add copyrights
2020-02-27 09:57:26 +01:00
22b0449509
Merge pull request #47 from antmicro/zcu104
...
Add support for ZCU104 board
2020-02-27 09:51:54 +01:00
608541d5b8
add ZCU104 board
2020-02-26 13:53:21 +01:00
e516ff3452
vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:51 +01:00
9d2ca50c5f
kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:35 +01:00
83d2c71099
platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks
2020-02-25 18:32:42 +01:00
4a84e9b08a
targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool
2020-02-25 12:47:08 +01:00
f279fe9d33
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
2020-02-25 10:35:18 +01:00
3581df5af6
vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported)
2020-02-25 09:41:53 +01:00
88a1f80db1
vc707/vcu118: use proper copyrights
2020-02-25 09:03:52 +01:00
373e74f435
add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
2020-02-24 14:20:47 -05:00
2cf4e084ec
platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
2020-02-23 10:01:41 +01:00
f72e7bd314
Merge pull request #41 from lromor/fix-wrong-import
...
Changed wrong imports for fomu board.
2020-02-12 18:48:13 +07:00
ec30cc05c3
Changed wrong imports for fomu board.
2020-02-12 12:40:07 +01:00
c94360c2e0
targets: avoid direct use of mem_decoder.
2020-02-11 21:59:42 +01:00
4edf196911
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:45:35 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
7a24406b2e
targets: fomu: fix compatibility for when a cpu is added
...
Things weren't quite right for adding a CPU. This fixes that by
correcting the placer arguments, memory map, and USB type.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-03 08:58:54 +08:00
0627f55dca
de10nano: cleanup a bit, rename SDRAMSoC to MiSTerSDRAMSoC and argument to --with-mister-sdram to make it clear that it's using the MiSTer SDRAM extension board.
2020-01-31 09:29:02 +01:00
cf9a9ff91b
de10nano: update copyrights, remove trailing whitespaces
2020-01-31 09:13:36 +01:00
36e1f1fe75
rename sw to user_sw
2020-01-30 05:01:46 -08:00
1631b071c3
finish up sdram, passes memtest
2020-01-30 03:41:44 -08:00
5091a1b40a
WIP sdram module option
2020-01-29 13:59:57 -08:00
3a6a9258ce
add de10 nano board
...
add iostandard to hdmi
2020-01-29 00:21:51 -08:00
2ec6bc0bdc
colorlight_5a_75b: add disclaimer
2020-01-23 14:13:13 +01:00
55c0b781e4
colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt)
2020-01-23 13:16:36 +01:00
4fb89fc9c5
colorlight_5a_75b: set RGMII tx/rx_delay to 0ns in the FPGA (added by PCB/PHY)
2020-01-23 09:39:48 +01:00
dcc65b347d
targets/colorlight_5a_75b: switch to SoCCore, CPU and Etherbone working :)
...
Tested with:
./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv
Load with following script:
#!/usr/bin/env python3
# Load ---------------------------------------------------------------------------------------------
def load():
import os
f = open("openocd.cfg", "w")
f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
f.close()
os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
exit()
if __name__ == "__main__":
load()
Then start lxserver:
lxserver --udp
And run following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
while True:
if wb.regs.uart_xover_rxempty.read() == 0:
print(chr(wb.regs.uart_xover_rxtx.read()), end="")
sys.stdout.flush()
# # #
wb.close()
2020-01-22 15:57:52 +01:00
c07e4a6b3a
colorlight_5a_75b: fix rst_n
2020-01-22 14:57:48 +01:00
8da8ed7a0e
colorlight_5a_75b/v7.0: update eth_clocks/rx pinout, remove FIXME
2020-01-22 14:56:17 +01:00
bb805999cb
platforms/colorlight_5a_75b: fix 6.1 used_led_n/user_btn_n thanks @smunaut
2020-01-22 12:43:37 +01:00
43badd162e
colorlight_5a_75b/v6.1: add led/btn and remove FIXME on sdram now that clarified
2020-01-22 11:05:08 +01:00
1d9e349093
partner: add colorlight_5a_75b initial support
2020-01-22 09:51:00 +01:00
07067301d5
targets/linsn_rv901t: cleanup arguments
2020-01-22 09:04:28 +01:00
8113b491db
aller/nereid/tagus: update litepcie
2020-01-21 21:26:23 +01:00
684c1640bb
add Linsn RV901T support
2020-01-18 21:40:04 +01:00
0e4569a48a
platforms/camlink_4k: remove #!/usr/bin/env python3
2020-01-18 21:35:18 +01:00
e72cd1468c
platforms/ac701: fix eth indent
2020-01-18 21:34:50 +01:00
908539d49f
targets/nexys4ddr: fix typo
2020-01-17 13:15:22 +01:00
bb99a8dd0c
targets/kcu105: remove main_ram_size_limit
2020-01-17 12:09:53 +01:00
eca9bf10ae
mimas_v7: cleanup, make it similar to others boards
2020-01-16 11:24:09 +01:00
54f39b600a
mimas_a7: fix copyrights
2020-01-16 11:02:11 +01:00
8d298951a8
Merge pull request #37 from feliks-montez/master
...
Add Mimas A7 board support
2020-01-16 11:00:32 +01:00
f9619c4a8f
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
2020-01-16 10:51:35 +01:00
fd1e655700
targets: cleanup EthernetSoC
2020-01-16 10:28:09 +01:00
206ec34551
platforms/mimas_a7: add support
2020-01-14 23:31:03 -05:00
9f1c3305b6
targets/mimas_a7: add support
2020-01-14 23:30:49 -05:00
50d550c911
kx2: cleanup, fix copyright
2020-01-13 17:22:33 +01:00
3811b58f32
Merge pull request #36 from Marrkson/master
...
ADD: KX2 and DDR3 support
2020-01-13 17:07:16 +01:00
c109b36fb9
travis: update/fix
2020-01-13 17:00:01 +01:00
028d4a78aa
targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
2020-01-13 15:20:37 +01:00
13e5ca03a5
ADD: KX2 and DDR3 support
2020-01-13 14:21:54 +01:00
beccf670e5
hadbadge: fix _CRG
2020-01-11 10:46:23 +01:00
15f3457aea
platforms/de0nano/serial: add gpio names in comment
2020-01-10 18:53:52 +01:00
94ba343daf
targets/ac701: cpu_reset is active high
2020-01-10 18:53:14 +01:00
ab01f70e5c
platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq
2020-01-09 21:56:01 +01:00
7afe3dc674
platforms/targets: sync with litex
2020-01-09 21:10:59 +01:00
4192b20f09
targets: cleanup Altera CRGs
2020-01-09 19:46:39 +01:00
9e9fc5ef78
platforms: always use 1e9/clk_freq for default_clk_period
2020-01-09 19:28:50 +01:00
fe23881348
Merge pull request #33 from msloniewski/master
...
targets/de10lite: use external clock for sys directly
2020-01-09 19:23:55 +01:00
aaf8d54c6a
targets/de10lite: use AsyncResetSynchronizer for clock domains
...
At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
2020-01-09 18:47:13 +01:00
d08dfdb808
platforms/nexys4ddr: add sdcard pins (sync w. litex commit #e99740e8)
2020-01-09 09:25:19 -05:00
babbc676eb
targets: cleanup ECP5 CRGs
2020-01-09 14:24:18 +01:00
82601ff700
hadbadge: remove speed_grade workaround, now passed to trellis from device.
2020-01-08 19:44:35 +01:00
1f300bb03e
add initial camlink_4k support
2020-01-08 09:56:37 +01:00
c0e4578bea
targets/hadbadge: cleanup/simplify (keep things similar to ulx3s) and add copyrights
2020-01-07 10:29:58 +01:00
85c4f76eba
platform/hadbadge: cleanup/simplify and add copyrights
2020-01-07 10:29:01 +01:00
829898d652
Merge pull request #31 from pdp7/master
...
add the Hackaday Supercon ECP5 badge
2020-01-07 09:48:15 +01:00
ab41cf5b79
Update ecp5_evn.py
2020-01-07 01:55:59 +01:00
b3f175c064
add the Hackaday Supercon ECP5 badge
...
Add the Hackaday Supercon 2019 badge which has an ECP5 FPGA:
https://hackaday.io/project/167255-2019-hackaday-superconference-badge
These changes are from Michael Welling's fork:
https://github.com/mwelling/linux-on-litex-vexriscv
During Supercon, we trying two approaches:
- use the built-in 16MB QSPI SRAM
- use add-on cartiridge with 32MB SDRAM by Jacob Creedon
We were not able to get the QSPI SRAM working so I've removed
those changes, and I have just added the changes that are needed
to boot Linux with the 32MB SDRAM.
Thanks to Jacob Creedon, Greg Davill and Tim Ansell who helped debug.
KiCad design files for the SDRAM cartridge are available at:
https://github.com/jcreedon/dram-cart/
The SDRAM cartridge PCB is shared at:
https://oshpark.com/shared_projects/IQSl2lid
More information in this blog post:
https://blog.oshpark.com/2019/12/20/
The Hackaday Supercon badge PCB design is here:
https://github.com/Spritetm/hadbadge2019_pcb
2020-01-06 16:59:15 +01:00
f8f2301a3e
Merge pull request #30 from mithro/fomu-update
...
Updating the templates for Fomu.
2020-01-03 08:40:18 +00:00
250706b98c
Updating the templates for Fomu.
2020-01-02 13:55:09 +00:00
2b43a18a3c
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
2019-12-31 18:18:56 +01:00
c96e7c8fb9
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
2019-12-31 18:07:18 +01:00
2259042383
pipistrello: add copyrights
2019-12-31 17:44:24 +01:00
6324433e1c
Merge pull request #28 from zakgi/master
...
Adding initial support for Saanlima's Pipistrello LX45 board
2019-12-31 17:33:25 +01:00
980b0ebda0
targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer)
2019-12-31 17:30:23 +01:00
10e5248bda
targets/de10lite: minor cleanup on import/_CRG
2019-12-31 17:26:09 +01:00
9c5a4f757f
targets/de10lite: add VideoSoC with VGA peripheral
...
Add VideoSoC build option, based on Frank Buss example.
2019-12-30 23:25:43 +01:00
cace17e162
targets/de10lite: refactor setting up clock domains
...
Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
2019-12-30 23:25:43 +01:00
9ed68d129f
platforms/de10lite: add additional configuration
...
Use single image with memory initialization
to make more space for SoC ROM sector.
2019-12-30 23:23:44 +01:00
28753a2c04
platforms/de10lite: remove UART pins from GPIO resource
...
V10 and W10 pins were used in UART periph, causing error
when gpio_0 were requested.
2019-12-30 23:06:58 +01:00
359918c2a2
Comment out template overrides for now.
2019-12-30 19:23:05 +01:00
1f32dcf662
partner: rename orange_crab to orangecrab
2019-12-30 12:07:34 +01:00
8965b01347
partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC
2019-12-30 11:54:53 +01:00
e77afaaef0
partner: add OrangeCrab support ( https://github.com/gregdavill/OrangeCrab )
2019-12-30 11:54:45 +01:00
39e428581f
Adding initial support for Saanlima's Pipistrello LX45 board
2019-12-29 18:29:11 -08:00
48476be9e2
aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address
2019-12-14 22:10:04 +01:00
7184032555
aller/neired/tagus: fix gateware/software build directory
2019-12-14 11:29:15 +01:00
4334ba9527
partner/aller, nereid, tagus: Remove deprecated param
...
get_csr_header parameter with_shadow_base
removed/deprecated in litex 2a8d8c8f. New default
behavior matches the desired behavior in these targets.
2019-12-14 01:04:28 +00:00
3012cf75fe
partner/aller, nereid, tagus: Use updated csr APIs
...
litex commit 8be5824e258b84df240d34636aaa539124b92c65 simplified the handling
of csr regions and constants.
2019-12-14 01:00:52 +00:00
d91458c3e6
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:16:19 +01:00
30ea463b41
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 16:01:59 +01:00
8fa3f09226
partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices.
2019-12-06 15:22:40 +01:00
0a56d86b1a
partner/c10lprefkit: remove FAMILY platform_command (not needed)
2019-12-06 15:21:48 +01:00
5193f7155a
partner/aller,nereid & tagus: fix compilation
2019-12-03 09:37:18 +01:00
f7fbfb4639
partner/community/targets: uniformize, improve presentation
2019-12-03 09:33:08 +01:00
1b1370d086
official/targets: uniformize, improve presentation
2019-12-03 09:07:09 +01:00
4e13b7fdab
targets: fomu: move SoCCore import definition
...
The SoCCore definition used to be available under litex.soc.integration,
however it was removed in
626533ce9d
2019-11-25 12:46:21 +08:00
Florent Kermarrec
Piotr Binkowski
Fei Gao
Gwenhael Goavec-Merou
Sean Cross
Leonardo Romor
Paul Sajna
Feliks
Mark
Marcin Sloniewski
Gabriel Somlo
Arnaud Durand
Drew Fustini
Tim Ansell
Greg Davill
Giammarco Zacheo
Derek Kozel