7d130d6981
targets/pcie: Cleanup.
2021-03-25 17:47:06 +01:00
333fb362ca
Move import Compat directly to litex_boards.__init__.py and simplify.
2021-03-25 16:47:47 +01:00
062b899e29
platforms/targets: Add mode Vendor prefixes.
2021-03-25 16:19:11 +01:00
7633eae360
targets/colorlight_i5: Remove l2-size args (already provided by soc_core_args.
2021-03-25 14:44:52 +01:00
5253a3c43e
test/ci: Fix/Update.
2021-03-25 14:21:13 +01:00
9a45c49918
targets/versa_ecp5: Also add Vendor prefix.
2021-03-25 14:13:32 +01:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
219067ed3a
Merge pull request #190 from kazkojima/colorlight_i5-video
...
colorlight_i5: Integrate Video Terminal and Video Framebuffer with ne…
2021-03-25 10:28:52 +01:00
47bdf5f759
targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
2021-03-25 10:11:24 +01:00
b3786c5e52
fomu/icebreaker: Update Up5KSPRAM import (litex.soc.cores.up5kspram deprecated, still supported for now but triggers a compat notice).
2021-03-24 17:22:55 +01:00
5995769b46
targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).
2021-03-24 17:22:51 +01:00
cb4e00c3f2
colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-20 07:56:59 +09:00
7a1fe7a6bc
nexys4ddr: add pmod connectors, and optional sdcard on pmodd
2021-03-19 12:33:11 -04:00
6d32c76aa2
Merge pull request #188 from hansfbaier/848-deca-video-bloat
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fix #848 : allow ram initialization in bitstream to enable block ram
2021-03-19 11:11:05 +01:00
ddd46205aa
ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-18 15:06:35 +01:00
4330769add
minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY.
2021-03-18 14:10:42 +01:00
b7d86df01d
fix #848 : allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value
2021-03-18 08:41:19 +07:00
8b69ee57a6
arrow_sockit: get video terminal working on VGA
2021-03-16 12:31:41 +07:00
75f7120ff9
targets/Ultrascale: Fix build since idelay's reset is now handled by the PLL (with_reset=True).
2021-03-11 10:00:06 +01:00
8d3aaa8ea9
targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).
2021-03-11 09:48:26 +01:00
0e2d9a571e
alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).
2021-03-10 11:23:27 +01:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
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Alveo U280 board
2021-03-10 11:16:32 +01:00
7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x
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crosslink_nx_vip: Remove constraints for hard MIPI pins
2021-03-10 11:13:49 +01:00
61f44739d7
Merge pull request #185 from stffrdhrn/arty-jtagbone
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arty: Add an option to enable jtagbone
2021-03-10 11:12:20 +01:00
47faaf20d5
deca: Integrate Video Terminal (untested, resource issue).
2021-03-09 15:02:30 +01:00
8fb80053f7
targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).
2021-03-08 17:39:13 +01:00
496cae54ff
crosslink_nx_vip: Remove constraint for MIPI pins
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 14:26:40 +00:00
9cdcb8cb43
ecpix5: Add Etherbone (--with-etherbone).
2021-03-08 13:45:09 +01:00
52ce49cf0c
arty: Add an option to enable jtagbone
...
Then adds jtagbone for arty. I have tested with the following
litex_server and it seems to work fine.
litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg
Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.
2021-03-08 07:05:54 +09:00
6139bd7eba
Merge pull request #183 from gatecat/vip_split_mclk
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crosslink_nx_vip: Camera IO fixes
2021-03-06 11:20:53 +01:00
e280bff1ec
targets/video: Simplify/Cleanup integration.
2021-03-05 14:40:27 +01:00
ce669ac8cd
targets/nexys_video: Add optional VideoTerminal/VideoFramebuffer.
2021-03-05 14:33:22 +01:00
547157c9ca
crosslink_nx_vip: Fix cam_reset IO configuration
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:26:56 +00:00
542001dddf
crosslink_nx_vip: Split camera MCLK to its own resource
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:18:37 +00:00
21207533b0
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
2021-03-04 19:49:03 +01:00
71652e8d44
icebreaker: Lower VideoTerminal resolution to use default 24MHz sys_clk.
2021-03-04 18:29:21 +01:00
253d8129af
nexys4ddr: Integrate simple VideoFrameBuffer.
2021-03-03 20:00:31 +01:00
51a0bbfa65
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
2021-03-03 18:05:24 +01:00
465a95d2a6
icebreaker/nexys4ddr: Use new LiteXSoC's add_video_terminal method to add the Video Terminal.
2021-03-03 17:47:20 +01:00
3af8ec0c8d
targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal.
2021-03-03 17:10:22 +01:00
7e3b8ab3b5
icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
...
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash
https://twitter.com/enjoy_digital/status/1365324823447171074
2021-03-03 16:21:04 +01:00
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod
2021-02-25 09:37:34 +01:00
768c10c630
targets/arty: rebase/merge PR179, rename adaptor to adapter.
2021-02-25 09:36:26 +01:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
98c80f0b2b
Merge pull request #177 from antmicro/arty-dynamic-ip
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target/arty: add eth_ip_configurable switch
2021-02-24 09:29:55 +01:00
08ccf384aa
targets/arty: Allow selection of sdcard mod adaptor
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The default stays with the Digilent/Antmicro layout, but the user can
optionally provide --sdcard-adaptor numato to use the Numato layout.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
2b49082696
platforms/arty: Add numato sd card pmod
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It has a different layout.
Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817
Expansion Pin SD SPI SD Artix Arty-A7 PMOD PIN PMOD Index
2 DATA_2 D4 JD1 1 0
4 CMD MOSI D3 JD2 2 1
6 DATA_0 MISO F4 JD3 3 2
CD F3 JD4 4 3
1 DATA_3 CS_N E2 JD7 7 4
3 CLK CLK D2 JD8 8 5
5 DATA_1 H2 JD9 9 6
G2 JD10
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
ae0d4dc0d8
target/arty: add eth_dynamic_ip switch
2021-02-23 21:01:27 +01:00
aad8154e3a
targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.
2021-02-23 15:27:50 +01:00
5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk
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fix vc707 default_clk_period
2021-02-23 12:17:45 +01:00
a90c0bc8f9
platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope .
2021-02-22 13:45:48 +01:00
09c3bd616b
Merge branch 'master' into vc707_clk
2021-02-19 22:49:46 -08:00
c32e790421
vc707: fix default clock frequency
2021-02-19 22:47:18 -08:00
11405d9ee3
targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.
2021-02-18 19:30:05 +01:00
1fcd96971d
Merge pull request #172 from hansfbaier/master
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sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
2021-02-16 22:44:52 +01:00
975150ca68
platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.
2021-02-16 17:32:41 +01:00
9baa9d5d83
platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811 ).
2021-02-12 15:23:17 +01:00
9a94e835c3
sockit: Add an option to plug in an UART via the GPIO daughter board
2021-02-10 14:52:19 +07:00
7442c2dada
vc707.py: clk156 add missing constraint
2021-02-08 19:04:01 -08:00
fef9dd036a
platforms/de0nano: directly use JP1 connector for serial pins.
2021-02-08 09:52:26 +01:00
ea58ef94a7
Merge pull request #170 from hansfbaier/master
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arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-04 16:44:58 +01:00
38242b713f
Merge pull request #171 from antmicro/symbiflow_nexys_video_support
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nexys_video: enable symbiflow toolchain
2021-02-04 16:42:34 +01:00
e6d05001aa
use parameter for dram channel 0 or 1 and LedChaser
2021-02-03 17:29:30 -05:00
cdff5e3ca3
nexys_video: enable symbiflow toolchain
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Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 14:52:54 +01:00
c64e13f687
arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-03 09:37:03 +07:00
8692ed462f
targets/colorlight_i5: use .bit stream instead of .svf when loading.
2021-02-03 08:17:24 +09:00
31d7f810e7
use SDRAM C1 sysclk and constraints
2021-02-02 11:15:25 -05:00
f32c61d5d2
Merge pull request #163 from garytwong/friendly-incompatible-options
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Be friendlier about incompatible options.
2021-02-02 08:51:46 +01:00
a1d830566a
added ddr4_sdram_c1 constraints
2021-02-01 12:22:41 -05:00
7c48af9b50
tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
...
./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
2021-02-01 13:32:01 +01:00
51c5d69586
targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources.
2021-02-01 13:31:56 +01:00
538878ce13
tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?).
2021-02-01 13:31:51 +01:00
6cce07d9db
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
2021-02-01 13:31:44 +01:00
0831b33285
tec0117: fix copyrights.
2021-02-01 13:31:39 +01:00
5e4b29c0b5
sockit: Fix cable name, default to jtag_atlantic
2021-02-01 11:48:06 +07:00
601c297c8f
Merge pull request #164 from rdolbeau/ztex213
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Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 21:43:07 +01:00
31df53ef0a
Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)
2021-01-30 13:19:08 +01:00
027e57b851
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 05:19:18 -05:00
99e2f04ee5
Be friendlier about incompatible options.
...
Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s. That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.
2021-01-29 18:08:38 -07:00
abccd12058
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
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Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
2021-01-29 22:28:40 +01:00
edb99797aa
targets/tec0117: minor cleanups.
2021-01-29 21:25:10 +01:00
345feddce9
ECPIX-5: ddram: Add missing address pin.
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Fixes #161
2021-01-29 16:03:43 +03:00
7525b8772f
platforms/fpc_iii: avoid dummy pin on ethernet.rst_n.
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rst_n is optional in LiteEth's PHYs.
2021-01-29 09:33:33 +01:00
19767e1a2a
platforms/fpc_iii: avoid using dummy pin on odt.
...
Now possible with 2f5784432d
2021-01-29 09:30:54 +01:00
3deeb69531
targets/fpc_iii: review/cleanup to increase similarities with others targets to ease maintenance.
2021-01-29 08:46:31 +01:00
6c6d8a1393
platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance.
2021-01-29 08:41:10 +01:00
1916677dc9
use VREF constraint for DDR4 C0
2021-01-28 19:58:38 -05:00
4e5bb1bf1e
Add FPC-III board support.
...
FPC-III is the Free Permutable Computer; details on the board are
available from:
https://repo.or.cz/fpc-iii.git
2021-01-28 09:51:42 -07:00
9bd667720d
targets/ecpix5: add LedChaser with red leds.
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Fits nicely LambdaConcept colors and Blue/Green leds are too bright and would need to be controlled through a PWM.
2021-01-28 14:29:07 +01:00
aa20fca1f1
ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3.
2021-01-28 14:25:16 +01:00
691bfd8b70
Merge pull request #159 from euryecetelecom/master
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Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
2021-01-28 14:01:01 +01:00
bd716d956f
netv2: add device variant to allow 100T as well
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-01-28 13:19:53 +01:00
9beba7209d
Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration
2021-01-28 12:00:28 +01:00
aef78831c8
colorlight_i5: Use tx_delay=0 for LiteEthPHYRGMII instead of target specifig bios initialization
2021-01-27 18:19:27 +09:00
84656a9c2e
re-compare and adjust to u250
2021-01-26 23:03:09 -05:00
c3fa0eac8b
Add colorlight i5 board support
2021-01-27 11:44:59 +09:00
5fd04a97ea
targets/netv2/pcie: reduce max_pending_requests to 2 to reduce resource usage.
2021-01-26 11:01:51 +01:00
d256cc8bd6
camlink_4k: disable leds when serial is used (since pin is shared).
2021-01-25 12:19:29 +01:00
1e1bec10c4
orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.
2021-01-25 11:52:59 +01:00
537f494cbb
arrow_sockit: review/harmonize with others boards.
2021-01-25 09:14:46 +01:00
4adc1b14c4
platforms/de0nano: use separator for connectors.
2021-01-25 08:58:12 +01:00
bbaa2fdc98
Merge pull request #149 from hansfbaier/master
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Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
2021-01-25 08:55:48 +01:00
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash
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ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-24 21:22:35 +01:00
8132f9f65b
Merge pull request #154 from euryecetelecom/master
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Fix SDCard issue when no SDCard inserted in ECPIX5 board.
2021-01-24 21:14:58 +01:00
72985c72ca
Merge pull request #153 from Disasm/ecpix5-add-45f
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ECPIX-5: add option to select ECP5 device
2021-01-24 21:14:14 +01:00
cae51c0c24
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-23 14:44:26 -06:00
aa771e9ff4
de0-nano: add connectors
2021-01-23 20:18:15 +07:00
c9f0745d54
sockit: add board definitions for Terasic SocKit
2021-01-23 20:17:38 +07:00
23760e2eae
orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC).
2021-01-22 22:55:02 +01:00
b386ee5059
Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence.
...
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
2021-01-20 18:02:13 +01:00
a678672fc9
ecpix5: add option to select ECP5 device
2021-01-19 01:22:52 +03:00
e71a4940c0
nexys4ddr: etherbone support
2021-01-15 12:14:40 -05:00
7a738245af
fix bitstream problem
2021-01-14 21:53:25 -05:00
5a73eb0b6d
initiate target and platform for alveo_u280 board
2021-01-14 18:35:43 -05:00
6a5f2f59a6
targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands.
...
This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.
Also remove un-needed cd_sys2x_eb.
2021-01-12 18:57:22 +01:00
9ff90eb9fe
targets/c10lprefkit: fix default sys-clk-freq.
2021-01-12 16:15:52 +01:00
0a7443d273
targets/orangecrab: make usr_btn optional to fix compilation with revision 0.1.
2021-01-08 19:30:37 +01:00
ae5494d7b6
orangecrab: defaults to USB-ACM UART.
2021-01-08 19:01:41 +01:00
c6e75122d9
sds1104xe: defaults to Crossover UART.
2021-01-08 19:00:41 +01:00
ab72f69937
targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.
2021-01-08 18:50:01 +01:00
0ee62dd681
add etherbone ip address option for relevant boards
2021-01-08 18:44:31 +01:00
869cce2bba
targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip.
...
eth-ip will also be used to configure Ethernet IP addresss.
2021-01-07 09:26:38 +01:00
c829a47c31
targets/colorlight_5a_75x: Automatically disable Led Chaser when serial is used.
2021-01-07 09:17:28 +01:00
adbcc81ecf
Merge pull request #145 from hansfbaier/master
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colorlight: Add option for etherbone ip address and LED chaser
2021-01-07 09:08:43 +01:00
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard
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genesys2: LiteSDCard support
2021-01-07 08:12:24 +01:00
d2d17e00a2
Merge pull request #142 from geertu/master
...
platforms/ecp5: Fix slewrate configuration
2021-01-07 08:11:30 +01:00
d73bd2f7ce
targets/xilinx: add comment on sys_clk to pll.clkin false path.
2021-01-07 08:01:54 +01:00
1ac1c6857f
targets/xilinx: add false path constraint between sys_clk and pll.clkin.
...
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
2021-01-07 00:02:46 +01:00
0d69cfa6b0
colorlight: make LEDs optional
2021-01-05 08:03:26 +07:00
4bec17e1a7
colorlight: Add option for etherbone ip address
2021-01-05 07:49:44 +07:00
2589d9f704
genesys2: add (spi-)sdcard build options
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:57:21 -05:00
4eb0026a69
genesys2: add "rst" and "cd" signals to (spi-)sdcard records
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:10:13 -05:00
4a95b94dbf
platforms/ecp5: Fix slewrate configuration
...
When building linux-on-litex-vexriscv for OrangeCrab:
Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)
Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW". Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-01-04 17:08:51 +01:00
fe67766fb7
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
2021-01-04 11:38:07 +01:00
0e3c03f2f6
mercury_xu5: remove unneeded cmd_latency=0 (now defaulting to 0).
2021-01-04 10:48:34 +01:00
5cc49bafbd
orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press).
2021-01-04 09:42:05 +01:00
1fb24d4c71
orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset.
...
Allows the USB-ACM link to stay up during reset.
2021-01-04 09:05:19 +01:00
06cb49af37
targets/arty: add variant support through --variant args.
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./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
2020-12-29 18:43:14 +01:00
02a81d54e2
targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01).
2020-12-29 16:01:12 +01:00
93779ecb95
platforms/colorlight_5a_75b: revert toolchain args.
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Useful to do tests with Diamiond.
2020-12-29 14:22:42 +01:00
f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0
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add colorlight v8.0 PCB
2020-12-29 14:20:29 +01:00
84098d2de5
targets/qmtech_wukong: submitted target was the platform file, update with target shared in #133 .
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Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.
2020-12-29 14:13:11 +01:00
b67b18caad
qmtech_wukong: review/cleanup platform.
2020-12-29 14:10:49 +01:00
3e6b934961
add colorlight v8.0 PCB
2020-12-29 13:52:13 +01:00
e380f24655
targets/qmtech_wukong: +x.
2020-12-29 13:24:41 +01:00
4b721eded7
add QmTech Wukong board support.
2020-12-29 13:20:42 +01:00
9beaf25822
nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue.
2020-12-24 10:15:29 +01:00
2a04c5c74e
nexys4ddr: add support for litexvideo VGA Terminal
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This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.
The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
2020-12-23 02:24:18 +05:30
f6a106cdf4
Fix orangecrab target
2020-12-20 01:07:43 +03:00
00fc2c5166
targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM.
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Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
2020-12-16 11:52:58 +01:00
Florent Kermarrec
Kaz Kojima
Gabriel Somlo
Hans Baier
gatecat
Stafford Horne
Joel Stanley
Aleksandra Swierkowska
Michael Betz
Sergiu Mosanu
Jan Kowalewski
Guillaume REMBERT
Romain Dolbeau
Gary Wong
Vadzim Dambrouski
Alessandro Comodi
Blake Smith
Vadim Kaushan
Geert Uytterhoeven
la6m
Shinken Sanada
Sahaj Sarup