cd3a51ada6
litescope: fix missing source ack on LiteScopeWishboneBridge
2015-05-01 20:44:57 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
23126415d3
litescope: use full name in io.py
2015-05-01 17:49:31 +02:00
da0fe2ecfb
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.
...
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
2015-05-01 16:22:26 +02:00
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
a6f290ac16
liteusb: add ft2232h_sync_tb
2015-04-28 19:05:34 +02:00
28c50112a4
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests
2015-04-28 19:01:03 +02:00
30eed19283
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
7fc96da51c
misoclib/com/uart: remove liteeth dependency (copy/paste error)
2015-04-28 18:53:46 +02:00
d253adee61
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend
2015-04-28 18:51:40 +02:00
453279a7c8
litesata: cleanup link
2015-04-27 15:33:01 +02:00
dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
20dd6d3047
litepcie: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:05:40 +02:00
1ef81c4d24
litesata: split hdd model (phy, link, transport, command & hdd) and update simulations
2015-04-27 14:51:03 +02:00
ded3f22574
litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores)
2015-04-27 14:48:14 +02:00
fe867ccf33
litesata: remove icarus_workaround.patch (obsolete)
2015-04-27 14:44:54 +02:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
07b7c2a13f
liteeth/phy/gmii: add default value for pads_register
2015-04-26 14:54:54 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
130fd19dec
liteeth/core/ip: simplify ip rx checksum control
2015-04-24 11:31:10 +02:00
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
2d56d32009
liteeth/mac/core: simplify and fix padding
2015-04-24 09:36:33 +02:00
ff2d1d9383
litescope: fix read in reg.py
2015-04-20 08:16:31 +02:00
4c0d9f5f36
litescope: remove repeat mode on drivers (not useful) and cleanup
2015-04-18 15:37:38 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
341f635a85
litescope: add PCIe driver (mmap/Sysfs) and use it on litepcie example design
2015-04-18 13:58:20 +02:00
602eaf69c7
litepcie: fix asciiart in make.py
2015-04-17 14:10:32 +02:00
b4b37fb10e
litepcie: add linux driver + utilities (sysfs + dma)
2015-04-17 13:48:34 +02:00
d22d58c7cc
add litepcie core
2015-04-17 13:45:01 +02:00
93de581931
soc: add shadow_address parameter
...
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
2015-04-17 13:42:29 +02:00
9666629c4f
soc/cpuif: add with_access_functions parameter
...
When don't necessary need access functions in our csr.h (for example with an X86 CPU)
2015-04-17 13:26:38 +02:00
958f149992
litesata/test: fix PYTHONPATH
2015-04-16 19:49:46 +08:00
2ccb5655c9
global: more pep8
...
we will have to continue the work... volunteers are welcome :)
2015-04-13 18:02:26 +02:00
fc68d915c1
global: pep8 (E261, E271)
2015-04-13 17:16:12 +02:00
71d0f6ab2a
global: pep8 (W262)
2015-04-13 17:02:59 +02:00
f3c010c1d5
global: pep8 (E225)
2015-04-13 17:01:05 +02:00
042b160b81
global: pep8 (E222)
2015-04-13 16:58:04 +02:00
01ba965d0c
global: pep8 (E401)
2015-04-13 16:56:25 +02:00
796119fcaf
global: pep8 (E203)
2015-04-13 16:53:07 +02:00
ca7019fa0d
global: pep8 (E231)
2015-04-13 16:51:00 +02:00
9ad90b531e
global: pep8 (E201)
2015-04-13 16:48:51 +02:00
f68423f423
global: pep8 (E302)
2015-04-13 16:47:22 +02:00
d9e09707ae
global: pep8 (replace tabs with spaces)
2015-04-13 16:19:55 +02:00
2040727179
litesata: more pep8 (when convenient), should be almost OK
2015-04-13 16:09:04 +02:00
1f19e6ae92
litesata: pep8 (E265)
2015-04-13 15:58:58 +02:00
c8bcbfb855
litesata: pep8 (E261, E271)
2015-04-13 15:51:17 +02:00
2e5501933a
litesata: pep8 (W292)
2015-04-13 15:44:52 +02:00
ea67080462
litesata: pep8 (E225)
2015-04-13 15:44:04 +02:00
a9b42161c0
litesata: pep8 (E222)
2015-04-13 15:29:34 +02:00
77cdb953ad
litesata: pep8 (E401)
2015-04-13 15:27:36 +02:00
8f7751e412
litesata: pep8 (E203)
2015-04-13 15:25:40 +02:00
61fa72b655
litesata: pep8 (E231)
2015-04-13 15:19:34 +02:00
d0c5bd377a
litesata: pep8 (E302)
2015-04-13 15:12:39 +02:00
808e1fe866
litesata: pep8 (replace tabs with spaces)
2015-04-13 14:59:00 +02:00
312f302d36
litescope/examples_designs: add build directory
2015-04-13 14:53:17 +02:00
1e1f7ce30e
liteusb: more pep8 (when convenient), should be almost OK
2015-04-13 14:47:44 +02:00
f10e873063
liteusb: pep8 (E265)
2015-04-13 14:37:39 +02:00
5343537fc2
liteusb: pep8 (E225)
2015-04-13 14:34:36 +02:00
39df1ff636
liteusb: pep8 (E222)
2015-04-13 14:32:51 +02:00
9e3d3e7930
liteusb: pep8 (E231)
2015-04-13 14:30:48 +02:00
ce0e818d66
liteusb: pep8 (E201)
2015-04-13 14:29:44 +02:00
4974fd6bc9
liteusb: pep8 (E302)
2015-04-13 14:27:31 +02:00
cb473ddb6e
liteusb: pep8 (replace tabs with spaces)
2015-04-13 14:09:58 +02:00
40abd66d69
litescope: more pep8 (when convenient), should be almost OK
2015-04-13 13:56:24 +02:00
4cdb0ddf3a
litescope: pep8 (E265)
2015-04-13 13:46:06 +02:00
8f9bd24f6f
litescope: pep8 (E261, E271)
2015-04-13 13:40:30 +02:00
eb58f45b31
litescope: pep8 (W292)
2015-04-13 13:38:35 +02:00
f16623d548
litescope: pep8 (E225)
2015-04-13 13:37:46 +02:00
7e37d7b6d0
litescope: pep8 (E222)
2015-04-13 13:29:41 +02:00
651e228e22
litescope: pep8 (E401)
2015-04-13 13:28:47 +02:00
49dcf8d831
litescope: pep8 (E203)
2015-04-13 13:25:27 +02:00
51ca259bdb
litescope: pep8 (E231)
2015-04-13 13:23:48 +02:00
67b4da8ecf
litescope: pep8 (E201)
2015-04-13 13:20:13 +02:00
13e4d7c525
litescope: pep8 (E302)
2015-04-13 13:18:21 +02:00
1328328540
litescope: pep8 (replace tabs with spaces)
2015-04-13 13:09:44 +02:00
2bd38f44a3
liteeth: more pep8 (when convenient), should be almost OK
2015-04-13 13:02:04 +02:00
154d3d3b04
liteeth: pep8 (E265)
2015-04-13 11:27:01 +02:00
45dc4920ec
liteeth: pep8 (E261, E271)
2015-04-13 11:07:50 +02:00
021a5ae8a0
liteeth: pep8 (W292)
2015-04-13 10:58:45 +02:00
a84f12618b
liteeth: pep8 (E225)
2015-04-13 10:56:18 +02:00
66ce40d880
liteeth: pep8 (E222)
2015-04-13 10:48:59 +02:00
ff2d7f9adc
liteeth: pep8 (E401)
2015-04-13 10:45:09 +02:00
726fd3ab42
liteeth: pep8 (E203)
2015-04-13 10:39:46 +02:00
8dc817dd70
liteeth: pep8 (E231)
2015-04-13 10:31:18 +02:00
9c527742cb
liteeth: pep8 (E201)
2015-04-13 10:23:33 +02:00
5720638d85
liteeth: pep8 (E302)
2015-04-13 10:20:02 +02:00
cd43eaffc2
liteeth: pep8 (replace tabs with spaces)
2015-04-13 09:53:43 +02:00
afa9b889ae
liteeth/phy/gmii: fix clock generation for mii mode (clock_pads.tx is an input)
2015-04-12 22:15:45 +02:00
8e639160e3
liteeth/phy/gmii_mii: add pads registers in RX
2015-04-12 20:43:01 +02:00
0c27708b0a
liteeth/phy/gmii_mii: avoid doubling pads register on TX
2015-04-12 20:42:12 +02:00
bc81d9d639
liteeth/phy/__init__.py: add more comments
2015-04-12 18:56:46 +02:00
515398634f
liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode
2015-04-12 18:42:52 +02:00
857bee8a00
liteeth/phy: add GMII/MII phy
...
for now swicth is manual, we will need a clk counter to allow software or logic to automatically switch between GMII and MII
2015-04-12 17:25:55 +02:00
cfac3d9f5c
liteeth/phy/mii: simplify LiteEthPHYMIIRX using Converter
2015-04-12 16:03:21 +02:00
ddae41f2e4
liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter
2015-04-12 15:34:56 +02:00
8c722db54e
liteeth/phy/mii: assign tx_er only if exists (as it's done on GMII)
2015-04-12 14:43:35 +02:00
4329e3e1b9
liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705)
2015-04-12 14:28:17 +02:00
93ed3212f7
timer: revert prescaler (we will in fact use a software prescaler for uIP)
2015-04-10 18:57:06 +02:00
80ef7291c1
timer: add prescaler
2015-04-10 13:58:44 +02:00
d6c19858fa
s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE
2015-04-10 16:12:29 +08:00
603a4ef51e
liteeth: adapt to new ModuleTransformer
2015-04-10 11:42:25 +08:00
ea613cd8ee
litesata: update build core target generation
2015-04-09 00:00:25 +02:00
03aa972bb6
lite*: finish ModuleTransformer adaptations (need to be tested on board)
2015-04-08 23:27:22 +02:00
3a2b677f85
soc,cpuif: support user defined constants
2015-04-09 00:34:36 +08:00
176b9240a9
soc: use new ModuleTransformer API
2015-04-06 23:52:34 +08:00
66f8dcbfaf
lite*: adapt to new ModuleTransformer semantics
...
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
2015-04-04 19:17:24 +08:00
2583e975f0
soc/cpuif: fix CSR base generation for memories (name is already fullname)
2015-04-03 13:57:37 +02:00
c9c11e7aa8
soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions
2015-04-03 12:45:32 +02:00
85b3cced22
use str.format
2015-04-03 17:43:46 +08:00
0db6e1d624
soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube)
2015-04-03 11:14:28 +02:00
b437dc3185
remove use of _r prefix on CSRs
2015-04-02 12:18:43 +02:00
696819cc7f
move gpio from cpu.peripherals to com
2015-04-02 17:17:33 +08:00
382ed013af
minor cleanups
2015-04-02 14:40:29 +08:00
bbdbf87599
Merge branch 'master' of github.com:m-labs/misoc
2015-04-02 10:14:24 +08:00
60124be293
adapt LiteSATA to new SoC
2015-04-01 22:52:19 +02:00
dcdf5df4de
adapt LiteEth to new SoC
2015-04-01 22:50:29 +02:00
f65c0a3c95
adapt LiteScope to new SoC
2015-04-01 22:46:24 +02:00
2d23ab7a85
soc/sdram: fix do_finalize
2015-04-01 22:38:04 +02:00
2900429e65
soc: use set
2015-04-02 00:14:56 +08:00
369086a178
soc: simplify integrated memory parameters
2015-04-02 00:09:38 +08:00
273242b399
soc/sdram: minor cleanup
2015-04-01 23:41:55 +08:00
6e2a662dd7
litesata: adapt to new SoC API
2015-04-01 17:37:53 +08:00
9599eb6fae
soc: remove cpu_boot_file argument
2015-04-01 17:32:45 +08:00
fb86445d14
soc: remove cpu_or_bridge and with_cpu arguments
2015-04-01 17:29:51 +08:00
a148af97ba
soc: retrieve csr and memory regions using methods
2015-04-01 16:49:32 +08:00
8b19a11cd7
soc: use add_wb_master function
2015-04-01 15:56:54 +08:00
2a1112b912
soc: simplify/fix csr busword
2015-04-01 15:48:56 +08:00
04f29e97e2
soc: remove unnecessary imports
2015-04-01 15:15:09 +08:00
5113301130
soc: improve memory region conflict check
2015-04-01 15:14:02 +08:00
980791e2b8
soc: remove ns function
2015-04-01 14:33:12 +08:00
b313772a0c
sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
2015-03-29 12:34:40 +02:00
be20fbabe4
soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)
2015-03-28 23:35:44 +01:00
0649ded5fd
soc: simplify main_ram_size computation and share it between LASMIcon and Minicon
2015-03-28 23:10:33 +01:00
a8d91c0c1d
sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
2015-03-28 16:35:15 +01:00
75ee8a5db9
sdram/phy/simphy: OK with DDR3
2015-03-28 01:59:55 +01:00
51ce7cad6f
sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
2015-03-28 01:18:35 +01:00
a95b3f8f13
sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
2015-03-28 01:17:50 +01:00
7fe748e1b0
sdram/module: clean up tREFI. (use 64ms/8k or 4k)
2015-03-28 01:09:21 +01:00
9137b91e9e
sdram: remove nbits from modules and databits from GeomSettings
2015-03-26 23:27:37 +01:00
9a9af17aca
sdram/phy/simphy: remove use of iter
2015-03-26 23:02:23 +01:00
e6de4b1bf9
sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
2015-03-26 22:28:32 +01:00
257706517e
software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
2015-03-26 00:01:42 +01:00
ff11cb97a9
sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True
2015-03-25 17:22:26 +01:00
ba8b24df57
sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
2015-03-25 16:57:38 +01:00
7ea9e2ba89
sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
2015-03-25 16:56:29 +01:00
20207c9c32
liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
2015-03-22 11:11:37 +01:00
c77562f44b
liteusb: make oe_n optional on ft2232h phy
2015-03-22 10:56:56 +01:00
ed5746a1fe
liteusb: fix imports
2015-03-22 10:56:29 +01:00
Florent Kermarrec
Sebastien Bourdeauducq
Robert Jordens