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710 commits

Author SHA1 Message Date
Florent Kermarrec
9051cf97e4 soc_zynq: fix typo 2019-09-05 15:55:18 +02:00
Florent Kermarrec
67a09aef05 soc/interconnect/stream: add Monitor module 
Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
 2019-09-05 11:54:14 +02:00
Tim 'mithro' Ansell
2a41f0d2a4 Use SMALL_CRC to enable smaller CRC versions. 
@xobs created a smaller code size version of the CRC functions. Enable
these if someone uses the `SMALL_CRC` define.
 2019-09-02 14:48:30 -07:00
Tim 'mithro' Ansell
083337441a Remove extra whitespace. 2019-09-02 14:47:20 -07:00
Sean Cross
c0e723868e libbase: crc16: commit smaller version of crc16 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:44:18 -07:00
Sean Cross
a59d0efca0 libbase: crc32: add smaller version 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:44:18 -07:00
Florent Kermarrec
a2938a7ae7 soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" 2019-08-31 18:34:08 +02:00
enjoy-digital
19d3acfc71
Merge pull request #251 from micro-FPGA/master 
atlantic JTAG UART working module
 2019-08-31 18:33:27 +02:00
Antti Lukats
fb00ee85a2 Create atlantic.py 
atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
 2019-08-30 09:35:10 +02:00
Florent Kermarrec
41fe7cae0b core/spi: add minimal SPISlave 2019-08-29 09:46:20 +02:00
Florent Kermarrec
c179741cf3 software/bios: switch to standard CRLF 
Avoid setting terminal to "implicit CR in every LF" mode.
 2019-08-27 09:45:44 +02:00
Florent Kermarrec
ffebd2076c bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) 2019-08-26 17:15:01 +02:00
Gabriel L. Somlo
6d844a038a software: use native toolchain for same host, target architectures 
LiteX rightfully assumes that most often the target software must
be cross-compiled from an x86 host platform. However, LiteX can be
also built on a 'linux-riscv64' platform (e.g. Fedora's riscv64
port), where the software for riscv64 targets should be compiled
using the native toolchain.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-08-23 09:04:55 -04:00
Florent Kermarrec
4990bf33c0 soc/core: simplify/cleanup HyperRAM core 
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
 2019-08-16 14:04:58 +02:00
Antti Lukats
d1502d4195 soc/cores: add initial simple hyperram core 2019-08-16 09:48:17 +02:00
Florent Kermarrec
2899928aba cpu_interface: add json csr map export, simplify csv csr map export using json 2019-08-15 09:27:33 +02:00
Florent Kermarrec
9d4b7cd515 bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) 2019-08-14 19:09:58 +02:00
chmousset
db4c609a33 [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat 2019-08-14 11:30:39 +02:00
Florent Kermarrec
6d5fddc160 cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) 2019-08-14 07:35:45 +02:00
Daniel Kucera
a5eaf172c5
more understandable error when missing a memory 2019-08-13 10:14:16 +02:00
Florent Kermarrec
31bfb54667 software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys 2019-08-09 13:26:31 +02:00
Florent Kermarrec
e670cb9176 cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus 2019-08-09 12:33:10 +02:00
Florent Kermarrec
6d94c07d70 software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle 2019-08-09 10:33:42 +02:00
Florent Kermarrec
0c287b11ba cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap 2019-08-09 09:27:32 +02:00
Florent Kermarrec
82cd557c24 software/bios: add Ethernet PHY MDIO read/write/dump commands 2019-08-09 09:26:41 +02:00
Florent Kermarrec
d3d0a6231c cores/clock: juse use 1e9/freq instead of period_ns 2019-08-07 08:29:20 +02:00
Florent Kermarrec
a881817fb3 cores/clock/s6pll: add phase support 2019-08-07 08:18:54 +02:00
Florent Kermarrec
6b7ca0cff7 cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq 2019-08-07 08:17:44 +02:00
Florent Kermarrec
e052d7f645 soc/integration/builder: -x 2019-08-06 07:56:45 +02:00
Florent Kermarrec
236070fdcf cores: -x on spi.py 2019-08-05 10:36:43 +02:00
Florent Kermarrec
a9fe2788a2 wishbone/SRAM: make read_only emited verilog code compatible with all tools 
Quartus was not able to implement ROM correctly, see #228
 2019-08-05 09:08:56 +02:00
Florent Kermarrec
ce5c58592b soc/cores/uart: add FT245 FIFO mode support (sync & async) 2019-08-04 12:22:35 +02:00
Florent Kermarrec
92d93ad221 cores/pwm: remove default CSR reset values. 2019-07-29 08:38:28 +02:00
Florent Kermarrec
25ca0a8b71 soc: generate git header and show migen/litex git sha1 in bios 2019-07-27 20:27:53 +02:00
Mateusz Holenko
932475a29b cpu/vexriscv: bump submodule 2019-07-25 08:43:35 +02:00
Florent Kermarrec
bc7ab637dd bios/sdram: fix compilation warning 2019-07-25 07:46:14 +02:00
Florent Kermarrec
1cfb36e1e4 soc_core: round memory regions size/length to next power of 2 (if not already a power of 2) 2019-07-23 20:35:28 +02:00
Mateusz Holenko
3e89c56468 cpu/vexriscv: bump submodule 2019-07-23 11:49:18 +02:00
Florent Kermarrec
e673fce445 bios/boot: fix default EMULATOR_RAM_BASE 2019-07-23 10:28:19 +02:00
Florent Kermarrec
0acacbaa82 cores/clock: cleanup 2019-07-23 09:54:30 +02:00
Florent Kermarrec
edf8aa8cfd cores/clock: add initial iCE40 support 2019-07-23 09:27:20 +02:00
Florent Kermarrec
6d54335839 cores/spi_flash/add_clk_primitive: return if clk primitive is not needed 2019-07-22 21:55:07 +02:00
Florent Kermarrec
462d12bacc bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET 2019-07-22 21:54:24 +02:00
Florent Kermarrec
fc12961e7e soc_core: fix cpu_variant definition 2019-07-22 12:46:39 +02:00
Florent Kermarrec
af61688d1d bios/boot: fix booting rework 
- keep emulator.bin in a specific ram (for now)
- print message when falling back to boot.bin
- print destination on tftp download (to ease debug)
 2019-07-22 11:47:41 +02:00
Florent Kermarrec
4b686dbdb2 soc_core: fix cpu_variant config (we don't want the extension) 2019-07-22 11:44:32 +02:00
enjoy-digital
7d9cf1d2bd
Merge pull request #216 from antmicro/booting_vexriscv_linux 
Rework booting Linux on VexRiscv
 2019-07-22 11:44:20 +02:00
Florent Kermarrec
95cfd0b9e5 cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) 2019-07-22 10:28:03 +02:00
Florent Kermarrec
41eb21b343 soc_core: optimize mem_decoder 
Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.

The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.
 2019-07-22 08:53:54 +02:00
Florent Kermarrec
0eff65bb31 cores/up5ksram: optimize bus.adr decoding 2019-07-22 07:55:47 +02:00
Florent Kermarrec
bb99c4685a cores/up5kspram: simplify and add support for all width/depth configurations 2019-07-21 19:28:31 +02:00
Florent Kermarrec
eaf84b8581 cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional 2019-07-20 12:57:32 +02:00
Florent Kermarrec
ea619e3afe cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
Florent Kermarrec
ec411a6ac1 soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs 2019-07-20 12:52:44 +02:00
Mateusz Holenko
8335f13fb1 bios/boot: rework netboot/flashboot for VexRiscv in linux variant 
Get rid of NETBOOT_LINUX_VEXRISCV/FLASHBOOT_LINUX_VEXRISCV defines
and use information about CPU_TYPE and CPU_VARIANT instead.

Use common kernel/rootfs/device tree/emulator images layout
when booting over network and from flash.
 2019-07-15 16:02:58 +02:00
Mateusz Holenko
a19bdd0e6a soc_core: generate extra string-based config defines 
C preprocessor does not allow to compare strings, so
the current defines are not usable at the compile time.
This adds new defines that can be ifdefed.
 2019-07-15 15:58:54 +02:00
Mateusz Holenko
005c07769b soc_core: include information about cpu variant in csv and headers 2019-07-15 15:58:54 +02:00
Francis Lam
c6c743915a soc: cores: fix name of EHXPLLL output clock in ECP5PLL 2019-07-14 12:27:28 -07:00
Florent Kermarrec
d3aaaf5e6c cores/spi: fix/simplify loopback 2019-07-13 13:10:27 +02:00
Florent Kermarrec
769d15d433 cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test 
Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
 2019-07-13 12:55:19 +02:00
Florent Kermarrec
ee8fec10ff soc/cores: add ECC (Error Correcting Code) 
Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
 2019-07-13 11:44:29 +02:00
enjoy-digital
95796c5b29
Merge pull request #218 from railnova/zynq 
[fix] Slave interface HP0 clk name
 2019-07-12 18:00:03 +02:00
chmousset
dcf55ad4f3 [fix] Slave interface HP0 clk name 2019-07-12 16:37:23 +02:00
Ilia Sergachev
dacec6aa86 spi: change CSR to CSRStorage 2019-07-12 14:12:51 +02:00
Florent Kermarrec
be280bed5e soc_zynq: use zynq fabric reset as sys reset 2019-07-12 09:52:50 +02:00
Florent Kermarrec
220f43753b soc_zynq: add missing axi hp0 clock 2019-07-10 16:51:08 +02:00
Florent Kermarrec
9c8c037108 soc_zynq: move axi gp0 clock connection to add_gp0 method 2019-07-10 16:50:06 +02:00
Florent Kermarrec
b0192e5f8b soc_core: use fixed 16MB CSR address space 
Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
 2019-07-10 10:39:00 +02:00
Florent Kermarrec
68a503174c soc_sdram: limit main_ram to 512MB for now 
Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.
 2019-07-09 12:14:50 +02:00
Florent Kermarrec
21a5aaa4a6 soc_core: declare csr address size when registering csr, fixes #212 2019-07-08 22:58:07 +02:00
Florent Kermarrec
41b6fbde42 soc_cores: fix typos 2019-07-08 22:56:14 +02:00
Gabriel L. Somlo
e42f33ede1 soc_core: additional csr_alignment follow-up fixes 
- Update a few additional places to use DFII_ADDR_SHIFT instead of
  a hard-coded 4, which assumed 32-bit alignment.

- Force 64-bit alignment Rocket -- the only supported configuration!

This is a fixup for commit f4770219, tested on Rocket and 64bit Linux.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-07-08 10:15:14 -04:00
Florent Kermarrec
f4770219fa soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs 2019-07-08 10:20:51 +02:00
Florent Kermarrec
927b7c13a2 soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) 2019-07-08 08:57:05 +02:00
Florent Kermarrec
96f45bbd87 software/libbase/id: update code (length is now fixed to 256) 2019-07-06 17:18:34 +02:00
Florent Kermarrec
282ae96354 cores: add simple PWM (Pulse Width Modulation) module 2019-07-05 19:39:08 +02:00
Florent Kermarrec
77e7f9b3c1 core/spi: make cs_n optional (sometimes managed externally) 2019-07-05 19:18:52 +02:00
Florent Kermarrec
e726ad80ac cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) 2019-07-05 19:01:55 +02:00
Florent Kermarrec
4c18c991bc cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
Florent Kermarrec
6b82f23ce1 cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. 2019-07-05 15:50:58 +02:00
Florent Kermarrec
ada70e8c52 soc/cores/spi: remove too complicated and does not seem reliable in all cases. 2019-07-05 14:38:09 +02:00
Florent Kermarrec
7cd5c0f39b cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
Florent Kermarrec
d29b841997 cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) 2019-07-05 13:13:31 +02:00
Florent Kermarrec
3f6bd266d9 cores/gpio: remove Blinker 2019-07-05 13:09:21 +02:00
Florent Kermarrec
4ee9c53f18 csr: add assert to ensure CSR size < busword (thanks tweakoz) 2019-07-03 13:44:15 +02:00
Florent Kermarrec
0116b2b708 soc_core: update default RocketChip mem_map 2019-06-28 23:40:01 +02:00
Florent Kermarrec
9d170b0944 soc_core: rearrange default mem_map 2019-06-28 23:27:23 +02:00
Florent Kermarrec
05b667bb95 bios/main: fix #ifdefs for fw command 2019-06-28 22:42:02 +02:00
Florent Kermarrec
37687579e0 libnet/tftp: fix compilation warning 2019-06-28 22:32:45 +02:00
Florent Kermarrec
9f3c8a9b8a bios/main: fix spiflash compilation warnings 2019-06-28 22:18:24 +02:00
Florent Kermarrec
2da59b29e2 soc_sdram: allow main_ram_size > 256MB (limitation no longer exists) 2019-06-28 22:10:25 +02:00
Florent Kermarrec
7618b84533 soc_core: use new way to add wisbone slave (now prefered) 2019-06-28 22:10:15 +02:00
Florent Kermarrec
740629ba53 soc_core: remove 256MB mem_map limitation 
mem_map was limited to 8 256MB for simplicity but has become an issue for
complex SoCs. Default mem_map size is still 256MB (retro-compatibility) but
size can now be specified.
 2019-06-28 22:10:02 +02:00
Florent Kermarrec
b65968c329 soc/core: remove #!/usr/bin/env python3 2019-06-28 21:37:52 +02:00
Gabriel L. Somlo
5a42dbf333 BIOS: TFTP: ASCII spinner progress indicator (cosmetic) 2019-06-27 10:31:33 -04:00
enjoy-digital
d5177d72ac
Merge pull request #204 from antmicro/write_to_flash 
fw (flash write) command
 2019-06-25 19:10:17 +02:00
Florent Kermarrec
cef2369015 core/spi_flash: re-integrate bitbang write support 2019-06-25 19:09:30 +02:00
Mateusz Holenko
2ee194b259 bios: add fw (flash write) command 2019-06-25 16:58:12 +02:00
Florent Kermarrec
ecf999b8c7 soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB 
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
 2019-06-24 10:58:36 +02:00
Florent Kermarrec
8f6e66ca52 make sure #!/usr/bin/env python3 is before copyright header 2019-06-24 07:29:24 +02:00