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Author SHA1 Message Date
Florent Kermarrec
bb99c4685a cores/up5kspram: simplify and add support for all width/depth configurations 2019-07-21 19:28:31 +02:00
Florent Kermarrec
eaf84b8581 cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional 2019-07-20 12:57:32 +02:00
Florent Kermarrec
ea619e3afe cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
Florent Kermarrec
ec411a6ac1 soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs 2019-07-20 12:52:44 +02:00
Mateusz Holenko
8335f13fb1 bios/boot: rework netboot/flashboot for VexRiscv in linux variant 
Get rid of NETBOOT_LINUX_VEXRISCV/FLASHBOOT_LINUX_VEXRISCV defines
and use information about CPU_TYPE and CPU_VARIANT instead.

Use common kernel/rootfs/device tree/emulator images layout
when booting over network and from flash.
 2019-07-15 16:02:58 +02:00
Mateusz Holenko
a19bdd0e6a soc_core: generate extra string-based config defines 
C preprocessor does not allow to compare strings, so
the current defines are not usable at the compile time.
This adds new defines that can be ifdefed.
 2019-07-15 15:58:54 +02:00
Mateusz Holenko
005c07769b soc_core: include information about cpu variant in csv and headers 2019-07-15 15:58:54 +02:00
Francis Lam
c6c743915a soc: cores: fix name of EHXPLLL output clock in ECP5PLL 2019-07-14 12:27:28 -07:00
Florent Kermarrec
d3aaaf5e6c cores/spi: fix/simplify loopback 2019-07-13 13:10:27 +02:00
Florent Kermarrec
769d15d433 cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test 
Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
 2019-07-13 12:55:19 +02:00
Florent Kermarrec
ee8fec10ff soc/cores: add ECC (Error Correcting Code) 
Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
 2019-07-13 11:44:29 +02:00
enjoy-digital
95796c5b29
Merge pull request #218 from railnova/zynq 
[fix] Slave interface HP0 clk name
 2019-07-12 18:00:03 +02:00
chmousset
dcf55ad4f3 [fix] Slave interface HP0 clk name 2019-07-12 16:37:23 +02:00
Ilia Sergachev
dacec6aa86 spi: change CSR to CSRStorage 2019-07-12 14:12:51 +02:00
Florent Kermarrec
be280bed5e soc_zynq: use zynq fabric reset as sys reset 2019-07-12 09:52:50 +02:00
Florent Kermarrec
220f43753b soc_zynq: add missing axi hp0 clock 2019-07-10 16:51:08 +02:00
Florent Kermarrec
9c8c037108 soc_zynq: move axi gp0 clock connection to add_gp0 method 2019-07-10 16:50:06 +02:00
Florent Kermarrec
b0192e5f8b soc_core: use fixed 16MB CSR address space 
Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
 2019-07-10 10:39:00 +02:00
Florent Kermarrec
68a503174c soc_sdram: limit main_ram to 512MB for now 
Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.
 2019-07-09 12:14:50 +02:00
Florent Kermarrec
21a5aaa4a6 soc_core: declare csr address size when registering csr, fixes #212 2019-07-08 22:58:07 +02:00
Florent Kermarrec
41b6fbde42 soc_cores: fix typos 2019-07-08 22:56:14 +02:00
Gabriel L. Somlo
e42f33ede1 soc_core: additional csr_alignment follow-up fixes 
- Update a few additional places to use DFII_ADDR_SHIFT instead of
  a hard-coded 4, which assumed 32-bit alignment.

- Force 64-bit alignment Rocket -- the only supported configuration!

This is a fixup for commit f4770219, tested on Rocket and 64bit Linux.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-07-08 10:15:14 -04:00
Florent Kermarrec
f4770219fa soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs 2019-07-08 10:20:51 +02:00
Florent Kermarrec
927b7c13a2 soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) 2019-07-08 08:57:05 +02:00
Florent Kermarrec
96f45bbd87 software/libbase/id: update code (length is now fixed to 256) 2019-07-06 17:18:34 +02:00
Florent Kermarrec
282ae96354 cores: add simple PWM (Pulse Width Modulation) module 2019-07-05 19:39:08 +02:00
Florent Kermarrec
77e7f9b3c1 core/spi: make cs_n optional (sometimes managed externally) 2019-07-05 19:18:52 +02:00
Florent Kermarrec
e726ad80ac cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) 2019-07-05 19:01:55 +02:00
Florent Kermarrec
4c18c991bc cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
Florent Kermarrec
6b82f23ce1 cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. 2019-07-05 15:50:58 +02:00
Florent Kermarrec
ada70e8c52 soc/cores/spi: remove too complicated and does not seem reliable in all cases. 2019-07-05 14:38:09 +02:00
Florent Kermarrec
7cd5c0f39b cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
Florent Kermarrec
d29b841997 cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) 2019-07-05 13:13:31 +02:00
Florent Kermarrec
3f6bd266d9 cores/gpio: remove Blinker 2019-07-05 13:09:21 +02:00
Florent Kermarrec
4ee9c53f18 csr: add assert to ensure CSR size < busword (thanks tweakoz) 2019-07-03 13:44:15 +02:00
Florent Kermarrec
0116b2b708 soc_core: update default RocketChip mem_map 2019-06-28 23:40:01 +02:00
Florent Kermarrec
9d170b0944 soc_core: rearrange default mem_map 2019-06-28 23:27:23 +02:00
Florent Kermarrec
05b667bb95 bios/main: fix #ifdefs for fw command 2019-06-28 22:42:02 +02:00
Florent Kermarrec
37687579e0 libnet/tftp: fix compilation warning 2019-06-28 22:32:45 +02:00
Florent Kermarrec
9f3c8a9b8a bios/main: fix spiflash compilation warnings 2019-06-28 22:18:24 +02:00
Florent Kermarrec
2da59b29e2 soc_sdram: allow main_ram_size > 256MB (limitation no longer exists) 2019-06-28 22:10:25 +02:00
Florent Kermarrec
7618b84533 soc_core: use new way to add wisbone slave (now prefered) 2019-06-28 22:10:15 +02:00
Florent Kermarrec
740629ba53 soc_core: remove 256MB mem_map limitation 
mem_map was limited to 8 256MB for simplicity but has become an issue for
complex SoCs. Default mem_map size is still 256MB (retro-compatibility) but
size can now be specified.
 2019-06-28 22:10:02 +02:00
Florent Kermarrec
b65968c329 soc/core: remove #!/usr/bin/env python3 2019-06-28 21:37:52 +02:00
Gabriel L. Somlo
5a42dbf333 BIOS: TFTP: ASCII spinner progress indicator (cosmetic) 2019-06-27 10:31:33 -04:00
enjoy-digital
d5177d72ac
Merge pull request #204 from antmicro/write_to_flash 
fw (flash write) command
 2019-06-25 19:10:17 +02:00
Florent Kermarrec
cef2369015 core/spi_flash: re-integrate bitbang write support 2019-06-25 19:09:30 +02:00
Mateusz Holenko
2ee194b259 bios: add fw (flash write) command 2019-06-25 16:58:12 +02:00
Florent Kermarrec
ecf999b8c7 soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB 
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
 2019-06-24 10:58:36 +02:00
Florent Kermarrec
8f6e66ca52 make sure #!/usr/bin/env python3 is before copyright header 2019-06-24 07:29:24 +02:00
Florent Kermarrec
daa4307d9e add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
Florent Kermarrec
361f9d0dff bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) 2019-06-22 10:55:15 +02:00
Tim 'mithro' Ansell
d8ac936206 Convert top level comment to a docstring. 2019-06-21 12:03:30 -07:00
William D. Jones
7656f54d0a soc: cores: add up5kspram module 
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-20 11:12:46 -07:00
Florent Kermarrec
73dbffe8f2 cores/frequency_meter: allow passing clk to be measured as a parameter 2019-06-20 09:03:30 +02:00
Gabriel L. Somlo
f75863fc31 cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants 2019-06-18 06:46:24 -04:00
Florent Kermarrec
c0df9e0823 cpu/rocket: update submodule 2019-06-18 09:44:13 +02:00
Florent Kermarrec
87118d509c integration/soc_core: move cpu_variant checks/formating to cpu 2019-06-17 09:55:27 +02:00
Florent Kermarrec
f6b67a6dae cpu/vexriscv: add "linux+no-dsp" variant 2019-06-17 09:54:17 +02:00
Florent Kermarrec
95b1b454f4 cpu/vexriscv: update 2019-06-17 09:24:57 +02:00
Ambroz Bizjak
ca70ea91e4
bios: Fix build when ethphy is present but ethmac is not. 
While testing my Ethernet DMA, I renamed the `ethmac` module to `ethmac_dma` so that it wouldn't be used from the BIOS, but I got an undefined reference to `eth_init` because `bios.c` checks different CSR defines than the code that defines `eth_init`.
 2019-06-13 01:02:22 +02:00
Florent Kermarrec
243d7c7696 soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker 
Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.
 2019-06-10 16:05:36 +02:00
Florent Kermarrec
1c34b4a015 cpu/vexriscv: update submodule 2019-06-10 12:57:21 +02:00
Florent Kermarrec
850b311d04 cpu/vexriscv: update submodule 2019-06-07 18:36:46 +02:00
Florent Kermarrec
c64129dc69 soc/integration/soc_core: list rocket as supported CPU 2019-06-07 11:14:36 +02:00
Florent Kermarrec
ca4e7811e9 software/bios: change prompt to "litex" in green. 2019-06-07 11:13:36 +02:00
Florent Kermarrec
8d0f008a3b integration/soc_core: improve readibility (add separators/comments) 2019-06-05 23:43:16 +02:00
Mateusz Holenko
93b61a65bf integration/builder: generate flash_boot address to csv 2019-06-05 17:37:23 +02:00
Mateusz Holenko
d0b019b1f0 integration/builder: generate shadow_base address to mem.h and csv 2019-06-05 17:37:09 +02:00
Gabriel L. Somlo
f88b85a31c software/libbase: memcpy: simple, arch-width agnostic implementation 
Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.

Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-04 14:48:51 -04:00
Tim Ansell
42e9d09755
Merge pull request #192 from sutajiokousagi/pr_c99_types 
fix signed char type to be explicitly signed
 2019-06-02 16:54:20 -07:00
bunnie
ab0b2cac2e fix signed char type to be explicitly signed 2019-06-03 06:01:13 +00:00
bunnie
200d413def update stdint.h to include c99 types 
needed for some third party libraries to compile
 2019-06-02 22:27:12 +00:00
Ilia Sergachev
db890736ea fix csr_name in add_csr() 2019-06-02 20:56:02 +02:00
Ilia Sergachev
40cbe3a952 fix interrupt_name 2019-06-02 20:52:31 +02:00
Gabriel L. Somlo
273a3ea15d soc/integration/cpu_interface: improve code legibility 
Factor out code appearing in both branches of an if/else.
 2019-05-29 10:07:43 -04:00
Florent Kermarrec
08a811b1a5 soc/interconnect/gearbox: add msb_first/lsb_first order 2019-05-29 10:25:25 +02:00
Florent Kermarrec
5109511259 soc/interconnect/axi: add round/robin arbitration between writes/reads 2019-05-25 10:02:31 +02:00
Florent Kermarrec
961101d809 bios/irc: remove compilation workaround 2019-05-25 09:24:48 +02:00
Florent Kermarrec
712977a0cf software/bios/isr.c: workaround compilation issue (need to be fixed) 2019-05-24 10:18:50 +02:00
Florent Kermarrec
28ba8b3201 soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) 2019-05-24 10:18:32 +02:00
Gabriel L. Somlo
019fd94005 fixup: generated-verilog submodule for experimental Rocket support 
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
 2019-05-23 18:22:37 -04:00
Gabriel L. Somlo
1a530cf27d soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) 
Simulate a Rocket-based 64-bit LiteX SoC with the following command:

  litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket

NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-05-23 15:59:51 -04:00
Florent Kermarrec
10670e22ac soc/cores/minerva: update to latest 2019-05-17 22:21:57 +02:00
Florent Kermarrec
0a8699f1e6 Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-05-16 15:15:30 +02:00
Florent Kermarrec
526ba1b165 soc_core: remove csr_expose and add add_csr_master method 
This could be useful in specific case were we don't have a wishbone master
but just want to have a csr bus and allow the user to define it.

/!\ Since there is no arbitration on between the CSR masters, use this with
precaution /!\
 2019-05-16 15:14:55 +02:00
Florent Kermarrec
1ea22d49b7 software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva 2019-05-15 22:40:32 +02:00
Florent Kermarrec
f25707012f software/bios/boot: remove specific linux commands (not needed with device tree) 2019-05-14 11:45:16 +02:00
Florent Kermarrec
eb6fa45833 cpu/vexriscv/core: update 2019-05-13 10:59:26 +02:00
Florent Kermarrec
0cad80e935 cpu/vexriscv: update submodule (new linux variant) 2019-05-13 10:59:03 +02:00
Florent Kermarrec
2f2b9b319f soc/cores: remove cordic 
Cordic is useful for DSP cores but not as a Soc building block.
 2019-05-11 09:36:53 +02:00
Florent Kermarrec
6e4ac1c493 LICENSE: clarify 2019-05-11 09:26:51 +02:00
Florent Kermarrec
67159349d6 soc/interconnect: remove axi_lite 
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has  proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
 2019-05-11 09:12:20 +02:00
Florent Kermarrec
a49d170a6d soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy 2019-05-10 15:46:22 +02:00
Florent Kermarrec
7445b9e2e0 soc/integration/soc_core: allow user to defined internal csr/interrupts 
For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.
 2019-05-10 11:05:34 +02:00
Florent Kermarrec
b6be534cd6 soc/integration/soc_core: rework csr assignation/reservation 
Similar refactor than on interrupts. Adds a add_csr method but still
retro-compatible with old way to declare CSRs.
 2019-05-09 23:32:22 +02:00
Florent Kermarrec
2abb3e809c Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-05-09 11:57:19 +02:00
Florent Kermarrec
47dc87584f integration/soc_core: rework interrupt assignation/reservation 
The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.

Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
 2019-05-09 11:54:22 +02:00
Mateusz Holenko
8caa38bc25 cpu: add reserved_interrupts property 2019-05-09 09:00:06 +02:00
Gabriel L. Somlo
c264a00964 soc/integration/cpu_interface: more arch-specific address size fixes 
When generating arch-specific include files (generated/[mem|csr].h)
ensure address literal defines are suffixed by 'L', denoting their
'unsigned long' type. This inhibits compiler warnings when values
computed based on these constants are cast to pointers.

Also ensure csr_[read|write][b|w|l]() function declarations have
'unsigned long' address arguments.

Finally, restore the correct (32-bit, (unsigned *)) expected
behavior of the MMPTR() macro, inadvertently converted to an
arch-specific sized access (unsigned long *) by commit 5c2b8685.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-05-08 16:03:36 -04:00
Florent Kermarrec
b7e3713388 bios/boot/ update linux memory mapping 2019-05-07 11:59:28 +02:00
David Shah
a048ba47c4 vexriscv: Fix some floating signals 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-04 17:27:21 +01:00
Florent Kermarrec
fcd518b5d0 bios/boot: add specific flash_boot for linux with vexriscv 2019-05-04 11:27:01 +02:00
Florent Kermarrec
1ba1ad9a00 bios/boot: rename MM_RAM to EMULATOR_RAM 2019-05-03 19:47:36 +02:00
Florent Kermarrec
fbb24720f0 soc/get_mem_data: add direct support for regions 
We now support passing filename (offset=0), json file and regions
 2019-05-03 13:24:06 +02:00
Florent Kermarrec
0714816f31 soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone 2019-05-03 11:59:06 +02:00
Florent Kermarrec
c6d0d23445 soc/interconnect/axi: add AXI Lite definition 2019-05-03 09:43:12 +02:00
Florent Kermarrec
9fab4752c4 soc/interconnect/axi: add comment on axi signas that are present but not used 2019-05-03 09:30:59 +02:00
Florent Kermarrec
5989076346 cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant 2019-05-03 09:30:26 +02:00
Florent Kermarrec
21bf10383d bios/boot: add liftoff banner just before booting 2019-05-02 18:26:35 +02:00
Florent Kermarrec
8f4685b3b1 bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config 2019-05-02 16:34:41 +02:00
Florent Kermarrec
6cf1ff091c soc/interconnect/axi: connect axi.ar/aw when selecting write or read 2019-05-02 09:58:55 +02:00
Florent Kermarrec
6affc56a09 soc/interconnect/axi: wishbone address shift is not always 2, make it generic 2019-05-02 09:35:07 +02:00
Florent Kermarrec
698bc88296 soc/interconnect/wishbone: allow setting adr_width (default to 30) 2019-05-02 09:34:30 +02:00
Florent Kermarrec
4dccb8a9eb soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent 2019-05-01 12:59:04 +02:00
Gabriel L. Somlo
5c2b8685fc software: use "unsigned long" for address values, also 8-byte alignment 
Enable future support for 64-bit CPU models.
 2019-04-29 15:03:38 -04:00
Florent Kermarrec
5c1d980540 soc/interconnect/axi: add burst support to AXI2Wishbone 2019-04-29 16:49:20 +02:00
Florent Kermarrec
6de2713524 soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize 2019-04-29 14:02:05 +02:00
Florent Kermarrec
305b8879de integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k) 
Keep or1k retro-compatibility for now but add a warning
 2019-04-29 10:14:30 +02:00
Florent Kermarrec
b40d1b73c4 cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) 2019-04-29 10:00:04 +02:00
Florent Kermarrec
dbb71af189 cpu: use property methods to return name, endianness, gcc triple/flags, linker output format 2019-04-29 09:58:51 +02:00
Florent Kermarrec
d828c3a596 cpu: integrate nmigen version of Minerva, add submodule 2019-04-28 23:40:33 +02:00
Kurt Kiefer
bf27869ad9 fix vexriscv build 2019-04-28 11:10:20 +02:00
enjoy-digital
2d5bae3def
Merge pull request #175 from mithro/cpu-docs 
Standardizing `cpu_variants` and adding lots of documentation
 2019-04-27 21:24:06 +02:00
Tim 'mithro' Ansell
5cbc5bc199 Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
Tim 'mithro' Ansell
71a837315a Work with no cpu_variant provided. 2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell
39c579baa2 Standardize the cpu_variant strings. 
Current valid `cpu_variant` values;
 * minimal  (alias: min)
 * lite     (alias: light, zephyr, nuttx)
 * standard (alias: std) - Default
 * full     (alias: everything)
 * linux

Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file
mirrored from the
[LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki).

Also support "extensions" which are added to the `cpu_variant` with a
`+`. Currently only the `debug` extension is supported. In future hope
to add `mmu` and `hmul` extensions.
 2019-04-26 17:44:30 -05:00
Florent Kermarrec
3a2e283613 .gitmodules: use our VexRiscv-verilog 2019-04-27 00:00:55 +02:00
Florent Kermarrec
78c09125be soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes 2019-04-25 23:43:10 +02:00
Florent Kermarrec
0175f86cb2 soc/integration/soc_core: fix get_mem_data for json files 2019-04-25 18:36:47 +02:00
Florent Kermarrec
4443b5075b soc/integration/soc_core: add integrated_sram_init 2019-04-25 17:30:03 +02:00
Florent Kermarrec
f27084c6c0 soc/integration/cpu_interface: fix banner in get_mem_header 2019-04-24 22:44:37 +02:00
Florent Kermarrec
e8f3c49127 software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding 2019-04-24 11:32:40 +02:00
Florent Kermarrec
44e0cdda9a software/libnet/microudp: speed-up ARP by changing timeout/tries 
First ARP request does not seem to be transmitted (the link is probably not
fully established). Reduce the timeout between tries and increase number of
tries.
 2019-04-24 09:55:41 +02:00
Florent Kermarrec
68f12495cf soc/integration: also add sha-1/date to generated software files 2019-04-23 13:17:54 +02:00
Florent Kermarrec
10cf0fdea3 cores/cpu/vexriscv: fix wrong revert 2019-04-23 11:13:29 +02:00
Florent Kermarrec
40342404f2 cores/clock: add divclk_divide_range on S6PLL/S6DCM 2019-04-23 06:43:48 +02:00
Florent Kermarrec
0d282f38f9 cores/clock: use common XilinxClocking class for all Xilinx clocking modules 2019-04-23 06:35:39 +02:00
Michael Betz
83699ea0a5 cores/clock: add initial Spartan6 PLL/DCM support 2019-04-23 06:23:00 +02:00
Florent Kermarrec
7d278854d5 global: switch to VexRiscv as the default CPU 
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
 2019-04-22 09:41:07 +02:00
Florent Kermarrec
9ee6c35b42 tools: move from litex.soc.tools to litex.tools and fix usb.core import 2019-04-20 10:44:53 +02:00
enjoy-digital
49fd93ae83
Merge pull request #165 from xobs/vexriscv-cpu-reset-address 
Vexriscv cpu reset address
 2019-04-19 19:16:16 +02:00
enjoy-digital
ca6065a6a1
Merge pull request #164 from xobs/litex-usb-server 
Litex usb server support
 2019-04-19 19:14:15 +02:00
Sean Cross
9dd59d6301 tools: remote: add usb communications protocol 
This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 17:29:50 +01:00
Florent Kermarrec
9cbed91b3e soc/interconnect/axi: add AXIBurst2Beat 
Converts AXI bursts commands to AXI beats.
 2019-04-19 12:13:16 +02:00
Florent Kermarrec
5a8115d9e1 soc/interconnect/avalon: add description 2019-04-19 11:43:15 +02:00
Sean Cross
c780fb22b7 Merge branch 'master' of https://github.com/enjoy-digital/litex 2019-04-19 16:47:55 +08:00
Florent Kermarrec
fa95608694 soc/integration/soc_zynq: fix HP0 connections 2019-04-19 10:21:56 +02:00
Sean Cross
e2cf45b8a9 cpu: vexriscv: allow cpu_reset_address to be overridden 
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 13:04:57 +08:00
Florent Kermarrec
a92e90b215 soc/interconnect: add avalon with converters to/from native streams 2019-04-18 18:42:29 +02:00