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Author SHA1 Message Date
Florent Kermarrec
daa4307d9e add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
Florent Kermarrec
361f9d0dff bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) 2019-06-22 10:55:15 +02:00
Tim 'mithro' Ansell
d8ac936206 Convert top level comment to a docstring. 2019-06-21 12:03:30 -07:00
William D. Jones
7656f54d0a soc: cores: add up5kspram module 
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-20 11:12:46 -07:00
Florent Kermarrec
73dbffe8f2 cores/frequency_meter: allow passing clk to be measured as a parameter 2019-06-20 09:03:30 +02:00
Gabriel L. Somlo
f75863fc31 cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants 2019-06-18 06:46:24 -04:00
Florent Kermarrec
c0df9e0823 cpu/rocket: update submodule 2019-06-18 09:44:13 +02:00
Florent Kermarrec
87118d509c integration/soc_core: move cpu_variant checks/formating to cpu 2019-06-17 09:55:27 +02:00
Florent Kermarrec
f6b67a6dae cpu/vexriscv: add "linux+no-dsp" variant 2019-06-17 09:54:17 +02:00
Florent Kermarrec
95b1b454f4 cpu/vexriscv: update 2019-06-17 09:24:57 +02:00
Ambroz Bizjak
ca70ea91e4
bios: Fix build when ethphy is present but ethmac is not. 
While testing my Ethernet DMA, I renamed the `ethmac` module to `ethmac_dma` so that it wouldn't be used from the BIOS, but I got an undefined reference to `eth_init` because `bios.c` checks different CSR defines than the code that defines `eth_init`.
 2019-06-13 01:02:22 +02:00
Florent Kermarrec
243d7c7696 soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker 
Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.
 2019-06-10 16:05:36 +02:00
Florent Kermarrec
1c34b4a015 cpu/vexriscv: update submodule 2019-06-10 12:57:21 +02:00
Florent Kermarrec
850b311d04 cpu/vexriscv: update submodule 2019-06-07 18:36:46 +02:00
Florent Kermarrec
c64129dc69 soc/integration/soc_core: list rocket as supported CPU 2019-06-07 11:14:36 +02:00
Florent Kermarrec
ca4e7811e9 software/bios: change prompt to "litex" in green. 2019-06-07 11:13:36 +02:00
Florent Kermarrec
8d0f008a3b integration/soc_core: improve readibility (add separators/comments) 2019-06-05 23:43:16 +02:00
Mateusz Holenko
93b61a65bf integration/builder: generate flash_boot address to csv 2019-06-05 17:37:23 +02:00
Mateusz Holenko
d0b019b1f0 integration/builder: generate shadow_base address to mem.h and csv 2019-06-05 17:37:09 +02:00
Gabriel L. Somlo
f88b85a31c software/libbase: memcpy: simple, arch-width agnostic implementation 
Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.

Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-04 14:48:51 -04:00
Tim Ansell
42e9d09755
Merge pull request #192 from sutajiokousagi/pr_c99_types 
fix signed char type to be explicitly signed
 2019-06-02 16:54:20 -07:00
bunnie
ab0b2cac2e fix signed char type to be explicitly signed 2019-06-03 06:01:13 +00:00
bunnie
200d413def update stdint.h to include c99 types 
needed for some third party libraries to compile
 2019-06-02 22:27:12 +00:00
Ilia Sergachev
db890736ea fix csr_name in add_csr() 2019-06-02 20:56:02 +02:00
Ilia Sergachev
40cbe3a952 fix interrupt_name 2019-06-02 20:52:31 +02:00
Gabriel L. Somlo
273a3ea15d soc/integration/cpu_interface: improve code legibility 
Factor out code appearing in both branches of an if/else.
 2019-05-29 10:07:43 -04:00
Florent Kermarrec
08a811b1a5 soc/interconnect/gearbox: add msb_first/lsb_first order 2019-05-29 10:25:25 +02:00
Florent Kermarrec
5109511259 soc/interconnect/axi: add round/robin arbitration between writes/reads 2019-05-25 10:02:31 +02:00
Florent Kermarrec
961101d809 bios/irc: remove compilation workaround 2019-05-25 09:24:48 +02:00
Florent Kermarrec
712977a0cf software/bios/isr.c: workaround compilation issue (need to be fixed) 2019-05-24 10:18:50 +02:00
Florent Kermarrec
28ba8b3201 soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) 2019-05-24 10:18:32 +02:00
Gabriel L. Somlo
019fd94005 fixup: generated-verilog submodule for experimental Rocket support 
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
 2019-05-23 18:22:37 -04:00
Gabriel L. Somlo
1a530cf27d soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) 
Simulate a Rocket-based 64-bit LiteX SoC with the following command:

  litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket

NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-05-23 15:59:51 -04:00
Florent Kermarrec
10670e22ac soc/cores/minerva: update to latest 2019-05-17 22:21:57 +02:00
Florent Kermarrec
0a8699f1e6 Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-05-16 15:15:30 +02:00
Florent Kermarrec
526ba1b165 soc_core: remove csr_expose and add add_csr_master method 
This could be useful in specific case were we don't have a wishbone master
but just want to have a csr bus and allow the user to define it.

/!\ Since there is no arbitration on between the CSR masters, use this with
precaution /!\
 2019-05-16 15:14:55 +02:00
Florent Kermarrec
1ea22d49b7 software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva 2019-05-15 22:40:32 +02:00
Florent Kermarrec
f25707012f software/bios/boot: remove specific linux commands (not needed with device tree) 2019-05-14 11:45:16 +02:00
Florent Kermarrec
eb6fa45833 cpu/vexriscv/core: update 2019-05-13 10:59:26 +02:00
Florent Kermarrec
0cad80e935 cpu/vexriscv: update submodule (new linux variant) 2019-05-13 10:59:03 +02:00
Florent Kermarrec
2f2b9b319f soc/cores: remove cordic 
Cordic is useful for DSP cores but not as a Soc building block.
 2019-05-11 09:36:53 +02:00
Florent Kermarrec
6e4ac1c493 LICENSE: clarify 2019-05-11 09:26:51 +02:00
Florent Kermarrec
67159349d6 soc/interconnect: remove axi_lite 
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has  proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
 2019-05-11 09:12:20 +02:00
Florent Kermarrec
a49d170a6d soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy 2019-05-10 15:46:22 +02:00
Florent Kermarrec
7445b9e2e0 soc/integration/soc_core: allow user to defined internal csr/interrupts 
For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.
 2019-05-10 11:05:34 +02:00
Florent Kermarrec
b6be534cd6 soc/integration/soc_core: rework csr assignation/reservation 
Similar refactor than on interrupts. Adds a add_csr method but still
retro-compatible with old way to declare CSRs.
 2019-05-09 23:32:22 +02:00
Florent Kermarrec
2abb3e809c Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-05-09 11:57:19 +02:00
Florent Kermarrec
47dc87584f integration/soc_core: rework interrupt assignation/reservation 
The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.

Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
 2019-05-09 11:54:22 +02:00
Mateusz Holenko
8caa38bc25 cpu: add reserved_interrupts property 2019-05-09 09:00:06 +02:00
Gabriel L. Somlo
c264a00964 soc/integration/cpu_interface: more arch-specific address size fixes 
When generating arch-specific include files (generated/[mem|csr].h)
ensure address literal defines are suffixed by 'L', denoting their
'unsigned long' type. This inhibits compiler warnings when values
computed based on these constants are cast to pointers.

Also ensure csr_[read|write][b|w|l]() function declarations have
'unsigned long' address arguments.

Finally, restore the correct (32-bit, (unsigned *)) expected
behavior of the MMPTR() macro, inadvertently converted to an
arch-specific sized access (unsigned long *) by commit 5c2b8685.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-05-08 16:03:36 -04:00
Florent Kermarrec
b7e3713388 bios/boot/ update linux memory mapping 2019-05-07 11:59:28 +02:00
David Shah
a048ba47c4 vexriscv: Fix some floating signals 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-04 17:27:21 +01:00
Florent Kermarrec
fcd518b5d0 bios/boot: add specific flash_boot for linux with vexriscv 2019-05-04 11:27:01 +02:00
Florent Kermarrec
1ba1ad9a00 bios/boot: rename MM_RAM to EMULATOR_RAM 2019-05-03 19:47:36 +02:00
Florent Kermarrec
fbb24720f0 soc/get_mem_data: add direct support for regions 
We now support passing filename (offset=0), json file and regions
 2019-05-03 13:24:06 +02:00
Florent Kermarrec
0714816f31 soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone 2019-05-03 11:59:06 +02:00
Florent Kermarrec
c6d0d23445 soc/interconnect/axi: add AXI Lite definition 2019-05-03 09:43:12 +02:00
Florent Kermarrec
9fab4752c4 soc/interconnect/axi: add comment on axi signas that are present but not used 2019-05-03 09:30:59 +02:00
Florent Kermarrec
5989076346 cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant 2019-05-03 09:30:26 +02:00
Florent Kermarrec
21bf10383d bios/boot: add liftoff banner just before booting 2019-05-02 18:26:35 +02:00
Florent Kermarrec
8f4685b3b1 bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config 2019-05-02 16:34:41 +02:00
Florent Kermarrec
6cf1ff091c soc/interconnect/axi: connect axi.ar/aw when selecting write or read 2019-05-02 09:58:55 +02:00
Florent Kermarrec
6affc56a09 soc/interconnect/axi: wishbone address shift is not always 2, make it generic 2019-05-02 09:35:07 +02:00
Florent Kermarrec
698bc88296 soc/interconnect/wishbone: allow setting adr_width (default to 30) 2019-05-02 09:34:30 +02:00
Florent Kermarrec
4dccb8a9eb soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent 2019-05-01 12:59:04 +02:00
Gabriel L. Somlo
5c2b8685fc software: use "unsigned long" for address values, also 8-byte alignment 
Enable future support for 64-bit CPU models.
 2019-04-29 15:03:38 -04:00
Florent Kermarrec
5c1d980540 soc/interconnect/axi: add burst support to AXI2Wishbone 2019-04-29 16:49:20 +02:00
Florent Kermarrec
6de2713524 soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize 2019-04-29 14:02:05 +02:00
Florent Kermarrec
305b8879de integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k) 
Keep or1k retro-compatibility for now but add a warning
 2019-04-29 10:14:30 +02:00
Florent Kermarrec
b40d1b73c4 cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) 2019-04-29 10:00:04 +02:00
Florent Kermarrec
dbb71af189 cpu: use property methods to return name, endianness, gcc triple/flags, linker output format 2019-04-29 09:58:51 +02:00
Florent Kermarrec
d828c3a596 cpu: integrate nmigen version of Minerva, add submodule 2019-04-28 23:40:33 +02:00
Kurt Kiefer
bf27869ad9 fix vexriscv build 2019-04-28 11:10:20 +02:00
enjoy-digital
2d5bae3def
Merge pull request #175 from mithro/cpu-docs 
Standardizing `cpu_variants` and adding lots of documentation
 2019-04-27 21:24:06 +02:00
Tim 'mithro' Ansell
5cbc5bc199 Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
Tim 'mithro' Ansell
71a837315a Work with no cpu_variant provided. 2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell
39c579baa2 Standardize the cpu_variant strings. 
Current valid `cpu_variant` values;
 * minimal  (alias: min)
 * lite     (alias: light, zephyr, nuttx)
 * standard (alias: std) - Default
 * full     (alias: everything)
 * linux

Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file
mirrored from the
[LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki).

Also support "extensions" which are added to the `cpu_variant` with a
`+`. Currently only the `debug` extension is supported. In future hope
to add `mmu` and `hmul` extensions.
 2019-04-26 17:44:30 -05:00
Florent Kermarrec
3a2e283613 .gitmodules: use our VexRiscv-verilog 2019-04-27 00:00:55 +02:00
Florent Kermarrec
78c09125be soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes 2019-04-25 23:43:10 +02:00
Florent Kermarrec
0175f86cb2 soc/integration/soc_core: fix get_mem_data for json files 2019-04-25 18:36:47 +02:00
Florent Kermarrec
4443b5075b soc/integration/soc_core: add integrated_sram_init 2019-04-25 17:30:03 +02:00
Florent Kermarrec
f27084c6c0 soc/integration/cpu_interface: fix banner in get_mem_header 2019-04-24 22:44:37 +02:00
Florent Kermarrec
e8f3c49127 software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding 2019-04-24 11:32:40 +02:00
Florent Kermarrec
44e0cdda9a software/libnet/microudp: speed-up ARP by changing timeout/tries 
First ARP request does not seem to be transmitted (the link is probably not
fully established). Reduce the timeout between tries and increase number of
tries.
 2019-04-24 09:55:41 +02:00
Florent Kermarrec
68f12495cf soc/integration: also add sha-1/date to generated software files 2019-04-23 13:17:54 +02:00
Florent Kermarrec
10cf0fdea3 cores/cpu/vexriscv: fix wrong revert 2019-04-23 11:13:29 +02:00
Florent Kermarrec
40342404f2 cores/clock: add divclk_divide_range on S6PLL/S6DCM 2019-04-23 06:43:48 +02:00
Florent Kermarrec
0d282f38f9 cores/clock: use common XilinxClocking class for all Xilinx clocking modules 2019-04-23 06:35:39 +02:00
Michael Betz
83699ea0a5 cores/clock: add initial Spartan6 PLL/DCM support 2019-04-23 06:23:00 +02:00
Florent Kermarrec
7d278854d5 global: switch to VexRiscv as the default CPU 
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
 2019-04-22 09:41:07 +02:00
Florent Kermarrec
9ee6c35b42 tools: move from litex.soc.tools to litex.tools and fix usb.core import 2019-04-20 10:44:53 +02:00
enjoy-digital
49fd93ae83
Merge pull request #165 from xobs/vexriscv-cpu-reset-address 
Vexriscv cpu reset address
 2019-04-19 19:16:16 +02:00
enjoy-digital
ca6065a6a1
Merge pull request #164 from xobs/litex-usb-server 
Litex usb server support
 2019-04-19 19:14:15 +02:00
Sean Cross
9dd59d6301 tools: remote: add usb communications protocol 
This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 17:29:50 +01:00
Florent Kermarrec
9cbed91b3e soc/interconnect/axi: add AXIBurst2Beat 
Converts AXI bursts commands to AXI beats.
 2019-04-19 12:13:16 +02:00
Florent Kermarrec
5a8115d9e1 soc/interconnect/avalon: add description 2019-04-19 11:43:15 +02:00
Sean Cross
c780fb22b7 Merge branch 'master' of https://github.com/enjoy-digital/litex 2019-04-19 16:47:55 +08:00
Florent Kermarrec
fa95608694 soc/integration/soc_zynq: fix HP0 connections 2019-04-19 10:21:56 +02:00
Sean Cross
e2cf45b8a9 cpu: vexriscv: allow cpu_reset_address to be overridden 
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 13:04:57 +08:00
Florent Kermarrec
a92e90b215 soc/interconnect: add avalon with converters to/from native streams 2019-04-18 18:42:29 +02:00
Joanna Brozek
40de01bcb0 vexriscv: Add full and full_debug CPU variant 2019-04-17 09:09:35 +02:00
Florent Kermarrec
c252972bef soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale 2019-04-15 11:36:42 +02:00
Florent Kermarrec
f986974d60 soc/cores/clock: improve presentation 2019-04-15 10:57:00 +02:00
Florent Kermarrec
13a76ec7fb software/libnet/microudp: simplify txbuffer managment 2019-04-12 18:47:31 +02:00
Florent Kermarrec
3441eb05cb software/libnet/microudp: cleanup eth_init 2019-04-12 17:15:09 +02:00
Florent Kermarrec
92a79c6dc1 software/libnet/microudp: simplify rxbuffer managment 2019-04-12 17:14:07 +02:00
Florent Kermarrec
fdeff7f64f software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE 2019-04-12 17:09:50 +02:00
Florent Kermarrec
1569e2e0cf software/libnet: remove use of ethmac_mem.h 2019-04-12 17:08:29 +02:00
Florent Kermarrec
c7ac96761c bios/sdram: add __attribute__((unused)) on cdelay 2019-04-11 22:26:58 +02:00
Florent Kermarrec
f8dcdb70d2 software/libnet: add #ifdef on eth_init 2019-04-10 16:16:47 +02:00
Florent Kermarrec
866fa34493 integration/soc_zynq: fix missing SoCCore.do_finalize 
Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
 2019-04-01 14:44:37 +02:00
Florent Kermarrec
794c3c5860 integration/soc_zynq: add add_hp0 method 2019-04-01 11:10:35 +02:00
Florent Kermarrec
38d404c3cb integration/soc_zynq: use add methods to add optional peripherals 2019-04-01 10:50:04 +02:00
Florent Kermarrec
7375856bec integration/soc_zynq: connect axi signals that were missing 2019-04-01 10:31:33 +02:00
Florent Kermarrec
b15fd9d834 interconnect/axi: add missing axi signals 2019-04-01 10:23:25 +02:00
Caleb Jamison
1f0b3f8124 Add ifdef check for MAIN_RAM_SIZE 2019-03-31 10:33:39 -05:00
Florent Kermarrec
dd214d2d21 bios/main: align SoC info, show CPU speed on CPU line, show L2 2019-03-30 11:49:39 +01:00
Florent Kermarrec
6599f7bb50 bios/main: move sdrinit 2019-03-30 10:56:17 +01:00
Florent Kermarrec
b92b89ab92 bios/main: print boot sequence only if sdr_ok 2019-03-30 10:19:00 +01:00
Florent Kermarrec
f4369c8fb2 bios/main: remove csr functions (not used and only supported by lm32), improve help presentation 2019-03-29 19:40:24 +01:00
Florent Kermarrec
66dffb7071 software/bios: improve readibility, add soc informations 2019-03-29 00:51:16 +01:00
Gabriel L. Somlo
449632e430 soc/interconnect/axi: data/address length cleanup 
Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
 2019-03-27 16:52:52 -04:00
Florent Kermarrec
552b0243b3 soc/interconnect/axi: remove dead code (thanks gsomlo) 2019-03-27 21:15:14 +01:00
Florent Kermarrec
3f386dad7d soc_core/get_mem_data: add json support 
example of json file:
{
    "vmlinux.bin":    "0x00000000",
    "vmlinux.dtb":    "0x01000000",
    "initramdisk.gz": "0x01002000"
}
 2019-03-16 21:23:36 +01:00
Florent Kermarrec
7b88980d06 vexriscv: allow user to use an external variant 2019-03-15 18:16:25 +01:00
Florent Kermarrec
b04a756abb vexriscv/core: fix min variant 2019-03-15 17:49:39 +01:00
Florent Kermarrec
317dba8314 software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation 
In the future, the PHYs should generated these constants.
 2019-03-05 18:03:24 +01:00
Florent Kermarrec
ca63db4040 bios/sdram: use burstdet detection for ECP5DDRPHY init 2019-03-05 13:27:06 +01:00
Florent Kermarrec
4bf789eab9 soc/software/bios/boot: add vexriscv workaround 
Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
 2019-03-01 09:16:48 +01:00
Florent Kermarrec
1fd81c2882 soc/integration: add initial SoCZynq SoC 2019-02-27 22:39:35 +01:00
Florent Kermarrec
3c527dcbdf soc/interconnect: add initial axi code with bus definition and AXI2Wishbone 2019-02-27 22:26:57 +01:00
Florent Kermarrec
ed2578799b test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) 2019-02-27 22:24:56 +01:00
Florent Kermarrec
4aa07f2ae9 soc/interconnect: rename axi to axi_lite 2019-02-27 22:11:09 +01:00
Florent Kermarrec
e38dfd99e8 soc/software/sdram: fix compilation on ultrascale 2019-02-25 16:12:21 +01:00
Florent Kermarrec
3dd529e40b soc/software/bios/sdram: add ECP5 support 2019-02-25 14:41:33 +01:00
Florent Kermarrec
2fd6d0e7e1 soc/software/bios/sdram: improve write_level robustness 2019-02-25 14:38:24 +01:00
Florent Kermarrec
36772b75f6 soc/software/bios/sdram: improve sdrlevel readibility 2019-02-25 14:37:31 +01:00
Florent Kermarrec
6a980781d3 soc/software/bios/sdram: add helpers for rst/inc of delays 2019-02-25 14:36:47 +01:00
Florent Kermarrec
ff155a474d soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write 2019-02-16 00:08:24 +01:00
Florent Kermarrec
d3ecdd9995 soc/cores/clock: add actual clk_freqs to config 2019-02-14 10:41:27 +01:00
Florent Kermarrec
af52842fbb soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches 2019-02-12 12:12:40 +01:00
Florent Kermarrec
aabf042d38 soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used 2019-02-11 09:23:39 +01:00
Florent Kermarrec
57b8bdd530 soc/integration/soc_core: allow disabling wishbone timeout 2019-01-29 12:47:11 +01:00
Florent Kermarrec
05dcb5cadc soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles 2019-01-27 08:28:01 +01:00
Florent Kermarrec
8344a6a4ef soc/cores/clock: add USIDELAYCTRL 2019-01-22 12:50:05 +01:00
Florent Kermarrec
7e0dd37616 soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case 
With ECC configurations, native port data_width is not necessarily a power of 2.
 2019-01-22 09:08:35 +01:00
Florent Kermarrec
1b23890e0d soc/cores/clock: allow ClockSignal to be used for clkin 2019-01-16 22:05:52 +01:00
Florent Kermarrec
7c67bac723 soc/cores/cpu/vexriscv: set default variant to None in add_sources 2019-01-09 10:28:24 +01:00
Florent Kermarrec
648015d78e soc/cores/cpu/vexriscv: move verilog variant selection to add_sources 2019-01-09 09:19:40 +01:00
Florent Kermarrec
2581a00380 soc/cores/clock: add Xilinx Ultrascale PLL/MMCM 2019-01-08 13:21:53 +01:00
Florent Kermarrec
041bf41226 soc/integration/cpu_interface: generate name for Memories in get_csr_header 2019-01-05 10:57:37 +01:00
Florent Kermarrec
9c801fbe50 soc/cores/clock/ECP5PLL: add basic phase support 2018-12-28 15:03:12 +01:00
Florent Kermarrec
ebe0d567f8 bios/sdram: only show read delays when they are valid. 2018-12-19 11:19:47 +01:00
Florent Kermarrec
67a2590235 bios/sdram: reduce write leveling scan range 2018-12-19 11:18:19 +01:00
Florent Kermarrec
fe5cef4294 soc/cores/clock: remove return on S7PLL.create_clkout 2018-12-19 09:14:26 +01:00
Florent Kermarrec
a27b5a3be1 update Ultrascale DDRPHY 2018-12-18 11:25:21 +01:00
Florent Kermarrec
f8f3683aaa bios/sdram: reduce scans verbosity on ultrascale 2018-12-17 16:00:44 +01:00
Florent Kermarrec
efce434aa9 bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY 2018-12-17 11:43:21 +01:00
Tim 'mithro' Ansell
22d454efcd Hack to fix #136. 2018-12-16 14:40:10 -08:00
Florent Kermarrec
e9f1049200 soc/cores/cpu/vexriscv: add add_debug method for debug variants 2018-12-12 10:01:49 +01:00
Florent Kermarrec
35155e5172 soc/cores/cpu/vexriscv: add support for the new variants. 2018-12-12 09:39:30 +01:00
Florent Kermarrec
2ace45e6f8 soc/cores/cpu/vexriscv: update submodule 2018-12-12 09:38:53 +01:00
Florent Kermarrec
6d6c2b4c45 soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) 2018-12-12 09:38:10 +01:00
Florent Kermarrec
0c687bc29e soc/interconnect/stream: add support for buffered async fifo 2018-12-08 01:24:08 +01:00
Florent Kermarrec
96527b5a3a soc/interconnect/stream/gearbox: remove bit reversing by changing words order 2018-11-30 23:12:30 +01:00
Florent Kermarrec
18048eb454 cores/clock: test and fix ECP5PLL, phase still not implemented. 2018-11-27 17:24:22 +01:00
Florent Kermarrec
909cff1940 bios/sdram: flush l2 cache only when present 2018-11-26 18:37:45 +01:00
Florent Kermarrec
2ad83778bf bios: allow testing main_ram at init when using an external controller 2018-11-26 15:21:00 +01:00
enjoy-digital
4592e3235b
Merge pull request #128 from mithro/small-fix 
Two small fixes
 2018-11-26 09:48:10 +01:00
Tim 'mithro' Ansell
4f565c5179 stream.Endpoint: Pass extra arguments to superclass. 2018-11-25 12:57:11 -08:00
Tim 'mithro' Ansell
3b9e4c4df6 wishbone.SRAM: Support non-32bit wishbone widths. 2018-11-25 12:56:37 -08:00
Florent Kermarrec
515c06219a cores/clock: add ECP5PLL 2018-11-24 00:47:38 +01:00
Florent Kermarrec
7623b5dd96 soc/interconnect/stream/gearbox: inverse bit order 2018-11-23 18:34:24 +01:00
Florent Kermarrec
d32e393033 soc/cores/spi_flash: add missing endianness parameter 2018-11-23 18:33:53 +01:00
Florent Kermarrec
1fe7d09fb5 soc/integration/soc_core: add csr_map_update function 2018-11-21 08:39:52 +01:00
William D. Jones
89c702187a libbase/crt0-picorv32: Add support for .data sections. 2018-11-21 00:13:13 -05:00
Florent Kermarrec
7359a99bf9 soc_core: convert cpu_type="None" string to None 2018-11-20 17:45:11 +01:00
Florent Kermarrec
a5ed42ec68 soc/interconnect/stream: add Gearbox 2018-11-17 17:29:45 +01:00
Florent Kermarrec
a538d36268 create utils directory and move the litex utils to it 2018-11-16 14:37:19 +01:00
Florent Kermarrec
af25bf2bc0 soc_core: check for cpu before checking interrupt 2018-11-13 16:17:49 +01:00
Florent Kermarrec
b4bdf2a023 cores/clock/S7: just reset the generated clock, not the PLL/MMCM 2018-11-13 14:47:04 +01:00
Florent Kermarrec
86fd945bc3 bios/main: fix typo on mor1kx 2018-11-13 11:16:06 +01:00
Florent Kermarrec
af95028574 cpu/mor1kx: use clang only for linux variant 2018-11-13 11:09:39 +01:00
Florent Kermarrec
9a6447172a soc/integration/soc_sdram: allow using axi interface with litedram 2018-11-09 15:42:34 +01:00
Florent Kermarrec
fc0d5c3963 bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients 2018-11-05 18:44:28 +01:00
Florent Kermarrec
2624ba48c2 bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 2018-11-05 10:47:25 +01:00
enjoy-digital
4cdd679908
Merge pull request #123 from cr1901/prv32-min 
PicoRV32 Enhancements
 2018-11-01 10:45:32 +01:00
William D. Jones
e56f71824d libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). 2018-11-01 05:02:04 -04:00
William D. Jones
f32121e0e1 cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. 2018-11-01 02:23:01 -04:00
William D. Jones
77389d27b5 libbase/crt0-picorv32: Ensure BSS is cleared on boot. 2018-11-01 02:18:03 -04:00
Florent Kermarrec
f7969b660a cores/clock: add with_reset parameter (default to True) 
In some cases we want to generate the reset externally.
 2018-10-31 16:23:23 +01:00
William D. Jones
f69bd877b9 cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). 2018-10-30 06:00:45 -04:00
William D. Jones
d05fe673a0 cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. 2018-10-30 06:00:45 -04:00
Florent Kermarrec
468780c045 soc/cores/spi_flash: add endianness parameter 2018-10-30 10:19:21 +01:00
Florent Kermarrec
6f3131e259 soc/interconnect/stream_packet: use reverse_bytes from litex.gen 2018-10-30 10:16:55 +01:00
enjoy-digital
b200ce9983
Merge branch 'master' into xilinx+yosys 2018-10-28 14:59:03 +01:00
Tim 'mithro' Ansell
ba0dd5728e uart: Enable buffering the FIFO. 
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
 2018-10-27 16:04:58 -07:00
Florent Kermarrec
a44181e716 soc_sdram: update litedram 2018-10-19 18:37:55 +02:00
Florent Kermarrec
ab6a530a24 bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode 2018-10-18 13:42:51 +02:00
Florent Kermarrec
ab8cf3e345 soc/cores/clock: add margin parameter to create_clkout (default = 1%) 2018-10-16 14:57:37 +02:00