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710 commits

Author SHA1 Message Date
Joanna Brozek
40de01bcb0 vexriscv: Add full and full_debug CPU variant 2019-04-17 09:09:35 +02:00
Florent Kermarrec
c252972bef soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale 2019-04-15 11:36:42 +02:00
Florent Kermarrec
f986974d60 soc/cores/clock: improve presentation 2019-04-15 10:57:00 +02:00
Florent Kermarrec
13a76ec7fb software/libnet/microudp: simplify txbuffer managment 2019-04-12 18:47:31 +02:00
Florent Kermarrec
3441eb05cb software/libnet/microudp: cleanup eth_init 2019-04-12 17:15:09 +02:00
Florent Kermarrec
92a79c6dc1 software/libnet/microudp: simplify rxbuffer managment 2019-04-12 17:14:07 +02:00
Florent Kermarrec
fdeff7f64f software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE 2019-04-12 17:09:50 +02:00
Florent Kermarrec
1569e2e0cf software/libnet: remove use of ethmac_mem.h 2019-04-12 17:08:29 +02:00
Florent Kermarrec
c7ac96761c bios/sdram: add __attribute__((unused)) on cdelay 2019-04-11 22:26:58 +02:00
Florent Kermarrec
f8dcdb70d2 software/libnet: add #ifdef on eth_init 2019-04-10 16:16:47 +02:00
Florent Kermarrec
866fa34493 integration/soc_zynq: fix missing SoCCore.do_finalize 
Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
 2019-04-01 14:44:37 +02:00
Florent Kermarrec
794c3c5860 integration/soc_zynq: add add_hp0 method 2019-04-01 11:10:35 +02:00
Florent Kermarrec
38d404c3cb integration/soc_zynq: use add methods to add optional peripherals 2019-04-01 10:50:04 +02:00
Florent Kermarrec
7375856bec integration/soc_zynq: connect axi signals that were missing 2019-04-01 10:31:33 +02:00
Florent Kermarrec
b15fd9d834 interconnect/axi: add missing axi signals 2019-04-01 10:23:25 +02:00
Caleb Jamison
1f0b3f8124 Add ifdef check for MAIN_RAM_SIZE 2019-03-31 10:33:39 -05:00
Florent Kermarrec
dd214d2d21 bios/main: align SoC info, show CPU speed on CPU line, show L2 2019-03-30 11:49:39 +01:00
Florent Kermarrec
6599f7bb50 bios/main: move sdrinit 2019-03-30 10:56:17 +01:00
Florent Kermarrec
b92b89ab92 bios/main: print boot sequence only if sdr_ok 2019-03-30 10:19:00 +01:00
Florent Kermarrec
f4369c8fb2 bios/main: remove csr functions (not used and only supported by lm32), improve help presentation 2019-03-29 19:40:24 +01:00
Florent Kermarrec
66dffb7071 software/bios: improve readibility, add soc informations 2019-03-29 00:51:16 +01:00
Gabriel L. Somlo
449632e430 soc/interconnect/axi: data/address length cleanup 
Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
 2019-03-27 16:52:52 -04:00
Florent Kermarrec
552b0243b3 soc/interconnect/axi: remove dead code (thanks gsomlo) 2019-03-27 21:15:14 +01:00
Florent Kermarrec
3f386dad7d soc_core/get_mem_data: add json support 
example of json file:
{
    "vmlinux.bin":    "0x00000000",
    "vmlinux.dtb":    "0x01000000",
    "initramdisk.gz": "0x01002000"
}
 2019-03-16 21:23:36 +01:00
Florent Kermarrec
7b88980d06 vexriscv: allow user to use an external variant 2019-03-15 18:16:25 +01:00
Florent Kermarrec
b04a756abb vexriscv/core: fix min variant 2019-03-15 17:49:39 +01:00
Florent Kermarrec
317dba8314 software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation 
In the future, the PHYs should generated these constants.
 2019-03-05 18:03:24 +01:00
Florent Kermarrec
ca63db4040 bios/sdram: use burstdet detection for ECP5DDRPHY init 2019-03-05 13:27:06 +01:00
Florent Kermarrec
4bf789eab9 soc/software/bios/boot: add vexriscv workaround 
Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
 2019-03-01 09:16:48 +01:00
Florent Kermarrec
1fd81c2882 soc/integration: add initial SoCZynq SoC 2019-02-27 22:39:35 +01:00
Florent Kermarrec
3c527dcbdf soc/interconnect: add initial axi code with bus definition and AXI2Wishbone 2019-02-27 22:26:57 +01:00
Florent Kermarrec
ed2578799b test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) 2019-02-27 22:24:56 +01:00
Florent Kermarrec
4aa07f2ae9 soc/interconnect: rename axi to axi_lite 2019-02-27 22:11:09 +01:00
Florent Kermarrec
e38dfd99e8 soc/software/sdram: fix compilation on ultrascale 2019-02-25 16:12:21 +01:00
Florent Kermarrec
3dd529e40b soc/software/bios/sdram: add ECP5 support 2019-02-25 14:41:33 +01:00
Florent Kermarrec
2fd6d0e7e1 soc/software/bios/sdram: improve write_level robustness 2019-02-25 14:38:24 +01:00
Florent Kermarrec
36772b75f6 soc/software/bios/sdram: improve sdrlevel readibility 2019-02-25 14:37:31 +01:00
Florent Kermarrec
6a980781d3 soc/software/bios/sdram: add helpers for rst/inc of delays 2019-02-25 14:36:47 +01:00
Florent Kermarrec
ff155a474d soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write 2019-02-16 00:08:24 +01:00
Florent Kermarrec
d3ecdd9995 soc/cores/clock: add actual clk_freqs to config 2019-02-14 10:41:27 +01:00
Florent Kermarrec
af52842fbb soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches 2019-02-12 12:12:40 +01:00
Florent Kermarrec
aabf042d38 soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used 2019-02-11 09:23:39 +01:00
Florent Kermarrec
57b8bdd530 soc/integration/soc_core: allow disabling wishbone timeout 2019-01-29 12:47:11 +01:00
Florent Kermarrec
05dcb5cadc soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles 2019-01-27 08:28:01 +01:00
Florent Kermarrec
8344a6a4ef soc/cores/clock: add USIDELAYCTRL 2019-01-22 12:50:05 +01:00
Florent Kermarrec
7e0dd37616 soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case 
With ECC configurations, native port data_width is not necessarily a power of 2.
 2019-01-22 09:08:35 +01:00
Florent Kermarrec
1b23890e0d soc/cores/clock: allow ClockSignal to be used for clkin 2019-01-16 22:05:52 +01:00
Florent Kermarrec
7c67bac723 soc/cores/cpu/vexriscv: set default variant to None in add_sources 2019-01-09 10:28:24 +01:00
Florent Kermarrec
648015d78e soc/cores/cpu/vexriscv: move verilog variant selection to add_sources 2019-01-09 09:19:40 +01:00
Florent Kermarrec
2581a00380 soc/cores/clock: add Xilinx Ultrascale PLL/MMCM 2019-01-08 13:21:53 +01:00
Florent Kermarrec
041bf41226 soc/integration/cpu_interface: generate name for Memories in get_csr_header 2019-01-05 10:57:37 +01:00
Florent Kermarrec
9c801fbe50 soc/cores/clock/ECP5PLL: add basic phase support 2018-12-28 15:03:12 +01:00
Florent Kermarrec
ebe0d567f8 bios/sdram: only show read delays when they are valid. 2018-12-19 11:19:47 +01:00
Florent Kermarrec
67a2590235 bios/sdram: reduce write leveling scan range 2018-12-19 11:18:19 +01:00
Florent Kermarrec
fe5cef4294 soc/cores/clock: remove return on S7PLL.create_clkout 2018-12-19 09:14:26 +01:00
Florent Kermarrec
a27b5a3be1 update Ultrascale DDRPHY 2018-12-18 11:25:21 +01:00
Florent Kermarrec
f8f3683aaa bios/sdram: reduce scans verbosity on ultrascale 2018-12-17 16:00:44 +01:00
Florent Kermarrec
efce434aa9 bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY 2018-12-17 11:43:21 +01:00
Tim 'mithro' Ansell
22d454efcd Hack to fix #136. 2018-12-16 14:40:10 -08:00
Florent Kermarrec
e9f1049200 soc/cores/cpu/vexriscv: add add_debug method for debug variants 2018-12-12 10:01:49 +01:00
Florent Kermarrec
35155e5172 soc/cores/cpu/vexriscv: add support for the new variants. 2018-12-12 09:39:30 +01:00
Florent Kermarrec
2ace45e6f8 soc/cores/cpu/vexriscv: update submodule 2018-12-12 09:38:53 +01:00
Florent Kermarrec
6d6c2b4c45 soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) 2018-12-12 09:38:10 +01:00
Florent Kermarrec
0c687bc29e soc/interconnect/stream: add support for buffered async fifo 2018-12-08 01:24:08 +01:00
Florent Kermarrec
96527b5a3a soc/interconnect/stream/gearbox: remove bit reversing by changing words order 2018-11-30 23:12:30 +01:00
Florent Kermarrec
18048eb454 cores/clock: test and fix ECP5PLL, phase still not implemented. 2018-11-27 17:24:22 +01:00
Florent Kermarrec
909cff1940 bios/sdram: flush l2 cache only when present 2018-11-26 18:37:45 +01:00
Florent Kermarrec
2ad83778bf bios: allow testing main_ram at init when using an external controller 2018-11-26 15:21:00 +01:00
enjoy-digital
4592e3235b
Merge pull request #128 from mithro/small-fix 
Two small fixes
 2018-11-26 09:48:10 +01:00
Tim 'mithro' Ansell
4f565c5179 stream.Endpoint: Pass extra arguments to superclass. 2018-11-25 12:57:11 -08:00
Tim 'mithro' Ansell
3b9e4c4df6 wishbone.SRAM: Support non-32bit wishbone widths. 2018-11-25 12:56:37 -08:00
Florent Kermarrec
515c06219a cores/clock: add ECP5PLL 2018-11-24 00:47:38 +01:00
Florent Kermarrec
7623b5dd96 soc/interconnect/stream/gearbox: inverse bit order 2018-11-23 18:34:24 +01:00
Florent Kermarrec
d32e393033 soc/cores/spi_flash: add missing endianness parameter 2018-11-23 18:33:53 +01:00
Florent Kermarrec
1fe7d09fb5 soc/integration/soc_core: add csr_map_update function 2018-11-21 08:39:52 +01:00
William D. Jones
89c702187a libbase/crt0-picorv32: Add support for .data sections. 2018-11-21 00:13:13 -05:00
Florent Kermarrec
7359a99bf9 soc_core: convert cpu_type="None" string to None 2018-11-20 17:45:11 +01:00
Florent Kermarrec
a5ed42ec68 soc/interconnect/stream: add Gearbox 2018-11-17 17:29:45 +01:00
Florent Kermarrec
a538d36268 create utils directory and move the litex utils to it 2018-11-16 14:37:19 +01:00
Florent Kermarrec
af25bf2bc0 soc_core: check for cpu before checking interrupt 2018-11-13 16:17:49 +01:00
Florent Kermarrec
b4bdf2a023 cores/clock/S7: just reset the generated clock, not the PLL/MMCM 2018-11-13 14:47:04 +01:00
Florent Kermarrec
86fd945bc3 bios/main: fix typo on mor1kx 2018-11-13 11:16:06 +01:00
Florent Kermarrec
af95028574 cpu/mor1kx: use clang only for linux variant 2018-11-13 11:09:39 +01:00
Florent Kermarrec
9a6447172a soc/integration/soc_sdram: allow using axi interface with litedram 2018-11-09 15:42:34 +01:00
Florent Kermarrec
fc0d5c3963 bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients 2018-11-05 18:44:28 +01:00
Florent Kermarrec
2624ba48c2 bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 2018-11-05 10:47:25 +01:00
enjoy-digital
4cdd679908
Merge pull request #123 from cr1901/prv32-min 
PicoRV32 Enhancements
 2018-11-01 10:45:32 +01:00
William D. Jones
e56f71824d libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). 2018-11-01 05:02:04 -04:00
William D. Jones
f32121e0e1 cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. 2018-11-01 02:23:01 -04:00
William D. Jones
77389d27b5 libbase/crt0-picorv32: Ensure BSS is cleared on boot. 2018-11-01 02:18:03 -04:00
Florent Kermarrec
f7969b660a cores/clock: add with_reset parameter (default to True) 
In some cases we want to generate the reset externally.
 2018-10-31 16:23:23 +01:00
William D. Jones
f69bd877b9 cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). 2018-10-30 06:00:45 -04:00
William D. Jones
d05fe673a0 cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. 2018-10-30 06:00:45 -04:00
Florent Kermarrec
468780c045 soc/cores/spi_flash: add endianness parameter 2018-10-30 10:19:21 +01:00
Florent Kermarrec
6f3131e259 soc/interconnect/stream_packet: use reverse_bytes from litex.gen 2018-10-30 10:16:55 +01:00
enjoy-digital
b200ce9983
Merge branch 'master' into xilinx+yosys 2018-10-28 14:59:03 +01:00
Tim 'mithro' Ansell
ba0dd5728e uart: Enable buffering the FIFO. 
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
 2018-10-27 16:04:58 -07:00
Florent Kermarrec
a44181e716 soc_sdram: update litedram 2018-10-19 18:37:55 +02:00
Florent Kermarrec
ab6a530a24 bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode 2018-10-18 13:42:51 +02:00
Florent Kermarrec
ab8cf3e345 soc/cores/clock: add margin parameter to create_clkout (default = 1%) 2018-10-16 14:57:37 +02:00
Florent Kermarrec
915c2f417a bios/sdram: improve write/read leveling 
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
 2018-10-10 10:42:56 +02:00
Florent Kermarrec
10624c26da bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) 2018-10-09 10:06:51 +02:00
Florent Kermarrec
d187921500 cpu_interface: fix select_triple when only one specified 2018-10-08 17:01:04 +02:00
Florent Kermarrec
3b27d2ae89 soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains 2018-10-06 21:32:38 +02:00
Florent Kermarrec
168b07b9a2 soc_core: add csr range check 2018-10-06 20:55:16 +02:00
Stafford Horne
ff6de429f0 Fix help for or1k builds 
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx.  Fix the message to properly represent what
needs to be passed to the commandline.
 2018-10-04 23:09:49 +09:00
Stafford Horne
dafdb8df72 Fix compiler warnings from GCC 8.1 
Fix these 2 warnings:

 litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
 [-Wstringop-truncation]
     strncpy(last_err, s, ERR_MAX_SIZE);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 In function 'set_last_error',

 litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  static char emerg_getc()
 2018-10-04 23:07:48 +09:00
Tim 'mithro' Ansell
d13ac3b3d5 cpu/mor1kx: Adding verilog include directory. 2018-10-03 21:57:24 -07:00
Florent Kermarrec
948527b0fe cores/cpu: revert vexriscv (it seems there is a regression in last version) 2018-10-02 12:30:11 +02:00
Florent Kermarrec
6e327cda26 bios/sdram: rewrite write_leveling (simplify and improve robustness) 2018-10-01 15:38:19 +02:00
Florent Kermarrec
934a5da559 soc/cores/clock: add expose_drp on S7PLL/S7MMCM 2018-09-28 13:02:10 +02:00
enjoy-digital
9097573e71
Merge pull request #109 from cr1901/xip-improve 
Improve XIP Support
 2018-09-25 15:32:04 +02:00
Florent Kermarrec
74e74dc0e7 soc/cores/clock: different clkin_freq_range for pll and mmcm 2018-09-25 09:09:47 +02:00
Florent Kermarrec
91d8cc2d6a soc/cores/clock: different vco_freq_range for pll and mmcm 2018-09-25 09:04:38 +02:00
Florent Kermarrec
6cd954940c soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) 2018-09-25 08:36:18 +02:00
Florent Kermarrec
912ca3236b soc/cores/clock: create specific S7IDELAYCTRL module 2018-09-24 23:22:59 +02:00
Florent Kermarrec
baec87f530 soc/cores/clock: add S7MMCM support 2018-09-24 23:20:12 +02:00
Florent Kermarrec
ef40524924 soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) 2018-09-24 22:58:23 +02:00
Florent Kermarrec
63fc395006 soc/cores: init clock abstraction module 2018-09-24 22:49:01 +02:00
William D. Jones
0ff6d58605 Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). 2018-09-24 14:48:54 -04:00
William D. Jones
8106008184 integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. 2018-09-24 12:28:45 -04:00
William D. Jones
db90619067 integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). 2018-09-24 11:04:57 -04:00
Florent Kermarrec
7f0d116d88 soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) 2018-09-24 10:59:32 +02:00
Florent Kermarrec
01b025aafd soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication 2018-09-24 08:01:32 +02:00
Florent Kermarrec
b528a005a0 cores/cpu: add software informations to cpu and simplify cpu_interface 2018-09-24 07:51:41 +02:00
Florent Kermarrec
c88029d330 soc_core: add uart-stub argument 2018-09-24 02:01:15 +02:00
Sean Cross
6f25a0d8a1 csr: use external csr_readl()/csr_writel() if present 
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.

With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:55:09 +02:00
Sean Cross
9a252e367c csr: use readl()/writel() accessors for accessing mmio 
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:54:46 +02:00
William D. Jones
9d4da737ff libbase/crt0-lm32.S: Add provisions for loading .data from flash. 
:100644 100644 e0cd7153 34428845 M	litex/soc/software/libbase/crt0-lm32.S
 2018-09-21 10:23:14 -04:00
Florent Kermarrec
1dbf591e78 targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) 2018-09-20 01:00:13 +02:00
Florent Kermarrec
9893c2460a integration/soc_core: add get_mem_data function to read memory content from file 2018-09-20 00:46:06 +02:00
Florent Kermarrec
a3eb2e403b soc/intergration/builder: fix when no sdram 2018-09-19 23:59:42 +02:00
Florent Kermarrec
9c6f76f18c bios/sdram: mode sdhw() 2018-09-13 06:33:54 +02:00
Florent Kermarrec
a44bedd557 bios/sdram: add missing #ifdef 2018-09-13 06:30:37 +02:00
Florent Kermarrec
1468b9f3ba bios/sdram: show all read scans when failing. 2018-09-13 05:26:51 +02:00
Florent Kermarrec
07e4c183cd cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) 2018-09-12 06:02:23 +02:00
Florent Kermarrec
df3f003ecd soc_sdram: update with litedram 2018-09-09 02:13:00 +02:00
enjoy-digital
bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram 
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
 2018-09-08 03:55:23 +02:00
William D. Jones
bd70ba278b Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. 2018-09-07 21:49:24 -04:00
Florent Kermarrec
12a8944711 soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) 2018-09-07 11:51:17 +02:00
Florent Kermarrec
2b786065b1 targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen 2018-09-07 10:37:15 +02:00
Jean-François Nguyen
26963d62fa libnet/microudp: (WIP) fix endianness issues 2018-09-06 18:43:55 +02:00
Jean-François Nguyen
22c0131324 fix typo and unused include 2018-09-06 17:07:14 +02:00
Florent Kermarrec
fb24ac0ecc cpu/minerva: add workaround on import until code is released 2018-09-06 16:40:30 +02:00
Jean-François Nguyen
8f377307d8 add Minerva support 2018-09-05 22:33:04 +02:00
Florent Kermarrec
1944289e64 litex_server: update pcie and remove bar_size parameter 2018-09-05 13:01:51 +02:00
William D. Jones
ed507d618d Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. 2018-09-03 19:48:19 -04:00
Tim Ansell
ff908e404f
Merge pull request #92 from cr1901/l2-gate 
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
 2018-08-23 13:15:49 +10:00
William D. Jones
3146109af3 software/bios: Gate flush_l2_cache() if L2 Cache isn't present. 2018-08-22 23:03:08 -04:00
Florent Kermarrec
759e7d4dc3 bios/sdram: improve/simplify read window selection 
Compute a score for each window and select the best
 2018-08-22 23:15:32 +02:00
Florent Kermarrec
06e835a3f8 builder: change call to get_sdram_phy_c_header and also pass timing_settings 2018-08-22 14:28:37 +02:00
Florent Kermarrec
ee26f8c5ae soc_sdram: cosmetic 2018-08-22 13:40:22 +02:00
Florent Kermarrec
2db5424ae6 soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) 2018-08-22 13:28:23 +02:00
Florent Kermarrec
45e9a42c7e soc_core: add cpu_endianness 2018-08-21 19:10:22 +02:00
Florent Kermarrec
3877d0f111 builder: get_sdram_phy_header renamed to get_sdram_phy_c_header 2018-08-21 18:15:57 +02:00
Florent Kermarrec
c64e44ef3f soc_sdram: use new LiteDRAMWishbone2Native and port.data_width 2018-08-21 14:52:28 +02:00
Florent Kermarrec
2eeccc5054 vexriscv: update 2018-08-21 11:04:15 +02:00
Florent Kermarrec
eecc6f68ed soc/integration: move sdram_init to litedram 2018-08-20 15:36:51 +02:00
Florent Kermarrec
077f939169 Vexriscv: update csr-defs.h 2018-08-18 14:15:43 +02:00
Florent Kermarrec
4225c3b87c update Vexriscv 2018-08-18 14:14:00 +02:00
Florent Kermarrec
9547938527 bios/sdram: changes to ease manual read window selection 2018-08-18 13:45:22 +02:00
Florent Kermarrec
a760322fbd litex_server: allow multiple clients to connect to the same server 2018-08-17 16:09:08 +02:00
Florent Kermarrec
8a69a47e7b cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) 2018-08-17 08:32:32 +02:00
Florent Kermarrec
cb5b4ac468 bios/boot: flush all caches before running from ram 2018-08-16 19:47:43 +02:00
Florent Kermarrec
0831ad5492 cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf 2018-08-16 10:04:09 +02:00
Florent Kermarrec
1610a7f3fb bios/sdram: fix read_level_scan result 2018-08-14 18:33:36 +02:00
Peter Gielda
3c7890cdd4
Fix generating csr.csv file 
Fix generating csr.csv file when no absolute path is given.
 2018-08-12 13:37:39 +02:00
Florent Kermarrec
9fa234da50 soc/intergration/cpu_interface: typo 2018-08-08 08:53:54 +02:00
Florent Kermarrec
22f645adc1 bios/main: use edata instead of erodata 2018-08-07 09:02:09 +02:00
Florent Kermarrec
580efecc8c picorv32: add reset signal 2018-08-07 08:59:34 +02:00
Florent Kermarrec
0429ee9f8f soc/software/bios: add reboot command 2018-08-06 12:23:50 +02:00
Florent Kermarrec
da75159814 soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers 2018-08-06 12:23:16 +02:00
Florent Kermarrec
8ba5625227 soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. 2018-08-06 12:21:18 +02:00
Florent Kermarrec
c0989f65dd soc/cores/cpu: add reset signal 2018-08-06 12:19:23 +02:00
Sean Cross
fb145daced tools: remove vexriscv_debug 
This program is no longer needed.

The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.

This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:25:33 +08:00
Sean Cross
f17b8324d4 vexriscv: reset wishbone bus on CPU reset 
If the CPU is resetting during a Wishbone transfer, assert the ERR line.

Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Sean Cross
c87ca4f1c3 vexriscv: put debug bus directly on wishbone bus 
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core.  Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.

Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Florent Kermarrec
df7e5dbcf6 bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup 2018-07-19 12:52:00 +02:00
Florent Kermarrec
1564b440eb soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 2018-07-19 12:51:16 +02:00
Florent Kermarrec
85308672d3 software/bios/linker: revert data section since required by RISC-V compiler 2018-07-18 09:30:14 +02:00
enjoy-digital
55dd58b023
Merge pull request #80 from xobs/fix-vexriscv-csr-read 
vexriscv_debug: use csr read()/write() accessors
 2018-07-17 17:31:48 +02:00
Sean Cross
41a9e7d9ae vexriscv_debug: use csr read()/write() accessors 
CSR access widths can be different from register widths.  8-bit
registers are common.

The runtime-generated `read()` and `write()` functions handle this
mapping correctly.  When direct register accesses are handled, this
mapping is lost.

Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-17 18:03:58 +08:00
Florent Kermarrec
7ecdcaca4b soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) 2018-07-16 18:40:36 +02:00
Florent Kermarrec
4f1274e6a6 bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) 2018-07-16 09:42:09 +02:00
Florent Kermarrec
7dbd85a842 soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) 2018-07-10 22:32:51 +02:00
Florent Kermarrec
ef1c778446 soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) 2018-07-10 13:29:32 +02:00
Florent Kermarrec
f9104b201a bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) 2018-07-06 19:22:33 +02:00
Florent Kermarrec
c84e189d6a bios/sdram: fix compilation with no write leveling 2018-07-06 16:22:49 +02:00
Sean Cross
be8eb5ff84 vexriscv: debug: fix reading DATA register 
The REFRESH register accepts an 8-bit address and determines which
register to refresh.  Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.

A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.

Replace this check with an explicit check for 0x00.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 18:22:32 +08:00
Sean Cross
6bc9265c2b setup: add vexriscv_debug to list of entrypoints 
Add the vexriscv_debug program to the list of scripts created when
installing this module.  This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 16:22:11 +08:00
Sean Cross
45a649be9b tools: vexriscv_debug: add debug bridge 
Add a bridge that uses litex_server to go from openocd to wishbone.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 16:08:06 +08:00
Florent Kermarrec
c821a0feab cores/cpu/vexriscv: create variants: None and "debug", some cleanup 2018-07-05 17:31:23 +02:00
Florent Kermarrec
59fa71593d core/cpu/vexriscv/core: improve indentation 2018-07-05 16:51:40 +02:00
Sean Cross
32d5a751db soc_core: uart: add a reset line to the UART 
Enable resetting the UART by adding a ResetInserter to the UART.

The UART must be reset when resetting the softcore.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:29 +08:00
Sean Cross
1ef127e06d soc: integration: use the new cpu_debugging flag for vexriscv 
Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:29 +08:00
Sean Cross
e7c762c8c3 soc: vexriscv: add cpu debug support 
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter.  With this enabled, a simple Wishbone interface is provided.

The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.

The debug register at address 4 is used to inject opcodes into the
core, and read back the result.

A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:28 +08:00
Sean Cross
2024542a3c vexriscv: verilog: pull debug-enabled verilog 
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v.  This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.

Sync the litex repo with the upstream version to take advantage of debug
support.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:27 +08:00
Florent Kermarrec
df99cc66e8 bios/sdram: also check for last read of scan to choose optimal window 2018-07-02 14:12:27 +02:00
Florent Kermarrec
8ce7fcb237 bios/main: add cpu frequency to banner 2018-07-02 13:47:18 +02:00
Florent Kermarrec
477d224921 bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. 2018-07-02 13:46:48 +02:00
Florent Kermarrec
9e737d3c57 soc/cores/code_8b10b: update (from misoc) 2018-06-29 14:24:44 +02:00
Florent Kermarrec
d58eb4ecb7 bios/sdram: use new phy, improve scan, allow disabling high skew 2018-06-28 18:43:48 +02:00
Florent Kermarrec
692cb14245 software/bios: fix picorv32 boot_helper 2018-06-28 11:42:43 +02:00
Florent Kermarrec
b5ee110e63 bios/sdram: add write/read leveling scans 2018-06-27 15:31:54 +02:00
Florent Kermarrec
8edc659d7d soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) 2018-06-19 11:15:29 +02:00
Florent Kermarrec
2c13b701f5 soc/integration/cpu_interface: add shadow_base parameter 2018-06-18 18:01:47 +02:00
Sean Cross
7444992999 soc: bios: fix windows build 
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`.  This command does not exist on Windows, and is unnecessary.

Add a conditional guard to prevent this command from running on Windows.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-06-18 17:13:54 +08:00
Florent Kermarrec
3e723d152a soc/cores/cpu: add add_sources static method 
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
 2018-06-12 10:54:20 +02:00
bunnie
7353197e21 fix the vexriscv boot helper 2018-05-31 01:24:22 +08:00
Florent Kermarrec
e7d1683e34 litex_term: cleanup getkey and revert default settings on KeyboardInterrupt 2018-05-24 08:10:05 +02:00
Florent Kermarrec
6854c7f5fc soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) 2018-05-09 15:39:25 +02:00
Dolu1990
66229c8c05 add VexRiscv support (imported/adapted from misoc) 2018-05-09 15:03:37 +02:00
Florent Kermarrec
f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec
d149f386c9 allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) 2018-05-09 13:26:55 +02:00
Florent Kermarrec
121eaba722 soc/intergration/soc_core: don't delete uart/timer0 interrupts 2018-05-01 00:46:26 +02:00
Florent Kermarrec
43f8c230a7 soc_core: uncomment uart interrupt deletion 2018-04-12 17:23:46 +02:00
Florent Kermarrec
4324c6f666 bios/sdram: update kuddrphy initialization procedure 2018-03-08 13:54:30 +01:00
Florent Kermarrec
90dcd45f0b soc/software/main: go to new line at startup 2018-03-07 21:39:10 +01:00
Florent Kermarrec
6706b24167 software/bios/main: add missing space 2018-03-07 15:24:39 +01:00
Florent Kermarrec
2a50a8021a soc/integration/soc_core: improve error message for missing csrs 2018-03-05 09:59:06 +01:00
Tim 'mithro' Ansell
5ef34500f7 Improving error message when csr name is not found. 
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```

Now;
```
Traceback (most recent call last):
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
    return self.csr_map[name]
KeyError: 'ddrphy'

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  ...
  File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
    mapaddr = self.address_map(name, None)
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
    ) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.

Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py

Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
 2018-03-03 16:02:44 -08:00
Florent Kermarrec
1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Sergiusz Bazanski
688f26cc32 Change AXI interface and tidy code 
Inspired by parts of https://github.com/peteut/migen-misc/
 2018-02-21 00:00:58 +00:00
Sergiusz Bazanski
512ed2b3d6 Preliminary AXI4Lite CSR bridge support 
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.

The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
 2018-02-20 21:27:51 +00:00
enjoy-digital
7b5bd4041a
Merge pull request #57 from rohitk-singh/master 
WIP - BIOS: Flashboot without main ram
 2018-02-10 21:37:38 +01:00
Florent Kermarrec
4f2725809e software/common: revert PYTHON to python3 (since breaking things) 2018-01-23 10:39:13 +01:00
Florent Kermarrec
4e168221d8 bios: fix riscv processor print 2018-01-23 10:33:05 +01:00
Florent Kermarrec
67f8718b26 minor cleanup 2018-01-23 00:35:20 +01:00
Sergiusz Bazanski
6daf3eabc5 Implement IRQ software support for RISC-V. 
Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.

It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
2108c97b9b Import PicoRV32-specific instruction macros. 
These come from the PicoRV32 repo and are released under the public
domain [1].

[1] - 70f3c33ac8/firmware/custom_ops.S
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
cf74c781f4 Write init files that respect CPU's endianness. 
This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
7176492231 Set the MABI and MArch of the riscv target. 
Again, this should be tunable, and synchronized with the core settings.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
7ea5a26734 Enable hardware multiplier and divider in PicoRV32 
This should become tunable later once we can configure whether we link
in the soft mul library or not.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
75e230aae7 Replace __riscv__ macros with __riscv. 
The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
20ed23443b Export trap signal from PicoRV32. 
This is useful for handling crashes from hardware.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
b0be563012 Bump PicoRV32 version. 2018-01-22 18:50:26 +00:00
Ewen McNeill
75e7f9505a BIOS: Flashboot without main ram 
Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash.  (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
 2018-01-20 15:05:47 +11:00
Florent Kermarrec
3a5f93db5d software/bios: add litex logo 2018-01-19 18:41:13 +01:00
Tim Ansell
fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port 
BIOS: Support alternate TFTP server port
 2018-01-18 13:40:28 +11:00
Ewen McNeill
5ce8ca8e9b BIOS: TFTP: try UDP/69 if specified port fails 2018-01-18 13:10:28 +11:00
Ewen McNeill
cb31266500 BIOS: set TFTP_SERVER_PORT from enviroment 2018-01-18 13:09:34 +11:00
Ewen McNeill
97f381baa6 BIOS: allow BIOS to specify TFTP server port 
Swaps hard coded PORT_OUT in tftp.c for parameter on the tftp_get()
and tftp_put() functions.  Allow TFTP_SERVER_PORT used by BIOS to be
set at compile time from compiler defines.
 2018-01-18 12:03:35 +11:00
enjoy-digital
e06bb3724b
Merge pull request #51 from felixheld/liteeth-untangling 
Include the ethernet related header files conditionally
 2018-01-16 21:37:24 +01:00
Felix Held
21ad435def Include the ethernet related header files conditionally 
Only including those header files in the litex firmware is the first step to
move the firmware parts of liteeth to the liteeth tree.
 2018-01-16 14:33:49 +11:00
Tim 'mithro' Ansell
3d40ad0a82 soc_core: Don't fail if name is the same. 
Otherwise you can't override the UART with another UART, you get an
error like;

```
  File "/home/tansell/github/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 176, in __init__
    interrupt, mod_name, interrupt_rmap[interrupt]))
AssertionError: Interrupt vector conflict for IRQ 2, user defined uart conflicts with SoC inbuilt uart
```
 2018-01-13 19:10:57 +11:00
Tim Ansell
bebaef1e25
Merge pull request #48 from mithro/fix-constants 
cpu_interface: Fix indenting on constant generation.
 2018-01-13 19:07:04 +11:00
Tim 'mithro' Ansell
f6f73cf13c cpu_interface: Fix indenting on constant generation. 
This was preventing constants from getting added to the csr.h header
file.
 2018-01-13 19:05:26 +11:00
Felix Held
6318a2b29a Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:19:36 +11:00
Chris Ballance
782711e5a9 bios/sdram: make read leveling robust for KUS SDRAM 
Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
 2018-01-12 19:23:08 +01:00
Florent Kermarrec
5681a3c1a9 bios/sdram: revert capability to do manual read leveling since still needed with some targets 2018-01-08 12:04:33 +01:00
Florent Kermarrec
03eb137449 bios/sdram: fix data error reporting 2018-01-08 11:43:49 +01:00
Florent Kermarrec
22ff745027 bump year 2018-01-08 11:43:13 +01:00
Florent Kermarrec
621aaf6988 soc/integration/soc_core: avoid removing uart interrupts (break some designs) 2017-12-30 18:41:49 +01:00
Tim 'mithro' Ansell
44650dffd8 cpu: Adding "variant" support. 
It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.

For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.

Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
 2017-12-30 01:18:51 +01:00
Greg Darke
bbd15ca567 Wait longer before giving up on the 2nd tftp block. 
Previously we would wait the same number of iterations as it took us to
receive the first data block after sending the request. When using the
build in tftp server in qemu, the first wait loop succeeds (and thus
breaks when 'i' is still 0.

Since the counter was never reset between the first and second data
block, under qemu the tftp_get call would fail before ever checking if
we have received the second block of data.

Now that we initialise 'i' to 12M, we ensure that we wait the same
amount of time for the second data block as it previously did for the
third (and subsequent) blocks.
 2017-12-29 23:56:32 +01:00
Florent Kermarrec
0a2d38ecd2 bios/sdram: use same initialization procedure for artix7 than kintex7 excepting write leveling that is not done 2017-12-29 17:13:58 +01:00
Florent Kermarrec
b78a4760bb soc/integration/builder: don't build bios is user is providing rom data 2017-12-28 22:42:58 +01:00
Florent Kermarrec
e7015e4191 soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file) 2017-12-26 18:11:47 +01:00
Florent Kermarrec
b31d0f37db cpu/picorv32: adapt to current version, some cleanup 2017-12-10 03:01:53 +01:00
Florent Kermarrec
4239aff68a cpu: cleanup wrappers 2017-12-10 02:52:01 +01:00
Florent Kermarrec
43429560d4 soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code 2017-12-08 10:18:01 +01:00
Florent Kermarrec
284b16e2c1 soc/integration/soc_core: make nmi interrupt optional 2017-12-03 23:07:41 +01:00
Florent Kermarrec
c1eba9a6cc soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware 2017-11-24 13:16:58 +01:00
Florent Kermarrec
831b489fd3 soc/interconnect/stream: fix specific cases for last/first signal in UpConverter 2017-11-23 17:58:02 +01:00
Florent Kermarrec
c3d902ef42 soc/software/bios/sdram: add Kintex Ultrascale support 2017-11-08 12:59:38 +01:00
Florent Kermarrec
2665a83288 soc/interconnect/stream: expose depth on SyncFIFO 2017-10-30 22:56:09 +01:00
Tim 'mithro' Ansell
56ef229029 Make the interrupt dicts read only. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
295e78ee9e Make it harder to have conflicting interrupts. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
73e0036b99 Change the default IRQs. 
* Reserve IRQ 0 to be used as a "non-maskable interrupt" (NMI) in the
   future.

 * Use IRQ 2 for the LiteX. This matches the standard mor1k config which
   connects the UART to IRQ 2.

This change is needed for Linux running on LiteX as it gets grumpy with
using IRQ 0 for anything other other than an NMI.
 2017-10-29 19:45:52 -07:00
Florent Kermarrec
db6c88bbef soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases) 2017-10-12 11:30:56 +02:00
Tim 'mithro' Ansell
279ec488e3 bios: Print location jumping too. 
Makes it easier to  understand what is happening (and that the BIOS is
jumping to the right place).
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
8152673d18 common: Compile with debugging symbols on. 
Debugging symbols are useful when using GDB :-)
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
b1b6a74170 or1k: Use EXCEPTION_STACK_SIZE of 256bytes. 
or1k defines a 128 byte "red zone" after the stack that can not be
touched by the exception handler.

We also need 128 bytes to store the 32 registers.
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
07a9df3586 bios: Declare dependency on linked in .a files. 2017-10-06 20:38:44 +11:00
Florent Kermarrec
ba1bf20f37 soc/cores: add cordic 2017-09-29 12:07:43 +02:00
enjoy-digital
878380abba Merge pull request #28 from enjoy-digital/eb-docs-2 
More docs for etherbone packet fields.
 2017-09-26 12:33:57 +02:00
Florent Kermarrec
2a8f6edded soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier 2017-09-06 15:39:54 +02:00
Tim Ansell
3a656c61d9 More docs for etherbone packet fields. 
Info comes from http://www.ohwr.org/attachments/1669/spec.pdf dated 24 July 2012
 2017-09-01 23:57:34 +10:00
Tim Ansell
c125ea6440 Adding a little docs to field descriptions. 2017-09-01 23:27:58 +10:00
Florent Kermarrec
8f3dcf90ab soc/software/bios/sdram: add optional memtest debug traces 2017-08-18 09:42:27 +02:00
Florent Kermarrec
c02de1632b soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists 2017-07-27 18:22:01 +02:00
Florent Kermarrec
04646b24ed soc/interconnect/stream: fix make_m2s for reset_less 2017-07-24 18:18:35 +02:00
Florent Kermarrec
756554371a soc/tools/remote/litex_server: allow multiple instance of server 2017-07-19 21:18:12 +02:00
Florent Kermarrec
d05d170b75 soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False 2017-07-19 12:18:35 +02:00
Florent Kermarrec
20c859d45c soc/tools/remote/etherbone: speed optimization (~20/30%) 2017-07-17 00:25:58 +02:00
Florent Kermarrec
bdea4152e3 soc/core/uart: add UartStub to enable fast simulation with cpu 2017-07-06 19:19:10 +02:00
Florent Kermarrec
c6f6d7b491 soc/interconnect/wishbonebridge: reset_less optimizations 2017-06-30 19:41:14 +02:00
Florent Kermarrec
7fcdd94cd4 soc/interconnect/stream_packet: reset_less optimizations 2017-06-30 19:40:54 +02:00
Florent Kermarrec
227b14c3f3 soc/interconnect/stream: improve reset_less support for streams 2017-06-30 19:40:17 +02:00
Florent Kermarrec
f5a971a8d8 soc/interconnect/stream: use reset_less attr of signal for payload and param 2017-06-28 23:10:45 +02:00
Florent Kermarrec
4d664730fe soc/software/libbase: fix get_ident 2017-06-28 18:10:56 +02:00
Florent Kermarrec
1364ac3657 soc/cores/identifier: append 0 to contents to indicate end of string 2017-06-22 17:53:19 +02:00
Florent Kermarrec
f720ef5631 soc/tools: simplify litex_server usage and integrage udp, pcie 2017-06-22 11:30:33 +02:00
Florent Kermarrec
41a91829eb soc/tools: syntax fix on comm_pcie, import in __init__.py 2017-06-22 11:29:57 +02:00
Florent Kermarrec
c82c1d103f soc/tools: fix debug prints of comm_pcie 2017-06-22 10:33:08 +02:00
Florent Kermarrec
684ae45dbe soc/tools: remove csr builder from comm_udp (we should use litex_server) 2017-06-22 10:32:39 +02:00
Florent Kermarrec
c44a4b051f soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases) 2017-06-09 19:35:48 +02:00
Florent Kermarrec
c19c4b711b soc/cores/identifier: remove additionnal first character 2017-06-08 14:15:27 +02:00
Florent Kermarrec
77732fca95 soc/cores/uart: add uart multiplexer 2017-06-05 19:36:30 +02:00
Florent Kermarrec
85aea62d74 soc/core: add frequency meter 2017-06-01 00:39:19 +02:00