7a7b9420e6
soc/integration/soc_dram: sync with litedram
2016-05-03 19:44:33 +02:00
dca8b3c92e
boards/targets/sim: update litedram
2016-05-01 10:26:21 +02:00
69f0035315
gen/fhdl: add Display for debug in simulation
2016-04-29 23:03:43 +02:00
e79b2e3fef
boards/targets: SDRAM modules are now litedram.modules
2016-04-29 19:05:23 +02:00
3d71ba6e66
targets: remove sdram_controller_type parameter (minicon removed)
2016-04-29 17:51:16 +02:00
8c7332e75e
soc/integration/soc_sdram: use new LiteDRAM names
2016-04-29 17:40:55 +02:00
dc52d33fba
soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage)
2016-04-29 16:24:24 +02:00
44d766c09f
software/sdram: cleanup artix7 init
2016-04-29 15:55:10 +02:00
66362b1280
move sdram code to litedram ( https://github.com/enjoy-digital/litedram )
2016-04-29 07:45:15 +02:00
42767286ca
gen/fhdl/verilog: add do in reserved_keywords
2016-04-27 17:43:25 +02:00
80d673e502
soc/integration/soc_sdram: always generate L2_SIZE constant
2016-04-27 12:34:18 +02:00
4e451a78d6
soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found manually)
2016-04-27 12:33:44 +02:00
ab8569916b
boards/platforms/arty: use 1.5V and the 16bits instead of only 8bits
2016-04-26 23:29:35 +02:00
e6681bbb9c
soc/interconnect/wishbone: add FlipFlop (should be removed)
2016-04-25 19:14:20 +02:00
b6d8999471
platforms/arty: add missing address pins, was not going to work :(
2016-04-25 16:56:23 +02:00
f6e1c45d57
gen/genlib/record: fix connect
2016-04-21 19:05:01 +02:00
e80cfedd7f
gen/genlib/record: fix connect
2016-04-21 12:16:26 +02:00
9ae16c2f40
boards/platforms/nexys_video: use TDMS_33 on hdmi
2016-04-21 11:13:29 +02:00
3d98be0997
use new Record.connect omit parameter (replace leave_out)
2016-04-21 09:39:21 +02:00
c330e7be49
gen/genlib/record: rename leave_out by omit and add keep parameter to Record.connect
2016-04-21 09:39:12 +02:00
ee378b2557
boards/plaforms/nexys_video: fix hdmi_out pinout
2016-04-19 19:04:05 +02:00
849434c1bd
soc/software/bios: show cpu on first banner line
2016-04-19 09:19:37 +02:00
76bb0ef456
Merge pull request #2 from mithro/master
...
More fixes.
2016-04-19 09:07:23 +02:00
1b9ab2f1fc
soc/integration/cpu_interface: fix clang detection
2016-04-19 08:06:56 +02:00
d9b598368f
Make verilator build output error messages.
2016-04-19 16:02:26 +10:00
8998ae5c92
bios: Print CPU architecture on boot.
2016-04-19 16:02:26 +10:00
e0e56e3655
Merge pull request #1 from mithro/master
...
Bunch of small fixes
2016-04-19 07:49:24 +02:00
514496d744
libcompiler_rt: Fixing Makefile for CPU endianness.
2016-04-19 14:55:01 +10:00
5ba03160ed
soc/cores: fix spi
2016-04-19 06:49:23 +02:00
7b7f1dd68c
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-19 06:05:22 +02:00
e7f3c585b7
Allow using gcc for or1k.
...
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
* or1k continues to default to CLANG if environment is not net.
2016-04-19 14:03:24 +10:00
2f834d0aa2
bios: Use single characters for boot modes.
...
* The function keys never really worked properly.
* Also add commands for the ROM/Flash/etc.
2016-04-19 13:42:56 +10:00
429f533bd0
soc/cores/sdram/settings: simplify modules and fix timing margins computation
2016-04-18 18:22:53 +02:00
41f6408d56
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-15 08:09:42 +02:00
7b3699839e
build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint
2016-04-14 21:48:52 +02:00
3d222d9e63
soc/interconnect/dma_lasmi: change endpoint names
2016-04-13 18:28:52 +02:00
fcd8d792a1
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-13 01:19:21 +02:00
6e0045e6be
soc/integration/soc_sdram: allow passing controller settings in register_sdram
2016-04-12 20:16:47 +02:00
40eb779e67
software/include/base: fix system.h for or1k
2016-04-10 17:21:54 +02:00
238d69f186
software/common: use -std=gnu99 for GCC
2016-04-10 17:21:17 +02:00
b2eaf412c1
soc/interconnect/stream/PipelinedActor: add latency attribute
2016-04-07 12:10:32 +02:00
9fa9bdcf68
build/sim: adapt verilator simulation to new stream signals
2016-04-07 08:56:53 +02:00
8ced064160
soc/software/libcompiler_rt: fix mulsi3 compilation
2016-04-07 08:28:38 +02:00
80d78698e3
soc/software/libnet/microudp: fix debug flag
2016-04-07 08:28:38 +02:00
454d5d13e2
soc/software: fix libcompiler_rt mulsi3.c compile
2016-04-04 08:36:23 +02:00
17f6cb1f17
initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)
2016-04-01 00:09:17 +02:00
7e62cdf601
soc/software/bios: update default ip addresses (local: 192.168.1.50 / remote: 192.168.1.100)
2016-03-31 10:55:11 +02:00
1d4f44e7db
soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores
2016-03-31 00:02:22 +02:00
b8d89535fd
soc/cores/sdram/phy: fix S6QuarterRateDDRPHY
2016-03-29 14:59:30 +02:00
f512971d9e
gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)
2016-03-25 13:22:26 +01:00
0ef1d44c44
gen/sim, fhdl: remove port.we_granularity limitation on simulations
...
We have to find a way to eliminate all replaced memory ports from specials,
here we use a workaround and remove remaining _MemPorts before simulating.
If possible, proper way would be to remove replaced ports from specials.
Another solution can to remove all ports that are no longer associated with
a Memory.
2016-03-23 09:46:54 +01:00
9517b9b870
soc/interconnect/stream_sim: use passive generators and some cleanup
2016-03-23 01:04:33 +01:00
5e16516706
gen: add missing sim files
2016-03-21 23:52:52 +01:00
dd2397b57c
gen: remove vpi (no longer used)
2016-03-21 20:07:03 +01:00
cf29ee0b91
soc/interconnect/stream_sim: adapt to new simulator
2016-03-21 19:56:43 +01:00
703b30e078
gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator
...
* fhdl/visit: determinism
* structure/Case/makedefault: fix corner cases
* fhdl/tools: apply lowerer to specials in deterministic order
* fhdl/verilog: fix variable name conflict
* fhdl/verilog: simpler names for IOs. Closes #40
* fhdl/namer: deterministic naming of signals with name_override
* use https url for m-labs.hk
* pipistrello: make PMOD an extension header
* vivado: find clock nets by get_nets, not get_ports
* build: support platform-independent false path designation
* sim: add more signals to VCD (#36 )
* build/xilinx: fix error message when Xilinx toolchain directory exists but does not contain a ISE version directory. Closes #39
* kc705: make xadc an extension header
* kc705: add xadc/ams gpios
* Merge branch 'master' of github.com:m-labs/migen
* conda: fix for conda-build > 1.19
* platforms/kc705: enable on-die termination for user_sma_clock
* README: update
* Revert "conda: use BUILDNUMBER from environment."
This reverts commit b2eedfd2e24f0b83c2fb118a3f98cf349b256e91.
* conda: use BUILDNUMBER from environment.
* typo
* Exception now has helpful string.
* README: remove outdated build badge
* sim: run MemoryToArray before lowering specials
* fhdl/simplify/MemoryToArray: remove spurious memory ports from specials
* sim: make unlowered specials an error
* sim: lower specials, closes #34
* sim: support evaluating Replicate()
* Revert "README.md->rst"
* Prevent backslashes in (Windows) paths from being escaped by OpenOCD's TCL implementation.
* Revert "conda: run tests as a part of package build."
* Revert "setuptools: include examples as migen.examples."
* Revert "test: also look for examples in [.../dist-packages]/migen/examples/."
* conda: use source from the current checkout.
* travis: disable (superseded by our buildbot).
* test: also look for examples in [.../dist-packages]/migen/examples/.
* setuptools: include examples as migen.examples.
* conda: run tests as a part of package build.
* build: return to current working directory after building
* sim/vcd: support signals not appearing in FHDL
* sim: deterministic clock iteration
* sim: add support for passive generators
* fhdl/structure: fix last test in _Value.__bool__ (a instead of b)
2016-03-21 19:15:40 +01:00
71a719be44
soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 20:13:47 +01:00
9032665750
soc/interconnect/wishbonebridge: fix import
2016-03-16 19:34:50 +01:00
d7112efdba
soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now)
2016-03-16 19:33:29 +01:00
39aacf2df4
soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring
2016-03-16 19:33:00 +01:00
e0e2427795
soc: replace all Sink/Source with stream.Endpoint
2016-03-16 18:05:57 +01:00
c860581b86
soc/interconnect/stream: use new Converter/StrideConverter
2016-03-16 17:00:58 +01:00
8c272c1f6f
soc/interconnect/stream: fix missing param
2016-03-16 16:21:32 +01:00
cb47373383
soc/interconnect/stream: remove packetized parameter and use of sop
2016-03-16 11:54:28 +01:00
44a5b95281
soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter)
2016-03-15 15:52:57 +01:00
a016ededa0
soc/integration/builder: remove use of symlinks (simply use make -C dst_dir -f src_dir/Makefile, thanks robert)
2016-03-04 20:56:05 +01:00
042c36ee1b
soc/tools/litex_term: continue cleanup
2016-02-19 17:44:25 +01:00
2fa848c15f
soc/tools/litex_term: continue cleanup
2016-02-19 14:35:18 +01:00
247ecc5d8a
soc/tools/litex_term: continue cleanup
2016-02-19 13:38:34 +01:00
ed2e623994
soc/tools/litex_term: remove write_exact, use more bytes
2016-02-19 00:20:10 +01:00
4bdefbdfba
soc/tools/litex_term: remove character function
2016-02-19 00:02:38 +01:00
5b8566d20f
soc/tools/litex_term: replace get_file_data with f.read()
2016-02-18 23:55:41 +01:00
68c2d3b7a0
soc/tools/remove: fix import
2016-02-18 12:55:18 +01:00
fd2997bf4a
build/xilinx: cleanup Vivado/ISE special_overrides
2016-02-18 00:36:53 +01:00
8ee3874088
soc/integration/soc_core: instanciate wishbone/csr/interrupts only if we have at least a wishbone master
2016-02-18 00:11:25 +01:00
34b45e3618
gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)
2016-02-11 22:54:26 +01:00
2218ece98a
soc/interconnect/stream: fix merge issue (missing params connect)
2016-02-01 00:08:27 +01:00
6c71811138
soc/tools/litex_term: also rename inside file
2016-01-16 21:26:33 +01:00
601c91a3e2
soc/tools: rename to litex_term, litex_server, litex_client
2016-01-16 21:22:21 +01:00
162900144a
soc/tools/remove_server: cleanup
2016-01-16 21:12:19 +01:00
b856b54720
soc/tools/flterm: get rid of serial.tools.miniterm import and fix echo on linux
2016-01-16 21:05:03 +01:00
002508a69a
soc/integration: return vns with soc and builder
2016-01-14 17:15:39 +01:00
2c32791a28
soc/software/bios/main: add capability to configure TEST_USER_ABORT_DELAY
2016-01-14 16:53:04 +01:00
492f276247
soc/software/bios/main: give priority to romboot over serialboot/netboot
2016-01-14 16:46:42 +01:00
9913da5ac9
boards/targets: change mode (add +x)
2016-01-01 18:37:20 +01:00
7b879b36c6
soc/tools/remove/server: avoid closing server when client closes connection
2015-12-27 22:33:08 +01:00
0498a31818
some cleanup
...
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
2015-12-27 13:09:58 +01:00
219fbef26c
soc/tools/remove/client: set socket timeout to 5s
2015-12-27 11:26:58 +01:00
6ea65f957c
soc/interconnect/stream: expose Endpoint
2015-12-19 21:49:45 +01:00
6a4e3bb5c0
build/xilinx/vivado: use build_name as top in synth_design
2015-12-09 11:40:27 +01:00
3191533889
soc/software/libnet: add debug defines on microudp
2015-12-07 12:03:36 +01:00
4fed1cc7a7
soc/integration/builder: move csr_csv generation outside of generate include
...
we mostly use csr_csv for designs without CPU
2015-12-03 15:16:22 +01:00
90f03133ef
build/sim/verilator: add toolchain_path parameter
2015-12-02 15:35:55 +01:00
e8262ed447
build: pass build_name to get_verilog (same name for top module and top level file)
2015-12-02 14:18:09 +01:00
b7a1888a36
gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation code (for icarus)
...
We will remove that when we will be using new migen simulator
2015-12-02 14:16:23 +01:00
646d3b19b4
boards/nexys_video: use ethernet constraints similar to kc705
2015-12-01 11:50:05 +01:00
ca6b9aa6e3
boards/targets: add default rom/ram configuration for arty
2015-12-01 10:20:16 +01:00
e5d35ccb6d
boards/targets: add nexys_video
2015-12-01 10:19:41 +01:00
4bfd1fdce6
boards/plaforms: fix IOStandard of eth_rst_n
2015-11-30 22:27:40 +01:00
b6a6b5d540
boards/platforms: add cpu_reset to nexys_video and some fixes around DDR3
2015-11-30 21:53:01 +01:00
5694dca0fc
boards/platforms: add hdmi_in/hdmi_out/ethernet/dram to nexys_video
2015-11-30 20:46:57 +01:00
7e1df951ba
boards/platforms: add nexys_video (basic)
2015-11-30 20:25:00 +01:00
a716c562f0
gen/build: use name_override for all IOs defined in Platform file (avoid random naming of IOs)
2015-11-30 18:26:33 +01:00
53c86e34f4
build: ensure we return to working directory after building
2015-11-30 13:33:39 +01:00
f6aeb6e41a
soc/interconnect/stream: improve Pipeline to allow passing endpoints
2015-11-28 18:31:47 +01:00
d85d2b7b9b
soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field
2015-11-27 20:14:01 +01:00
c0539fff3e
boards: add new digilent arty
2015-11-27 00:29:30 +01:00
c24727ab4c
soc/integration: allow using builder with soc.cpu_type == None
2015-11-26 17:44:50 +01:00
7298fff1e6
soc/interconnect/stream_packet: fix Counter removing
2015-11-24 20:30:53 +01:00
8ebffc563a
soc/tools/remote/csr_builder: manage memory regions and some fixes on CSRRegister
2015-11-23 19:13:37 +01:00
254504e73f
soc/integration/builder: export constants and memory_regions with csr_csv
2015-11-23 19:12:58 +01:00
f6a2d5847a
soc/tools/remote/client: make csr_csv parameter optional and default value to None
2015-11-23 18:39:28 +01:00
6f4dd14ffa
soc/software/boot: add #ifndef on LOCALIP and REMOTEIP to allow definition in the SoC with add_constant
2015-11-23 11:08:04 +01:00
cb22a207f1
build/generic_platform: add support for int parameter for Pins (useful for core generation)
2015-11-19 14:57:09 +01:00
8056653004
soc/tools/remote/server: add --debug parameter
2015-11-17 15:43:10 +01:00
6870707620
soc/tools/remoter/server: fix exit on KeyboardInterrupt
2015-11-17 15:31:23 +01:00
8ff31557c6
soc/tools/remoter/server: add some printfs
2015-11-17 15:18:46 +01:00
1a92489555
soc/tools/remote: add comm_pcie and comm_udp (to be tested)
2015-11-17 15:07:00 +01:00
d6fdd76930
soc/tools/remote: small cleanup and remove csr_data_width from server side
2015-11-17 11:35:22 +01:00
71483b8935
soc/tools: initialize wishbone remote control (for now only uart)
2015-11-17 01:05:52 +01:00
1cde84dccf
soc/cores/uart remove software (will be re-written and will move to soc/tools)
2015-11-16 17:07:22 +01:00
1f80bb9561
soc/interconnect/stream_packet: remove Counter
2015-11-16 16:53:23 +01:00
ec35290c45
soc/interconnect/wishbonebridge: remove Counter
2015-11-16 16:48:37 +01:00
6fd0b73817
build: remove edif support
2015-11-16 16:26:38 +01:00
e407a1cdda
gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign
2015-11-16 16:18:09 +01:00
2f52d364af
soc/interconnect/stream/SyncFIFO: expose fifo level
2015-11-16 16:11:31 +01:00
7ed2576ce1
soc/integration/cpu_interface: add bases, constants and memories output to csv files
2015-11-15 00:04:44 +01:00
af909b43d5
soc/cores/uart: add UARTWishboneBridgeDriver software
2015-11-14 21:23:20 +01:00
3a2e6117f4
soc/interconnect/stream: add Cast and others small fixes
2015-11-14 12:17:09 +01:00
041483dbe1
soc/integration/builder: only copy Makefiles when not using symlinks
2015-11-14 03:36:46 +01:00
a2aa5726bf
soc/cores: remove liteeth_mini and use liteeth
2015-11-14 03:22:43 +01:00
16ba646b1b
add TODOs
2015-11-14 03:15:10 +01:00
cf4c7da2e7
fix soc/integration/soc_core.py
2015-11-14 02:44:12 +01:00
032f5a9620
soc/interconnect: add stream_sim
2015-11-14 00:43:49 +01:00
ba959c832d
soc/interconnect: rename packet to stream_packet
2015-11-14 00:42:58 +01:00
fc3ffe87ac
for now use our fork of migen (to be able to simulate our designs)
2015-11-13 18:31:46 +01:00
ae3d54499a
litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented
2015-11-13 14:44:16 +01:00
7d6cee6751
soc/interconnect/stream: add BufferizeEndpoints
2015-11-12 18:54:15 +01:00
83427c87cd
soc/interconnect/stream: add Pipeline
2015-11-12 01:41:23 +01:00
81c6facca2
soc/interconnect/stream: reintroduce params
2015-11-12 01:12:15 +01:00
f6b30fcae2
soc/interconnect: add packet
2015-11-12 00:54:40 +01:00
525da89c7d
soc/interconnect: add wishbonebridge and uart bridge
2015-11-12 00:52:36 +01:00
89b189ce4a
soc/interconnect/stream: reintroduce PipelinedActor/Buffer
2015-11-12 00:51:32 +01:00
194e6137ae
soc/integration/soc_core: add support for SoCs without CPU
2015-11-12 00:50:23 +01:00
c076c2cbd6
boards/targets: remove papilio_pro/pipistrello
2015-11-11 17:38:03 +01:00
352cb91688
soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default
...
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
2015-11-11 17:37:28 +01:00
1cec0f8086
boards/targets/sim: add ethernet support
2015-11-11 14:23:39 +01:00
1f6983da2c
soc/cores/liteeth_mini: add phy model for verilator simulation
2015-11-11 14:22:27 +01:00
481163b233
soc/cores: reintroduce liteeth_mini (until we switch to liteeth)
2015-11-11 14:01:48 +01:00
714a3d88e2
add LICENSE, update copyrights, add Migen install instructions
2015-11-11 13:22:39 +01:00
bda196fbc8
soc/software/bios/sdram: split memtest and allow external #define of memtest sizes
2015-11-11 13:10:03 +01:00
619cd8e695
avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
2015-11-11 12:10:55 +01:00
3f43a49382
soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b
...
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
2015-11-10 16:51:51 +01:00
3297210e48
boards/targets/sim: get SDRAM working in simulation with sdram/model
2015-11-10 12:57:23 +01:00
4afe4a07e4
soc/software: remove memtest (should be re-written)
2015-11-10 12:22:08 +01:00
6764c06b62
soc/sofware: remove libdyld
2015-11-10 12:21:23 +01:00
f72e172ac3
soc/software: remove libunwind
2015-11-10 12:16:34 +01:00
85e6716b6b
litex/build/xilinx/programmer: remove UrJTAG and Adept
2015-11-10 12:01:25 +01:00
a775672314
litex: get verilator simulation working and add sim target as example
2015-11-07 23:51:37 +01:00
6a0f85dc42
litex: reorganize things, first work working version
2015-11-07 17:48:55 +01:00
637634f312
import migen in litex/gen
2015-11-07 12:22:32 +01:00
b028569784
import misoc in litex/soc
2015-11-07 12:19:30 +01:00
Florent Kermarrec
Tim 'mithro' Ansell