8ffa273719
flow/network: better determination of plumbing layout
2013-05-01 22:13:26 +02:00
471393d0f9
actorlib/dma_asmi: drive dat_wm
2013-05-01 21:52:26 +02:00
c8810a016f
actorlib/spi: add DMA read controller
2013-04-30 18:55:01 +02:00
c70c71502e
actorlib/spi/SingleGenerator: use CSR alignment bits
2013-04-30 18:54:47 +02:00
dc0304a87b
bank/description/CSRStorage: support alignment bits
2013-04-30 18:53:40 +02:00
51f1ace061
flow/network/CompositeActor: expose unconnected endpoints
2013-04-30 18:53:02 +02:00
4f13c5b74d
flow/network/DataFlowGraph: add add_pipeline
2013-04-30 15:49:51 +02:00
fb83794ef4
actorlib/spi/Collector: cleanup, new APIs
2013-04-28 18:32:46 +02:00
746e452838
actorlib/dma_asmi: support for writes
2013-04-28 18:06:36 +02:00
e97edd7253
genlib/fifo: disable retiming on Gray counter outputs
2013-04-25 14:57:07 +02:00
156ef43ace
genlib/cdc: add NoRetiming
2013-04-25 14:56:45 +02:00
b862b070d6
fhdl/verilog: recursive Special lowering
2013-04-25 14:56:26 +02:00
67c3119249
genlib/fifo: add asynchronous FIFO
2013-04-25 13:30:37 +02:00
fee228a09f
fhdl/specials/memory: do not write address register for async reads
2013-04-25 13:30:05 +02:00
6c08cd67aa
graycounter: expose binary output
2013-04-25 13:11:15 +02:00
0f9df2d732
genlib: add Gray counter
2013-04-24 19:13:36 +02:00
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
8e11fcf1d0
bus/csr/SRAM: fix Module conversion errors
2013-04-14 13:55:04 +02:00
ea63389823
fhdl: support len() on all values
2013-04-14 13:50:26 +02:00
75d33a0c05
fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
2013-04-11 18:55:49 +02:00
72ef4b9683
ioo+pytholite: use new Module API
2013-04-10 23:42:46 +02:00
4c9018ea17
fhdl/visit: add TransformModule
2013-04-10 23:42:14 +02:00
746acdacd1
ioo: move to genlib
2013-04-10 22:28:53 +02:00
1cc4c8ee9f
uio: remove Trampoline (Python 3.3 provides generator delegation instead)
2013-04-10 22:15:28 +02:00
6ce856290a
flow: match record fields by position
2013-04-10 21:33:56 +02:00
df1ed32765
genlib/record/connect: add match_by_position
2013-04-10 21:33:45 +02:00
692794a21f
flow: use Module and new Record APIs
2013-04-10 19:12:42 +02:00
20bdd424c8
flow: adapt to new Record API
2013-04-01 22:15:23 +02:00
29b468529f
bus: replace simple bus module with new bidirectional Record
2013-04-01 21:54:21 +02:00
6a3c413717
New bidirectional-capable Record API
2013-04-01 21:53:33 +02:00
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
633e5e6747
fhdl/module/finalize: pass additional args to do_finalize
2013-03-30 11:29:46 +01:00
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
77a0f0a3bb
actorlib/structuring/Cast: support inversion
2013-03-25 15:54:09 +01:00
c4c4765a4e
bank/csrgen/BankArray: retain name information
2013-03-25 14:44:15 +01:00
53edc3557e
bank/description/Register: add get_size
2013-03-25 14:43:44 +01:00
3da98ea04d
genlib/record: use getattr instead of __dict__
2013-03-24 00:51:01 +01:00
1897b74f97
genlib/record: add eq
2013-03-24 00:50:33 +01:00
9d7c679b8c
genlib/fifo: simple synchronous FIFO
2013-03-22 18:18:38 +01:00
ca431fc7c2
fhdl/module: support clock domain remapping of submodules
2013-03-22 18:17:54 +01:00
a94bf3b2c5
genlib/cdc/MultiReg: output clock domain defaults to sys
2013-03-21 10:40:02 +01:00
17f2b17654
fhdl/verilog: optionally disable clock domain creation
2013-03-18 18:45:19 +01:00
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
dc55289323
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
2013-03-18 14:38:01 +01:00
e95d2f4779
fhdl/tools/value_bits_sign: support not
2013-03-18 09:52:43 +01:00
b6fe3ace05
fhdl/structure: style fix
2013-03-17 15:33:38 +01:00
2a4cc3875c
Merge pull request #6 from larsclausen/master
...
Minor improvements
2013-03-17 07:33:14 -07:00
2f522bdd9f
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
2013-03-15 19:50:24 +01:00
e2d156ef64
genlib/cdc/MultiReg: remove idomain
2013-03-15 19:49:24 +01:00
7b49fd9386
fhdl/specials: fix rename_clock_domain declarations
2013-03-15 19:47:01 +01:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
9b9bd77d00
sim: compatibility with new ClockDomain API
2013-03-15 19:15:28 +01:00
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
5adab17efa
flow/actor/filter_endpoints: deterministic order
2013-03-14 12:20:18 +01:00
fc883198ae
bank/csrgen/BankArray: create banks in sorted order
2013-03-13 23:07:44 +01:00
52d13959f2
bank/description: modify reg/mem in-place
2013-03-13 19:46:34 +01:00
dea4674922
Allow SimActors to produce/consume a constant stream of tokens
...
Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.
The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
72579a6129
Add support for negative slice indices
...
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
7e2581bf17
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 13:48:09 +01:00
12158ceadf
fhdl/tracer: recognize LOAD_DEREF opcode
2013-03-12 10:31:56 +01:00
3c75121783
fhdl/tracer: remove leading underscores from names
2013-03-11 22:21:58 +01:00
80970b203c
bus/asmibus: use implicit finalization
2013-03-11 17:11:59 +01:00
b042757187
Fix Register name conflict between Pytholite and Bank
2013-03-10 19:47:21 +01:00
f93695f60e
bank/eventmanager: use module and autoreg
2013-03-10 19:29:05 +01:00
174e8cb8d6
bus/asmibus: use fhdl.module API
2013-03-10 19:28:22 +01:00
17e0dfe120
fhdl/module: replace autofragment
2013-03-10 19:27:55 +01:00
cddbc1157d
bank/description/AutoReg: check that get_memories and get_registers are callable
2013-03-10 18:11:29 +01:00
68fe4c269c
bank/csrgen: BankArray
2013-03-10 00:45:16 +01:00
f1474420df
bank/description: AutoReg
2013-03-10 00:43:16 +01:00
d0676e2dd1
migen/fhdl/autofragment: factorize
2013-03-09 23:23:24 +01:00
d0d2df3c4b
fhdl/autofragment: remove legacy functions
2013-03-09 23:05:45 +01:00
72fb6fd6bd
fhdl/tools/flat_iteration: generalize
2013-03-09 23:03:15 +01:00
f53acb92e7
fhdl/autofragment: fix submodules
2013-03-09 21:15:38 +01:00
6da8eb906f
fhdl/autofragment: empty build_fragment by default
2013-03-09 19:10:47 +01:00
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
b75fb7f97c
csr/SRAM: support for writes with memory widths larger than bus words
2013-03-09 00:50:57 +01:00
6fa30053bf
fhdl/verilog: tristate outputs are always wire
2013-03-06 11:30:52 +01:00
9b4ca987e0
bus/csr: support memories with larger word width than the bus (read only)
2013-03-03 19:27:13 +01:00
bb5ee8d3bd
fhdl/autofragment: bugfixes + add auto_attr
2013-03-03 17:53:06 +01:00
cc8118d35c
fhdl/autofragment: FModule
2013-03-02 23:30:54 +01:00
d2491828a4
csr/SRAM: prefix page register with memory name
2013-03-01 12:06:12 +01:00
c10622f5e2
fhdl/verilog: insert reset before listing signals
2013-02-27 18:10:04 +01:00
d2cbc70190
bank/description: memprefix
2013-02-25 23:14:15 +01:00
a81781f589
fhdl/specials: allow setting memory name
2013-02-25 23:14:03 +01:00
425de02f42
uio/ioo: fix specials
2013-02-25 23:13:38 +01:00
55ab01f928
fhdl/specials/Instance: _printintbool -> verilog_printexpr
2013-02-24 13:08:01 +01:00
a878db1e3c
genlib: clock domain crossing elements
2013-02-23 19:03:35 +01:00
7c4e6c35e5
fhdl/verilog: support special lowering and overrides
2013-02-23 19:03:16 +01:00
f9acee4e68
corelogic -> genlib
2013-02-22 23:19:37 +01:00
38664d6e16
fhdl: inline synthesis directive support
2013-02-22 19:10:02 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
1b18194b1d
fhdl: TSTriple
2013-02-19 17:26:02 +01:00
dc93a231c6
fhdl: tristate support
2013-02-15 00:17:24 +01:00
63d399b6ad
fhdl/autofragment: from_attributes
2013-02-11 18:34:01 +01:00
92b67df41c
sim: default runner to Icarus Verilog
2013-02-09 17:04:53 +01:00
bd6856ba7a
flow/perftools: finish removing ActorNode
2013-02-09 17:03:48 +01:00
473fd20f8c
fhdl/structure: store clock domain name
2013-01-24 13:49:49 +01:00
3201554f76
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
2013-01-23 15:13:06 +01:00
314a6c7743
corelogic: complex arithmetic support
2013-01-05 14:18:36 +01:00
badba89686
fhdl: support nested statement lists
2013-01-05 14:18:15 +01:00
47f5fc70e4
pytholite: fix bug with constant assignment to register
2012-12-19 16:21:57 +01:00
9c65402fda
pytholite: prune unused registers
2012-12-19 16:03:05 +01:00
3fae6c8f03
Do not use super()
2012-12-18 14:54:33 +01:00
b06fbdedd6
fhdl/tools: bitreverse
2012-12-14 23:56:16 +01:00
1f350adf14
actorlib/sim/SimActor: do not drive busy low when generator yields None
2012-12-14 23:56:03 +01:00
a67f483f0f
Token: support idle_wait
2012-12-14 19:16:22 +01:00
6f99241585
Move Token to migen.flow.transactions
2012-12-14 15:55:38 +01:00
28b4d99d31
replace some forgotten is_abstract()
2012-12-12 22:36:45 +01:00
a7227d7d2b
Remove ActorNode
2012-12-12 22:20:48 +01:00
8163ed4828
Merge branch 'master' of github.com:milkymist/migen
2012-12-06 20:57:30 +01:00
483b821342
fhdl/structure: do not create Signal in Instance when parameter is int
2012-12-06 20:56:46 +01:00
280a87ea69
elsewhere: do not create interface in default param
2012-12-06 17:34:48 +01:00
62187aa23d
migen/bank: do not create interface in default param
2012-12-06 17:28:28 +01:00
c3fdf42825
bus/csr: add SRAM
2012-12-06 17:16:17 +01:00
e89c66bf14
bank/csrgen: interface -> bus
2012-12-06 17:15:34 +01:00
273d9d285b
bank/description: define reset value of read signal
2012-12-05 16:40:44 +01:00
34ce934809
actorlib/sim: drive busy high until generator is finished
2012-12-05 16:40:12 +01:00
4bcb39699b
bus/wishbone/sram: accept memories < 32 bits
2012-12-01 13:04:22 +01:00
523816982a
bus/wishbone: add SRAM
2012-12-01 12:59:09 +01:00
adb1565d7a
pytholite: fix bit width of selection signal
2012-11-30 17:07:32 +01:00
cfb23c442f
pytholite: support signed registers
2012-11-30 17:07:12 +01:00
7093939309
corelogic/roundrobin: fix request width (again)
2012-11-29 23:47:51 +01:00
31c722f993
corelogic/roundrobin: fix request width
2012-11-29 23:47:08 +01:00
70e97e0456
Fix various errors from new bitwidth/signedness system conversion
2012-11-29 23:36:55 +01:00
261166d92b
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
...
See http://jandecaluwe.com/hdldesign/counting.html
2012-11-29 22:59:54 +01:00
55d143a454
fhdl/structure: add unary minus
2012-11-29 22:52:57 +01:00
d8e478efee
Replace Signal(bits_for(... with Signal(max=...
2012-11-29 21:53:36 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
6eebfce44a
Refactor Case
2012-11-29 01:11:15 +01:00
070652cc39
pytholite/reg: use source id in dictionary
2012-11-29 00:09:35 +01:00
fee22a4631
Remove Constant
2012-11-28 23:18:43 +01:00
59831e0485
fhdl/structure: improved bits_for function
2012-11-28 18:39:44 +01:00
11b1e53224
visit/NodeTransformer: copy most nodes
2012-11-28 17:50:55 +01:00
a2bcbfdf8f
fhdl/tools: use NodeTransformer to lower arrays
2012-11-28 17:46:15 +01:00
3bc15024ac
fhdl/tools: use NodeVisitor
2012-11-26 21:40:23 +01:00
e3a983d731
Remove unroll
2012-11-26 20:07:48 +01:00
1460f069f6
fhdl/structure: remove deprecated MemoryPort
2012-11-26 19:36:43 +01:00
5183774ec8
bus/wishbone2asmi: do not use MemoryPort
2012-11-26 19:14:59 +01:00
fc85ca53ad
actorlib/spi: do not use MemoryPort
2012-11-26 18:27:59 +01:00
dac0d11e52
actorlib/sim: Dumper
2012-11-24 00:00:07 +01:00
27d87c9412
fhdl/structure: disable we_granularity when larger than width
2012-11-23 23:08:12 +01:00
d2c61e6a90
sim/generic/multiread: do not return spurious items
2012-11-23 23:07:25 +01:00
74721b206f
pytholite: fix import of _Slice
2012-11-23 21:20:18 +01:00
95122bb778
pytholite/io: support memory
2012-11-23 20:36:09 +01:00
f42683b71e
fhdl/structure/Memory: fix we width
2012-11-23 19:21:52 +01:00
0f6215a13a
fhdl/structure: add Memory.get_port API
2012-11-23 19:17:49 +01:00
9d3e218863
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
2012-11-23 18:38:03 +01:00
3971600917
fhdl/structure: use sets for memories and instance collections
2012-11-23 17:20:08 +01:00
f3efd74dfd
uio: support memories
2012-11-23 16:23:24 +01:00
ab31b4d99c
bus: memory initiator
2012-11-23 16:22:50 +01:00
0b7dd7bdce
pytholite/io: fix Wishbone writes + support sel attribute
2012-11-23 13:40:46 +01:00
4c216d8f11
pytholite/io: support Wishbone reads
2012-11-23 13:09:55 +01:00
0b24a2ff36
pytholite/io: support Wishbone writes
2012-11-23 12:41:50 +01:00
f098c5c695
pytholite/compiler: pass keyword arguments to gen_io
2012-11-23 12:40:57 +01:00
51e2e6ecd0
fhdl/verilog: remove empty cases
2012-11-18 16:32:51 +01:00
89643bc434
sim/ipc/Message: convert values
2012-11-17 23:19:40 +01:00
e92af9de59
pytholite/transel: use python3-compatible comparison methods
2012-11-17 23:16:07 +01:00
b6b4c5d70e
uio/ioo: fix UnifiedIOSimulation
2012-11-17 22:25:42 +01:00
1cabcb3c3f
uio: support generator trampolining in simulation
2012-11-17 19:59:22 +01:00
be68ecfc72
uio: add simulation I/O object
2012-11-17 19:55:33 +01:00
7add4c6f3c
uio: unified I/O object
2012-11-17 19:54:50 +01:00
d10df1a8ab
actorlib/sim: swap TokenExchanger parameters
2012-11-17 19:46:28 +01:00
d4baac6c0f
bus/csr: allow specifying existing interface
2012-11-17 19:44:25 +01:00
86090e1cbd
bus/asmibus: swap port position to be consistent with wishbone API
2012-11-17 19:42:39 +01:00
ece786d6aa
bus/wishbone: allow specifying existing interface
2012-11-17 19:42:06 +01:00
d0d4c48098
bus/transactions: add busname parameter
2012-11-17 19:36:08 +01:00
897a2e3f9c
actorlib/sim: split TokenExchanger
2012-11-17 14:15:51 +01:00
eb156af20c
pytholite/io: support token pull
2012-11-16 23:48:41 +01:00
dd9a102a78
pytholite/io: support token push
2012-11-16 19:24:45 +01:00
bf5ce8dc20
pytholite: move expression and register handling to separate modules
2012-11-11 23:48:23 +01:00
f59fd69e34
pytholite/compiler: recognize composite I/O pattern
2012-11-11 18:03:16 +01:00
0b5652bb79
pytholite/compiler: visit_assign_special
2012-11-11 15:52:06 +01:00
687d18a150
pytholite: move FSM management to separate module
2012-11-11 14:30:25 +01:00
409a5570e4
pytholite/compiler: refactor visit_block
2012-11-11 14:17:52 +01:00
fb63698ef4
pytholite/compiler: clean up visit_statement
2012-11-10 23:30:14 +01:00
6ebd1e4503
pytholite: forward 'yield call' statements to io module
2012-11-10 22:59:14 +01:00
48acb1bcfd
pytholite: introduce io module
2012-11-10 21:51:19 +01:00
6776f06a42
pytholite/compiler: support bitslice
2012-11-10 18:04:05 +01:00
37f113c3ea
pytholite/compiler: support range(constants) in for loops
2012-11-10 15:26:13 +01:00
370bab1190
pytholite/compiler: cleanup print statements
2012-11-10 15:10:57 +01:00
39c7dc7d63
pytholite/compiler: support for loops (iterating on lists only)
2012-11-10 15:02:55 +01:00
93db3edd00
pytholite/compiler: support while loops
2012-11-10 14:37:33 +01:00
a901ef46ab
Revert "pytholite/compiler: SymbolStack"
...
This reverts commit f57da497b2
2012-11-10 12:09:45 +01:00
f57da497b2
pytholite/compiler: SymbolStack
2012-11-09 23:02:16 +01:00
5750c7c07e
pytholite/compiler: improve naming of selection signals
2012-11-09 20:19:22 +01:00
4921a34616
pytholite/compiler: fix handling of constants
2012-11-09 20:17:57 +01:00
26cf1b8840
fhdl: make constants hashable
2012-11-09 20:17:43 +01:00
c1b8492b61
pytholite/compiler: go to next state
2012-11-09 20:12:15 +01:00
e1075a962c
pytholite/compiler: support if statements
2012-11-09 19:37:52 +01:00
92ff5095da
pytholite/compiler: support comparisons in expressions
2012-11-09 18:41:32 +01:00
a645e0b24e
pytholite/compiler: create FSM
2012-11-09 17:37:42 +01:00
7744655ef2
fhdl/visit: add missing self
2012-11-09 17:37:24 +01:00
13af0ce556
fhdl: visit module (untested)
2012-11-09 16:00:11 +01:00
9c182c47d1
pytholith: add register muxes
2012-11-08 21:49:20 +01:00
18758d87f6
pytholite: do not use ast.NodeVisitor
2012-11-06 13:52:19 +01:00
Sebastien Bourdeauducq
Florent Kermarrec
Lars-Peter Clausen