96527b5a3a
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
2018-11-30 23:12:30 +01:00
1c8c2426b9
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-27 17:45:07 +01:00
8887fc24c4
build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
...
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
2018-11-27 17:42:39 +01:00
cc4ba65659
Merge pull request #130 from jfng/master
...
litex_sim: add --trace argument
2018-11-27 17:35:03 +01:00
ec46beeb47
targets/ulx3s, versa_ecp5: use ECP5PLL
2018-11-27 17:31:53 +01:00
71398e0155
litex_sim: add --trace argument
2018-11-27 17:26:32 +01:00
18048eb454
cores/clock: test and fix ECP5PLL, phase still not implemented.
2018-11-27 17:24:22 +01:00
20dd95c541
boards/platforms/ulx3s: add gpios 0-3
2018-11-27 14:15:35 +01:00
909cff1940
bios/sdram: flush l2 cache only when present
2018-11-26 18:37:45 +01:00
2ad83778bf
bios: allow testing main_ram at init when using an external controller
2018-11-26 15:21:00 +01:00
cdfe0454bb
build/microsemi/libero_soc: small cleanup
2018-11-26 11:35:06 +01:00
4592e3235b
Merge pull request #128 from mithro/small-fix
...
Two small fixes
2018-11-26 09:48:10 +01:00
4f565c5179
stream.Endpoint: Pass extra arguments to superclass.
2018-11-25 12:57:11 -08:00
3b9e4c4df6
wishbone.SRAM: Support non-32bit wishbone widths.
2018-11-25 12:56:37 -08:00
515c06219a
cores/clock: add ECP5PLL
2018-11-24 00:47:38 +01:00
7623b5dd96
soc/interconnect/stream/gearbox: inverse bit order
2018-11-23 18:34:24 +01:00
d32e393033
soc/cores/spi_flash: add missing endianness parameter
2018-11-23 18:33:53 +01:00
c954943e02
platforms/avalanche: add IOStandard on ddram pins
2018-11-23 12:47:45 +01:00
09a1cda943
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
2018-11-23 09:30:13 +01:00
a98e1ad689
build/microsemi/libero_soc: add additional_timing_constraints
2018-11-23 09:04:42 +01:00
b166882308
build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper
2018-11-23 08:26:31 +01:00
9df75d7d63
platforms/avalanche: add package/speed to platform.device
2018-11-23 08:24:29 +01:00
953b1f70df
build/microsemi/libero_soc: remove previous impl directory if exists
2018-11-23 08:11:57 +01:00
18d513a146
build/microsemi/libero_soc: give better names to pdc files: io/fp
2018-11-23 08:03:55 +01:00
4f092dbe35
build/microsemi/libero_soc: add additional_constraints
2018-11-22 18:40:19 +01:00
206c9a4697
platforms/avalanche: fix ddram dq7
2018-11-22 18:13:33 +01:00
f003407776
build/microsemi/libero_soc: add {} around port name.
2018-11-22 17:37:03 +01:00
beeca856e5
utils/litex_read_verilog: fix generated indent on instance
2018-11-22 17:33:46 +01:00
1fe7d09fb5
soc/integration/soc_core: add csr_map_update function
2018-11-21 08:39:52 +01:00
89c702187a
libbase/crt0-picorv32: Add support for .data sections.
2018-11-21 00:13:13 -05:00
80bdae0e55
build/sim/verilator: add trace parameter to enable tracer
2018-11-20 18:54:22 +01:00
7359a99bf9
soc_core: convert cpu_type="None" string to None
2018-11-20 17:45:11 +01:00
5805d63013
build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route
2018-11-19 16:36:30 +01:00
85f7666207
build/microsemi/common: add async reset synchronizer (using DFN1P0)
2018-11-19 15:35:59 +01:00
e3c6bd5846
build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools
2018-11-19 12:50:07 +01:00
4c966114f8
build/microsemi/libero_soc: add timing constraints support
2018-11-19 09:40:16 +01:00
60faae490a
boards/platforms/avalanche: fix swapped serial pins
2018-11-19 08:45:55 +01:00
52396add5d
boards/platforms/avalanche: rename rst to rst_n (active low reset)
2018-11-19 08:14:46 +01:00
8e07e1a099
build/microsemi/libero_soc: associate .pdc to place and route tool.
...
For constraint to be applied, we also to associate them with the tool that will use it.
2018-11-19 08:07:36 +01:00
a5ed42ec68
soc/interconnect/stream: add Gearbox
2018-11-17 17:29:45 +01:00
a25645afa6
utils: add litex_read_verilog utility
...
generate Migen's modules from verilog files
2018-11-16 16:09:44 +01:00
a538d36268
create utils directory and move the litex utils to it
2018-11-16 14:37:19 +01:00
45ec78e93a
build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.
2018-11-16 12:19:03 +01:00
4cb6583b4e
build: add microsemi template for polarfire fpgas support
2018-11-15 18:21:41 +01:00
b1425ba85f
lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.
...
Fixes the following error;
```
make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/ice40_hx8k_b_evn_base_lm32.lite/software/stub'
Traceback (most recent call last):
File "./make.py", line 164, in <module>
main()
File "./make.py", line 148, in main
vns = builder.build(**dict(args.build_option))
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
toolchain_path=toolchain_path, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
return self.platform.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
**kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
create_clock_domains=False, **kwargs)
TypeError: convert() got an unexpected keyword argument 'toolchain_path'
```
2018-11-13 16:18:08 -08:00
af25bf2bc0
soc_core: check for cpu before checking interrupt
2018-11-13 16:17:49 +01:00
b4bdf2a023
cores/clock/S7: just reset the generated clock, not the PLL/MMCM
2018-11-13 14:47:04 +01:00
86fd945bc3
bios/main: fix typo on mor1kx
2018-11-13 11:16:06 +01:00
af95028574
cpu/mor1kx: use clang only for linux variant
2018-11-13 11:09:39 +01:00
04523bc28a
xilinx/vivado: fix migen merge
2018-11-12 16:31:51 +01:00
f3343c46fc
platforms: remove versaecp55g_sdram
2018-11-12 12:45:33 +01:00
58414b1819
build/xilinx/vivado: merge migen change
2018-11-12 12:00:30 +01:00
a7f17f9915
build: use default toolchain_path on all backend when passed value is None
2018-11-12 11:48:30 +01:00
eed1d5cb2e
generic_platform: use set for sources
2018-11-12 11:47:39 +01:00
665fff8390
build: merge more migen changes
2018-11-12 11:26:35 +01:00
70f48775de
platforms/versa_ecp5: import migen changes
2018-11-12 10:52:28 +01:00
4ff241b981
targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis
2018-11-12 10:47:33 +01:00
cb86728ad1
build/lattice: import changes from migen
2018-11-12 10:46:49 +01:00
8574c62f75
targets/versa_ecp5: increase sys_clk_freq to 50MHz
2018-11-12 10:12:10 +01:00
a752dafb14
targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
2018-11-12 09:45:59 +01:00
87c7d23d16
targets/ulx3s: for now revert to 25MHz clock/no pll
2018-11-12 09:44:32 +01:00
d1baae36a6
platforms/versa_ecp5: add ecp5 soc hat ios
2018-11-12 09:43:31 +01:00
b3bf1c9517
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-12 08:12:07 +01:00
1be6762dfe
Merge pull request #125 from daveshah1/trellis_sdram
...
ecp5 soc hat wip
2018-11-12 08:11:57 +01:00
425ad755ec
plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5
2018-11-12 08:06:22 +01:00
c57aa545ca
targets/ulx3s: get memtest working by disabling sdram refresh
...
Will need to be fixed...
2018-11-09 18:40:14 +01:00
9a6447172a
soc/integration/soc_sdram: allow using axi interface with litedram
2018-11-09 15:42:34 +01:00
416bdb6483
boards/platforms: add avalanche polarfire board ios definition
2018-11-08 18:24:12 +01:00
f08f80bed1
working on Versa-5G dram
...
Signed-off-by: David Shah <dave@ds0.me>
2018-11-06 14:39:25 +00:00
fc0d5c3963
bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients
2018-11-05 18:44:28 +01:00
09f962fdc4
target/kcu105: add reset button
2018-11-05 18:41:49 +01:00
169f8d8cb5
boards/platforms/kcu105: fix sdram/dq pin swap
2018-11-05 17:01:42 +01:00
d78d5d3e7f
Debugging ULX3S SDRAM
...
Signed-off-by: David Shah <dave@ds0.me>
2018-11-05 11:54:22 +00:00
2624ba48c2
bios/sdram: replace DDR3_MR1 constant with DDRX_MR1
2018-11-05 10:47:25 +01:00
6be74aa17f
boards/targets: add kcu105
2018-11-05 10:44:50 +01:00
93c623251b
Merge pull request #122 from daveshah1/trellis_ulx3s
...
Switch Trellis build to use LPF constraints; working on ULX3S
2018-11-02 19:59:23 +01:00
dcbe759b64
build/sim/verilator: don't use --threads when $(THREADS) is unset
2018-11-02 14:22:44 +01:00
6f38213acc
boards/platforms/kc705: add user_sma_mgt_refclk
2018-11-01 10:52:01 +01:00
4cdd679908
Merge pull request #123 from cr1901/prv32-min
...
PicoRV32 Enhancements
2018-11-01 10:45:32 +01:00
e56f71824d
libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time).
2018-11-01 05:02:04 -04:00
f32121e0e1
cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector.
2018-11-01 02:23:01 -04:00
77389d27b5
libbase/crt0-picorv32: Ensure BSS is cleared on boot.
2018-11-01 02:18:03 -04:00
f7969b660a
cores/clock: add with_reset parameter (default to True)
...
In some cases we want to generate the reset externally.
2018-10-31 16:23:23 +01:00
0729b3a059
ulx3s: Connect SDRAM clock
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 13:29:35 +00:00
8404434956
Fix Trellis build; ULX3S demo boots to BIOS
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 12:27:05 +00:00
0c1d8d5993
trellis: Switch to using LPF for constraints
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 11:43:39 +00:00
445c49400f
boards/platforms/kcu105: add sfp_tx/rx definition
2018-10-31 10:48:48 +01:00
f69bd877b9
cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations).
2018-10-30 06:00:45 -04:00
d05fe673a0
cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs.
2018-10-30 06:00:45 -04:00
e9d4c882ba
build/lattice/prjtrellis: fix default toolchain_path
2018-10-30 10:28:12 +01:00
468780c045
soc/cores/spi_flash: add endianness parameter
2018-10-30 10:19:21 +01:00
6f3131e259
soc/interconnect/stream_packet: use reverse_bytes from litex.gen
2018-10-30 10:16:55 +01:00
b796853893
gen: add common with reverse_bits/reverse_bytes functions
2018-10-30 10:15:29 +01:00
71fc34d7b6
boards/targets/ulx3s: reduce l2_size
2018-10-30 10:14:48 +01:00
75d073f394
build/lattice/prjtrellis: fix typo
2018-10-30 10:14:30 +01:00
6048a5291c
build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts.
...
nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
2018-10-30 08:54:30 +01:00
2243f628f7
build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl
2018-10-30 08:47:12 +01:00
f3111e1142
Update vivado.py
...
Fix regression which caused Vivado to not be run at all.
2018-10-29 23:43:32 -04:00
98fa899692
boards/targets: add ulx3s
2018-10-29 19:24:28 +01:00
7d779473f1
boards/platforms: add ulx3s
2018-10-29 19:23:59 +01:00
d9dcad33a4
build/lattice/prjtrellis: add inout support
2018-10-29 19:23:21 +01:00
091ad799b0
build/lattice/common: add tristate support
2018-10-29 19:22:04 +01:00
23acefb14e
boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed
...
simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
2018-10-29 16:02:25 +01:00
1097f82283
build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis"
2018-10-29 15:58:54 +01:00
52917a710e
boards/targets/simple: add gateware-toolchain parameter
2018-10-29 15:56:46 +01:00
d84083f642
boards/platforms/versaecp55g: use ftdi serial pins
2018-10-29 15:39:51 +01:00
c05b9ef2ad
build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support
2018-10-29 13:26:29 +01:00
a8f819fec2
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-10-29 11:48:10 +01:00
4eb314a252
boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :)
2018-10-29 11:46:03 +01:00
27ec2a59e2
build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO
...
PrjTrellis does not yet have constraint files support, constraints are set
with signal attributes and specific TRELLIS_IO instances are requested. This
iowrapper does this work for us automatically.
Remove this code and replace with a constraint file generation code when
PrjTrellis will have constraint file support.
2018-10-29 11:44:31 +01:00
c506c9752c
gen/fhdl/verilog: set direction to io signals
2018-10-29 11:41:04 +01:00
1cac079efa
litex/build: Always run Vivado.
...
When using Yosys for synthesis, still need Vivado for place and route.
2018-10-29 02:04:44 -07:00
49dab3b448
build/lattice/prjtrellis: simplify code, remove some workarounds
2018-10-29 09:40:35 +01:00
a73d9d96b1
build/xilinx/vivado: fix merge issue
2018-10-29 08:26:13 +01:00
3e189379f9
boards/targets: add versa ecp55g prjtrellis target (experimental)
2018-10-28 19:34:17 +01:00
a69197d2db
build/lattice: add initial prjtrellis support
2018-10-28 17:51:16 +01:00
397e3c7682
build/lattice/diamond: use bash on linux
2018-10-28 15:40:52 +01:00
d029cd243d
build/lattice: improve special_overrides names (vendor_family)
2018-10-28 15:40:10 +01:00
b200ce9983
Merge branch 'master' into xilinx+yosys
2018-10-28 14:59:03 +01:00
ba0dd5728e
uart: Enable buffering the FIFO.
...
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
2018-10-27 16:04:58 -07:00
e3935b481e
build/sim/verilator: don't use THEADS parameters when threads=1
...
Allow using old (non multi-threaded) version of Verilator
2018-10-27 11:06:34 +02:00
a44181e716
soc_sdram: update litedram
2018-10-19 18:37:55 +02:00
ab6a530a24
bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode
2018-10-18 13:42:51 +02:00
b8be9545cc
build/xilinx/vivado: enable xpm libraries
2018-10-18 09:25:34 +02:00
ab8cf3e345
soc/cores/clock: add margin parameter to create_clkout (default = 1%)
2018-10-16 14:57:37 +02:00
915c2f417a
bios/sdram: improve write/read leveling
...
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
2018-10-10 10:42:56 +02:00
deffa60324
platforms/kc705: add ddram_dual_rank
2018-10-09 15:39:03 +02:00
10624c26da
bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r)
2018-10-09 10:06:51 +02:00
9f083e9bd3
Merge pull request #116 from stffrdhrn/sim-uart
...
sim: serial: Send '\r\n' instead of just '\n'
2018-10-09 07:32:31 +02:00
8877dba7e9
sim: serial: Send '\r\n' instead of just '\n'
...
This fixes an issue when running with the HDMI2USB firmware which
expects \r\n to come from the UART. Since the verilator adapter
is just sending \n commands cannot be executed.
Also, one minor whitespace cleanup. (could remove if needed)
2018-10-09 11:18:11 +09:00
d187921500
cpu_interface: fix select_triple when only one specified
2018-10-08 17:01:04 +02:00
3b27d2ae89
soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains
2018-10-06 21:32:38 +02:00
168b07b9a2
soc_core: add csr range check
2018-10-06 20:55:16 +02:00
ace976242e
build.xilinx: Convert attributes to something Yosys understands.
...
Convert keep, dont_touch and async_reg to something Yosys understands.
Write out an EDIF file with the attributes so that Vivado can use them.
(Requires Yosys with commit
115ca57647
2018-10-05 12:48:30 -07:00
6febb6826c
Merge pull request #112 from cr1901/8k-b-evn
...
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-04 21:12:33 +02:00
ff6de429f0
Fix help for or1k builds
...
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx. Fix the message to properly represent what
needs to be passed to the commandline.
2018-10-04 23:09:49 +09:00
dafdb8df72
Fix compiler warnings from GCC 8.1
...
Fix these 2 warnings:
litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
[-Wstringop-truncation]
strncpy(last_err, s, ERR_MAX_SIZE);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In function 'set_last_error',
litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
static char emerg_getc()
2018-10-04 23:07:48 +09:00
2be5205463
build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen)
2018-10-04 08:17:44 +02:00
78414c0588
xilinx/viviado: Allow yosys for synthesis.
2018-10-03 21:58:03 -07:00
d13ac3b3d5
cpu/mor1kx: Adding verilog include directory.
2018-10-03 21:57:24 -07:00
9a44f08a3e
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-03 20:53:33 -04:00
dc7cd75757
build.xilinx: Run `phys_opt_design` and generate timing report.
...
Makes the flow more similar to migen.
2018-10-03 16:02:43 -07:00
948527b0fe
cores/cpu: revert vexriscv (it seems there is a regression in last version)
2018-10-02 12:30:11 +02:00
15bca4535f
targets/sim: fix integrated_main_ram_size when with_sdram
2018-10-02 11:31:08 +02:00
6e327cda26
bios/sdram: rewrite write_leveling (simplify and improve robustness)
2018-10-01 15:38:19 +02:00
975be6686f
platforms/genesys2: add eth clock timing constraint
2018-10-01 15:37:34 +02:00
934a5da559
soc/cores/clock: add expose_drp on S7PLL/S7MMCM
2018-09-28 13:02:10 +02:00
9097573e71
Merge pull request #109 from cr1901/xip-improve
...
Improve XIP Support
2018-09-25 15:32:04 +02:00
082b03016c
targets: use new clock abstraction on all 7-series targets
2018-09-25 09:31:30 +02:00
74e74dc0e7
soc/cores/clock: different clkin_freq_range for pll and mmcm
2018-09-25 09:09:47 +02:00
91d8cc2d6a
soc/cores/clock: different vco_freq_range for pll and mmcm
2018-09-25 09:04:38 +02:00
6cd954940c
soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG)
2018-09-25 08:36:18 +02:00
912ca3236b
soc/cores/clock: create specific S7IDELAYCTRL module
2018-09-24 23:22:59 +02:00
baec87f530
soc/cores/clock: add S7MMCM support
2018-09-24 23:20:12 +02:00
ef40524924
soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest)
2018-09-24 22:58:23 +02:00
5415b521be
targets/arty: use new clock abstraction module (compile, untested on board)
2018-09-24 22:49:30 +02:00
63fc395006
soc/cores: init clock abstraction module
2018-09-24 22:49:01 +02:00
0ff6d58605
Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section).
2018-09-24 14:48:54 -04:00
8106008184
integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM.
2018-09-24 12:28:45 -04:00
db90619067
integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX).
2018-09-24 11:04:57 -04:00
70a32ed86f
sim/verilator: add multithread support (default=1)
2018-09-24 12:43:29 +02:00
7f0d116d88
soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now)
2018-09-24 10:59:32 +02:00
22febe9582
boards/targets: uniformize things between targets
2018-09-24 10:58:10 +02:00
01b025aafd
soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication
2018-09-24 08:01:32 +02:00
b528a005a0
cores/cpu: add software informations to cpu and simplify cpu_interface
2018-09-24 07:51:41 +02:00
2d785cb0ac
boards/plarforms: fix issues found while testing simple design on all platforms
2018-09-24 02:03:30 +02:00
c88029d330
soc_core: add uart-stub argument
2018-09-24 02:01:15 +02:00
e9ed737037
ease RemoteClient import
2018-09-23 10:23:00 +02:00
6f25a0d8a1
csr: use external csr_readl()/csr_writel() if present
...
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.
With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:55:09 +02:00
9a252e367c
csr: use readl()/writel() accessors for accessing mmio
...
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:54:46 +02:00
9d4da737ff
libbase/crt0-lm32.S: Add provisions for loading .data from flash.
...
:100644 100644 e0cd7153
2018-09-21 10:23:14 -04:00
15e584d880
targets/sim: generate analyzer.csv
2018-09-20 12:20:48 +02:00
cde72603a1
targets/sim: generate csr.csv
2018-09-20 11:17:18 +02:00
f62df5023f
targets/sim: add rom-init
2018-09-20 01:14:00 +02:00
1dbf591e78
targets/sim: add ram-init param to allow initializing ram from file (faster than tftp)
2018-09-20 01:00:13 +02:00
9893c2460a
integration/soc_core: add get_mem_data function to read memory content from file
2018-09-20 00:46:06 +02:00
a3eb2e403b
soc/intergration/builder: fix when no sdram
2018-09-19 23:59:42 +02:00
934b08ede8
targets/sim: merge in a single class and ease configuration
2018-09-19 23:59:15 +02:00
bd42b18856
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-09-19 19:21:14 +02:00
3e77ae788f
targets: replace MiniSoC with EthernetSoC
2018-09-19 19:19:50 +02:00
badd992469
targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server)
2018-09-19 19:17:32 +02:00
537b0e9058
Merge pull request #101 from cr1901/icestorm-migen-pull
...
Icestorm Improvements
2018-09-18 08:19:09 +02:00
5c83c88128
Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run.
2018-09-17 21:17:24 -04:00
9c6f76f18c
bios/sdram: mode sdhw()
2018-09-13 06:33:54 +02:00
a44bedd557
bios/sdram: add missing #ifdef
2018-09-13 06:30:37 +02:00
0e68daebf3
targets: self.pll_sys --> pll_sys
2018-09-13 05:31:35 +02:00
1468b9f3ba
bios/sdram: show all read scans when failing.
2018-09-13 05:26:51 +02:00
07e4c183cd
cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise)
2018-09-12 06:02:23 +02:00
df3f003ecd
soc_sdram: update with litedram
2018-09-09 02:13:00 +02:00
bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram
...
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
2018-09-08 03:55:23 +02:00
bd70ba278b
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region.
2018-09-07 21:49:24 -04:00
69716852f1
Merge pull request #100 from cr1901/tinyprog-fix
...
lattice/programmer: Use --program-image option with tinyprog if addre…
2018-09-08 03:48:04 +02:00
12a8944711
soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...)
2018-09-07 11:51:17 +02:00
2b786065b1
targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen
2018-09-07 10:37:15 +02:00
c812321a93
lattice/programmer: Use --program-image option with tinyprog if address is given.
2018-09-07 04:05:49 -04:00
26963d62fa
libnet/microudp: (WIP) fix endianness issues
2018-09-06 18:43:55 +02:00
22c0131324
fix typo and unused include
2018-09-06 17:07:14 +02:00
fb24ac0ecc
cpu/minerva: add workaround on import until code is released
2018-09-06 16:40:30 +02:00
8f377307d8
add Minerva support
2018-09-05 22:33:04 +02:00
1944289e64
litex_server: update pcie and remove bar_size parameter
2018-09-05 13:01:51 +02:00
Florent Kermarrec
Jean-François Nguyen
Tim 'mithro' Ansell
William D. Jones
David Shah
Stafford Horne
Sean Cross
Jean-François Nguyen
Jean-François Nguyen