935e4effd2
interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
2020-02-26 15:13:29 +01:00
d324c54eee
integration/soc: -x on soc.py
2020-02-26 14:43:01 +01:00
ee27a9e534
soc/cores/bitbang: fix missing self.comb on miso.
2020-02-25 15:57:14 +01:00
e2aebb427e
software: disable LTO with LM32 (not supported by old GCC versions easily available).
2020-02-25 15:32:36 +01:00
718a65c3c9
software: enable link time optimization (LTO)
...
Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
2020-02-24 16:12:21 +01:00
7a87d4e262
Fix ECP5PLL VCO frequency range
...
See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
2020-02-24 14:39:59 +01:00
0c7e0bf025
integration/soc: improve presentation of SoCLocHandler's locations.
2020-02-24 13:37:38 +01:00
0042a02807
interconnect/axi: remove bus_name on connect_to_pads
2020-02-24 13:24:32 +01:00
a3584147a5
litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:52 +01:00
d86db6f12b
litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:20 +01:00
0083e0978b
Merge pull request #396 from antmicro/external-wb
...
Add a script that allows to generate standalone cores
2020-02-24 10:01:16 +01:00
173117ad4b
Add 'volatile' qualifier to new CSR accessors
...
Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.
Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.
No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
2020-02-21 14:10:13 -05:00
79a14001b0
axi: add to_pads method
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2020-02-21 12:22:18 +01:00
e0bcb57d3d
wishbone: add extracting module signals to the top
2020-02-21 11:20:32 +01:00
53ee9a5e05
cpu/blackparrot: first cleanup pass
2020-02-20 18:50:13 +01:00
f3829cf081
integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.
2020-02-20 16:16:36 +01:00
d4d2b7f7c6
bios: add litesdcard test routines to boot menu
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This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
774a55a2aa
soc_core: fix missing init on main_ram
2020-02-19 14:59:58 +01:00
5d580ca4e1
Merge pull request #389 from antmicro/linux_flash_offsets
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bios/boot: allow to customize flash offsets of Linux images
2020-02-18 17:54:13 +01:00
00895518e5
cores/cpu: use standard+debug variant when only debug is specified.
2020-02-18 16:59:55 +01:00
659c244a0b
bios/boot: allow to customize flash offsets of Linux images
2020-02-18 13:38:09 +01:00
ae45be4773
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
2020-02-18 10:15:01 +01:00
9baa3ad5bb
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
2020-02-18 09:13:32 +01:00
854e7cc908
integration/soc: improve Region logger
2020-02-18 08:27:59 +01:00
9cb8f68e82
bios/boot: update and fix flashboot, improve verbosity
2020-02-17 19:21:54 +01:00
6ed0f445b6
soc: increase supporteds address_width/paging
2020-02-17 08:36:40 +01:00
5b3808cb81
soc_core: expose CSR paging
2020-02-17 08:34:10 +01:00
0497f3ca71
soc/csr_bus: improve CSR paging genericity
2020-02-17 08:28:56 +01:00
67e8a042f8
integration/soc: add configurable CSR Paging
2020-02-16 12:32:05 +01:00
6576470179
soc_core: add back identifier
2020-02-15 19:04:47 +01:00
18a9d4ff2f
interconnect/stream: cleanup imports/idents
2020-02-14 08:08:19 +01:00
e4712ff7f3
soc_core: fix cpu_variant renaming regression
2020-02-13 08:34:39 +01:00
baa29f1b03
doc: fix regression with new irq manager
...
Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts. This has been subsumed
into a more general `irq` object that manages the interrupts.
Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.
This fixes #385 .
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-13 08:32:44 +08:00
1620f9c5b0
soc/CSR: show alignment in report and add info when updating.
2020-02-12 21:55:30 +01:00
5b34f4cd34
soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
2020-02-12 21:25:52 +01:00
2f69f607e3
integration/soc: fix refactoring issues
2020-02-12 18:16:38 +01:00
1d6ce66bf7
soc/integration/builder: update copyright, align arguments
2020-02-12 16:43:11 +01:00
b56545791c
Unify output directory handling in builder
2020-02-12 15:47:16 +01:00
e9c665a539
soc_core/soc_sdram: add disclaimer
2020-02-11 18:28:05 +01:00
5558865cbf
soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region
2020-02-11 18:21:41 +01:00
1b5caf56fb
soc: fix busword typo
2020-02-11 17:57:05 +01:00
240a55bace
Merge branch 'master' into new_soc
2020-02-11 17:22:06 +01:00
d5ad1d56f2
soc/integration: move mem_decoder to soc_core
2020-02-11 17:19:22 +01:00
0a737cb624
soc/integration/common: simplify get_version
2020-02-11 17:16:24 +01:00
399b65fa17
soc/add_uart: fix bridge
2020-02-11 16:55:37 +01:00
160c55d1d4
soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
2020-02-11 16:44:25 +01:00
b2c66b1efd
soc: avoid double definition of main_ram
2020-02-11 16:39:37 +01:00
5f9946085b
soc: improve log colors on error reporting
2020-02-11 16:24:57 +01:00
b22d2ca02b
soc: add linker regions management
2020-02-11 15:28:02 +01:00
abc31a92c6
soc: improve log presentation/colors
2020-02-11 14:50:16 +01:00
Florent Kermarrec
Tim 'mithro' Ansell
Xiretza
Gabriel Somlo
Karol Gugala
Jan Kowalewski
Mateusz Holenko
Sean Cross