3bd14f541e
platforms/xilinx_zc706: added missing i2c node
2024-04-05 10:47:33 +02:00
d2d38794f4
Merge pull request #579 from hansfbaier/qmtech-altera-sdram-attrs
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Better Altera SDRAM IO properties for more speed
2024-04-04 10:56:37 +02:00
cb84141cec
Merge pull request #578 from hansfbaier/qmtech-optional-core-resources
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qmtech core boards: make core resources optional
2024-04-04 10:56:02 +02:00
e4c4391a9c
colorlight_i9plus: Switch to OpenFPGALoader for loading bitstreams.
2024-04-02 08:44:25 +02:00
7d89aa0fe9
qmtech altera boards: sdram io properties for more speed
2024-03-30 20:43:41 +07:00
af1cdc4ed9
qmtech core boards: make core resources optional
2024-03-30 09:59:22 +07:00
4ca13943eb
qmtech_wukong: Change --board-version to --revision as on other boards.
2024-03-28 15:30:57 +01:00
4df2ab98e7
qmtech_wukong: Add V3 support and minor cleanups.
2024-03-28 15:23:58 +01:00
9235468ce1
qmtech_wukong: Minor cleanups.
2024-03-28 14:50:03 +01:00
57a9970257
xilinx_zc706: ADD DDR3 support in target and update/fix IOs definition in platform (Untested on hardware).
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- Use/Mimic IO standards from KC705.
- Keep it to single rank for now (but add dual rank IOs in comments).
- Add DCI cascade property.
- Add sys4x and idelay clocking.
- Add LiteDRAM PHY/Core support.
2024-03-27 08:51:30 +01:00
ded90748ee
xilinx_kc705: Minor Cleanup/Update.
2024-03-27 08:48:05 +01:00
d582515af4
Merge pull request #576 from trabucayre/zc706_next
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xilinx_zc706: Add missing peripherals/resources.
2024-03-27 08:26:44 +01:00
e51b9eb392
sipeed_tang_mega_138k_pro: Fix previous commit.
2024-03-26 22:05:20 +01:00
40c7a63e53
Finish tang_mega_138k renaming to tang_mega_138k_pro.
2024-03-26 21:58:02 +01:00
6ec1cfe401
xilinx_zc706: add missing peripherals/resources
2024-03-26 21:57:21 +01:00
fdd4edbd1a
xilinx_zc706: Review/Minor changes.
2024-03-26 21:35:10 +01:00
6b35c47e8b
xilinx_zc706: new Xilinx/AMD Zynq7000 based board
2024-03-26 20:49:54 +01:00
8f7ba0ae28
Merge pull request #573 from Xilokar/master
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Fix sqrl_acorn proxy bitstream for cle-101
2024-03-26 12:36:56 +01:00
02ab7ee692
Merge pull request #571 from skrutt/master
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Correct pinout for VGA connector
2024-03-26 12:35:37 +01:00
191a5bb17a
alinx_axau15: Add RGMII Ethernet/Etherbone support.
2024-03-25 16:08:38 +01:00
9d083eb8bd
sqrl_acorn: the litefury (cle-101 variant is a xc7a100t, so use the right proxy when flashing
2024-03-22 10:01:43 +01:00
8dea12d48f
platforms/fairwaves_xtrx: Update with developments from XTRX-Julia project and simplify variants/switch to openFPGALoader.
2024-03-19 11:49:48 +01:00
f50ee97520
alinx_axau15: Minor adjustments.
2024-03-14 15:13:59 +01:00
93ba4aba6e
Add support for CTUCAN for Genesys2 board
2024-03-13 06:51:48 +01:00
0ec5624875
Correct pinout for VGA connector
2024-03-08 10:22:32 +01:00
e1e989acac
Olimex GateMate A1 EVB: new Board
2024-03-02 12:23:27 +01:00
85971de42e
Merge pull request #568 from hansfbaier/qmteck-k325-fix
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Enable bitstream compression on Kintex K325T
2024-03-02 10:42:20 +01:00
e5d8f62c83
enable bitstream compression on Kintex K325T
2024-03-02 07:48:12 +07:00
9dd246c26e
Merge pull request #567 from trabucayre/gatemate_evb
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adding colognechip_gatemate_evb
2024-02-28 17:35:48 +01:00
af09c81db6
adding colognechip_gatemate_evb
2024-02-28 17:27:21 +01:00
82c0e191a7
QMTech XC7K325T: use the buttons on the core board
2024-02-28 04:40:17 +07:00
72ea25512b
QMTech XC7K325T: remove wrong reset button assignment
2024-02-27 15:42:38 +07:00
9c3f272f6e
platforms/lambdaconcept_ecpix5: Minor cleanup.
2024-02-09 12:20:12 +01:00
a6f8f0e696
Merge pull request #561 from ruurdk/qmtech
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Add support for QMTech Kintex 7 Development board
2024-02-06 16:29:54 +01:00
66152390ba
Add support for QMTech Kintex 7 Development board
2024-02-01 16:16:01 +01:00
721fa0b4b3
axau15: added more FMC+ pins and made some corrrections
2024-01-27 03:27:48 +01:00
3438f74224
sipeed_tang_mega_138k: Added PCIe reset and other pins from sipeed documentation
2024-01-13 04:38:54 -03:00
29143a89f8
platforms/sipeed_tang_mega_138k: adding some resources/connectors definition (SPI flash, Buttons, SDRAM connector)
2024-01-10 10:37:01 +01:00
fd59d954ba
add support for minze board
2023-12-29 06:01:59 +01:00
e229d1a0b6
alinx_axau15: First review/cleanup pass and fix missing INTERNAL_VREF on bank 66.
2023-12-28 19:48:50 +01:00
b340d9e5e7
Merge pull request #550 from Johnsel/master
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alinx_axau15: Added new Alinx Artix US+ board
2023-12-28 19:24:14 +01:00
754b6d2427
add support for mozart ml1
2023-12-19 22:18:21 +01:00
2c2b3e318a
Fixed pinout and first steps adding PCIe support
2023-12-12 15:44:51 +01:00
7be052911b
alinx_axau15: Added new Alinx Artix US+ board
2023-12-05 20:45:57 +01:00
ba86121ea9
platforms/efinix_trion_t120_bga576_dev_kit: P2/P3 description
2023-11-14 19:27:59 +01:00
0ee5fedb63
platforms/sipeed_tang_mega_138k: move RGMII Ethernet to dock_io
2023-11-10 07:41:09 +01:00
fd36608438
sipeed_tang_mega_138k: fix pins DRIVE, remove a[15], fix memory model
2023-11-10 07:39:19 +01:00
17a0152ef9
Merge pull request #547 from trabucayre/tangMega138k
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Tang mega138k
2023-11-09 11:56:58 +01:00
4ff1362e5b
targets,platforms/sipeed_tang_mega_138k: fix copyright
2023-11-09 11:55:35 +01:00
8e3dc21ce5
aliexpress_xc7k70t: Review/Cleanup.
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- Cosmetic cleanups in platform.
- Add clk50 constraint.
- Remove JTAGBone specific support since now directly handled by LiteX.
2023-11-09 08:26:06 +01:00
69ee48d421
Add AliExpress Kintex XC7K70T board
2023-11-09 10:34:18 +07:00
8c3ac2f114
platforms/sipeed_tang_mega_138k: DDR3 IOs
2023-11-08 07:00:18 +01:00
d4e73fd389
platforms/sipeed_tang_mega_138k: fix sdram_connector pinout and move to _dock_io
2023-11-08 07:00:01 +01:00
c7ad9adacb
terasic_de2_115: Cosmetic cleanup.
2023-11-06 19:21:53 +01:00
d8228c2c0f
Merge pull request #544 from madprogrammer/master
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Improve terasic_de2_115 target support
2023-11-06 19:17:54 +01:00
e90c08cb30
platforms/sipeed_tang_mega_138k: adding dock io and DVI RX/TX
2023-11-05 16:26:33 +01:00
e9fd7433a6
platforms/sipeed_tang_mega_138k: adding module connectors
2023-11-05 16:25:38 +01:00
e9f26e1729
platforms/sipeed_tang_mega_138k: swapping serial pins
2023-11-05 16:23:59 +01:00
554cdaab73
Merge pull request #541 from hansfbaier/master
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QMTech boards: make Artix7 bitstream/platform commands conditional on toolchain
2023-10-24 08:41:31 +02:00
57a345cc75
tidy QMTech 7series boards, add missing bistream compression
2023-10-24 08:26:35 +07:00
ce951589d1
improve terasic_de2_115 target support
2023-10-23 21:15:00 +03:00
41351a845a
Merge pull request #526 from Chandler-Kluser/master
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Added QMTECH RP2040 Daughterboard
2023-10-23 11:23:44 +02:00
5f694166ce
platforms/sipeed_tang_primer_25k: swap UART TX & RX, fix TX pin (J1:20 -> J1:21)
2023-10-19 06:26:10 +02:00
9ae224a2a7
sipeed_tang_primer_25k: new board
2023-10-17 07:45:40 +02:00
842819d832
platforms/xilinx_zcu102: Add pin definitions for DDR4 SDRAM and FMC connectors.
2023-10-13 23:53:10 +09:00
371234b369
platforms/analog_pocket: Add Video Scaler pins definitions and output_term/current strength on SDRAM pins.
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From https://github.com/tpwrules/pocket_linux .
2023-10-09 10:12:38 +02:00
149ed9630c
platforms/ocp_tap_timecard: Add with_multiboot parameter to enable/disable multiboot images generation.
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Generating multiboot images is not very fast, disabling it for quick P&R iterations can be useful.
2023-10-03 19:03:42 +02:00
aa853d5a48
platforms/efinix_trion_t20_bga256_dev_kit: CON4 cleanup
2023-10-02 19:19:50 +02:00
bc6f6d869e
platforms/efinix_trion_t20_bga256_dev_kit: CON3 (LVDS RX) / CON4 (LVDS TX)
2023-10-02 18:51:53 +02:00
6f0cd56109
update to match zcu102 constraint spec
2023-09-28 11:11:21 +02:00
928c1a2539
platforms/sipeed_tang_mega_138k: Fix default_clk_name/period.
2023-09-26 21:07:21 +02:00
29018a8382
Merge pull request #523 from Icenowy/tangmega138k
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[RFC] sipeed_tang_mega_138k: new board
2023-09-26 19:12:44 +02:00
5f8ac853b1
Resolve High Density bank IOStandard error
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This resolves the following error during `build` on Vivado 2023.1:
```ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 47 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
clk125_p```
2023-09-25 12:50:30 +02:00
1fb317840f
platforms/ocp_tap_timecard: Add clk10 and som_led.
2023-09-22 08:33:04 +02:00
c14d66cb6b
analog_pocket: Add Serial (to fix CI) and add to board list.
2023-09-21 10:11:55 +02:00
3df677cfeb
Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART.
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$ ./analog_pocket.py --uart-name=jtag_uart --build --load
$ litex_term jtag --jtag-config=openocd_usb_blaster.cfg
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 21 2023 08:53:57
BIOS CRC passed (1e2b3f44)
LiteX git sha1: 7d738737
--=============== SoC ==================--
CPU: VexRiscv @ 50MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM: 8.0KiB
L2: 8.0KiB
SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM: 64.0MiB
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 15.6MiB/s
Read speed: 22.1MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2023-09-21 09:19:57 +02:00
a0b7811c54
platforms/ti60_f225: Add n parameter to rgmii_ethernet_qse_ios to allow having multiple adapters.
2023-09-11 10:45:28 +02:00
c26f76e8cb
Fixed misplacement of platform file
2023-09-03 15:49:38 -03:00
632bab937e
Update qmtech_artix7_fgg676.py
2023-09-01 05:03:44 -03:00
d8b006568a
Update qmtech_artix7_fgg676.py
2023-09-01 04:53:07 -03:00
b92c96b3a4
colorlight_i9plus: Cosmetic cleanups.
2023-08-30 17:22:11 +02:00
3471617878
Merge pull request #502 from chmousset/add_colorlight_i9plus
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[init] added colorlight i9+ based on XC7A50 FPGA
2023-08-30 16:54:26 +02:00
4862d0667c
Merge pull request #515 from josuah/crosslink_nx_openocd
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Allow use of OpenOCD for the Crosslink-NX
2023-08-28 16:35:20 +02:00
5799c35247
platforms/gsd_orangecrab: Set alt point to DFUProg.
2023-08-28 16:28:04 +02:00
ebfb9b8e01
sipeed_tang_mega_138k: new board
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Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-15 16:33:13 +08:00
8172a304b3
platforms/crosslink_nx_evn: allow use of OpenOCD
2023-08-08 23:25:41 +02:00
3903cdee92
Merge pull request #517 from bayi/master
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Digilent CMOD A7 ISSIRAM fix
2023-08-08 19:29:32 +02:00
a6b025f7f3
Fix Digilent Cmod A7 ISSIRAM reading
2023-08-05 19:56:15 +02:00
5412d0e0e9
platforms/crosslink_nx_evn: allow use of UARTBone
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This goes along a small resistor jumper modification and firmware flashing like
it is for the ECP5 board. A warning message is added as the default serial might
be affected (--serial serial by default). The FTDI modification software used
for the ECP5 seems to be requried and matching.
This can be tested this way:
targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load
litex_server --uart --uart-port /dev/ttyUSB1
litex_cli --regs
2023-08-04 20:47:32 +02:00
efc15a91a9
global: Use new WaitTimer integrated cast to int.
2023-08-01 14:56:35 +02:00
ace789653f
platforms/ti60_f225: Add connector numbering to ease review/schematic comparison.
2023-07-21 09:08:22 +02:00
72a951081a
xu8_pe3: Fix clk_p/n on pcie_x8.
2023-07-13 18:10:46 +02:00
18a3909a9c
global: Switch to litex.gen.genlib.misc.
2023-07-06 22:11:45 +02:00
e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu
2023-06-27 21:35:55 +05:30
061a768495
Add Alchitry Cu board
2023-06-16 21:36:57 +05:30
c49a50a934
platform/gsd_butterstick: Add mssing USB comment.
2023-06-16 09:10:47 +02:00
28ecb1e9f3
enclustra_mercury_xu8_pe3: Fix pcie_x8 and add GTH banks for pcie_x4/x8.
2023-06-15 17:57:38 +02:00
06e8829eb4
platforms/gsd_butterstick: Add default programmer to avoid breaking older designs.
2023-06-14 16:40:35 +02:00
96175a9986
sitlinv_stlv7325_v2: Add default value to vccio.
2023-06-07 15:00:49 +02:00
765ee1a3ce
sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V
2023-06-07 10:12:55 +07:00
Gwenhael Goavec-Merou
enjoy-digital
Hans Baier
Xilokar
Saket Sinha
skrutt
Gwenhael Goavec-Merou
Ruurd Keizer
John Simons
Lucas Teske
inc
Hans Baier
Sergey Anufrienko
rniwase
Liana Koleva
Chandler Klüser
Chandler Klüser
Icenowy Zheng
Josuah Demangeon
Bayi
Mark1626