6333fbe724
targets/siglent_sds1104xe: Update with new LiteX Ethernet/Etherbone integration.
2023-11-13 09:02:09 +01:00
1969b4f6d3
siglent_sds1104xe: Update Ethernet/Etherbone integration.
2023-11-10 18:58:42 +01:00
fd36608438
sipeed_tang_mega_138k: fix pins DRIVE, remove a[15], fix memory model
2023-11-10 07:39:19 +01:00
17a0152ef9
Merge pull request #547 from trabucayre/tangMega138k
...
Tang mega138k
2023-11-09 11:56:58 +01:00
4ff1362e5b
targets,platforms/sipeed_tang_mega_138k: fix copyright
2023-11-09 11:55:35 +01:00
8e3dc21ce5
aliexpress_xc7k70t: Review/Cleanup.
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- Cosmetic cleanups in platform.
- Add clk50 constraint.
- Remove JTAGBone specific support since now directly handled by LiteX.
2023-11-09 08:26:06 +01:00
69ee48d421
Add AliExpress Kintex XC7K70T board
2023-11-09 10:34:18 +07:00
2c52ce0c47
targets/sipeed_tang_mega_138k: fix SDRAM (requires Mister XSDS v3.0 extension)
2023-11-08 07:13:28 +01:00
e9f53685fe
targets/sipeed_tang_mega_138k: DDR3 support (not working)
2023-11-08 07:00:24 +01:00
bc74eeca78
targets/digilent_nexys_video: Use reset_buf on sys_clk's create_clkout to improve timings and demonstrate use.
2023-11-07 13:22:30 +01:00
c7ad9adacb
terasic_de2_115: Cosmetic cleanup.
2023-11-06 19:21:53 +01:00
d8228c2c0f
Merge pull request #544 from madprogrammer/master
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Improve terasic_de2_115 target support
2023-11-06 19:17:54 +01:00
e23ac0251a
targets/sipeed_tang_mega_138k: HDMI support
2023-11-05 16:36:59 +01:00
8792dd8e53
target/analog_pocket: Remove debug (Will be investigated externally).
2023-10-27 15:32:36 +02:00
ce951589d1
improve terasic_de2_115 target support
2023-10-23 21:15:00 +03:00
0d560bc240
targets/siglent_sds1104xe: Review.
2023-10-23 19:25:12 +02:00
71d8b17fff
Merge pull request #543 from trabucayre/siglent_sds1104xe_etherbone
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targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode
2023-10-23 19:20:32 +02:00
26d112b094
targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode
2023-10-23 19:07:37 +02:00
afbf9eb8c9
target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally
2023-10-23 17:43:13 +02:00
a6f3c5276e
target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally
2023-10-23 17:16:57 +02:00
a4fc45bba6
targets/efinix_titanium_ti60_f225_dev_kit: adding jtagbone support (`litex_server --jtag --jtag-config openocd_titanium_ft4232.cfg`)
2023-10-18 09:11:54 +02:00
eae62a60ac
target/analog_pocket: Fix.
2023-10-17 21:40:46 +02:00
cc19078650
targets/analog_pocket: Disable debug for CI.
2023-10-17 15:23:58 +02:00
f86ba2dea0
targets/analog_pocket: Add debug code for framebuffer (wip).
2023-10-17 13:18:07 +02:00
9ae224a2a7
sipeed_tang_primer_25k: new board
2023-10-17 07:45:40 +02:00
3a75f6cf79
Merge pull request #537 from rniwase/master
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xilinx_zcu102: Add pin definitions for DDR4 SDRAM and FMC connectors, add litedram to the target.
2023-10-14 20:14:53 +02:00
9fb388407a
targets/xilinx_zcu102: Add litedram to the target.
2023-10-14 00:00:26 +09:00
e0e8600db4
fix help text
2023-10-12 11:21:20 -04:00
ec2f9480b8
targets/analog_pocket: Fix indent on videophy/cores.
2023-10-09 11:59:32 +02:00
6386f290e9
targets/analog_pocket: Add --video-colorbars/video-terminal/video-framebuffer arguments.
2023-10-09 10:59:15 +02:00
dec25b7ce9
targets/analog_pocket: Add initial Video support.
...
From https://github.com/tpwrules/pocket_linux .
2023-10-09 10:14:00 +02:00
7359a331eb
analog_pocket: Add 1:2 (HalfRate) SDRAM support.
2023-10-06 19:25:42 +02:00
d00810c983
sds1104xe: Fix typo.
2023-10-06 19:25:22 +02:00
3d7a1dd152
analog_pocket: +x.
2023-10-02 16:20:09 +02:00
fd6aee0250
targets/sqrl_acorn: Drive pcie_clkreq_n (Thanks @myftptoyman).
2023-09-27 11:06:50 +02:00
29018a8382
Merge pull request #523 from Icenowy/tangmega138k
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[RFC] sipeed_tang_mega_138k: new board
2023-09-26 19:12:44 +02:00
3df677cfeb
Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART.
...
$ ./analog_pocket.py --uart-name=jtag_uart --build --load
$ litex_term jtag --jtag-config=openocd_usb_blaster.cfg
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 21 2023 08:53:57
BIOS CRC passed (1e2b3f44)
LiteX git sha1: 7d738737
--=============== SoC ==================--
CPU: VexRiscv @ 50MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM: 8.0KiB
L2: 8.0KiB
SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM: 64.0MiB
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 15.6MiB/s
Read speed: 22.1MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2023-09-21 09:19:57 +02:00
5064c65dac
targets: Switch to openocd_usb_blaster/2.cfg.
2023-09-21 09:16:24 +02:00
b92c96b3a4
colorlight_i9plus: Cosmetic cleanups.
2023-08-30 17:22:11 +02:00
3471617878
Merge pull request #502 from chmousset/add_colorlight_i9plus
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[init] added colorlight i9+ based on XC7A50 FPGA
2023-08-30 16:54:26 +02:00
c960e85d11
targets/efinix: Now rely in LiteX to automatically exclude Tristate IOs.
2023-08-30 09:59:23 +02:00
4bb064853d
targets/efinix: Update RGMII PHYs (IOs are now directly excluded in PHYs).
2023-08-30 08:56:20 +02:00
347b477b07
sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code.
...
Now passing memtest with valid reported memory size:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS CRC passed (d32a9529)
LiteX git sha1: 85dadb82
--=============== SoC ==================--
CPU: VexRiscv SMP-LINUX @ 48MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64.0KiB
SRAM: 6.0KiB
L2: 512B
SDRAM: 128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5)
MAIN-RAM: 128.0MiB
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |00000000| delays: -
m0, b01: |00000000| delays: -
m0, b02: |01100000| delays: 01+-00
m0, b03: |00000000| delays: -
best: m0, b02 delays: 01+-00
m1, b00: |00000000| delays: -
m1, b01: |00000000| delays: -
m1, b02: |01100000| delays: 01+-00
m1, b03: |00000000| delays: -
best: m1, b02 delays: 01+-00
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 11.7MiB/s
Read speed: 17.4MiB/s
2023-08-29 16:50:17 +02:00
4862d0667c
Merge pull request #515 from josuah/crosslink_nx_openocd
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Allow use of OpenOCD for the Crosslink-NX
2023-08-28 16:35:20 +02:00
232e829b8f
Merge branch 'master' into crosslink_nx_main_ram
2023-08-28 16:34:27 +02:00
a9ecbffe8f
Merge pull request #520 from josuah/crosslink_nx_prog_flash
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targets/lattice_crosslink_nx_evn: fix arguments in flash programming
2023-08-28 16:33:23 +02:00
2c3d77b5be
Merge branch 'master' into crosslink_nx_spi_flash
2023-08-28 16:32:37 +02:00
a5a6a313cc
targets/lattice_crosslink_nx_evn: add main_ram section for firmware
...
This takes the values from the Antmicro SDI MIPI converter as a model
and is enough to run a Zephyr hello world, but not seemingly enough for
a the Zephyr Shell sample.
Related: https://github.com/litex-hub/zephyr-on-litex-vexriscv/pull/13
2023-08-18 19:56:58 +02:00
ebfb9b8e01
sipeed_tang_mega_138k: new board
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Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-15 16:33:13 +08:00
2e5c6eb7a7
platforms/crosslink_nx_evn: add SPI flash support
2023-08-11 16:46:52 +02:00
1a46bcce5e
targets/lattice_crosslink_nx_evn: fix arguments in flash programming
2023-08-10 14:39:01 +02:00
3c0b6956cc
platforms/crosslink_nx_evn: Fix 5412d0e always disabling uartbone
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Also fix a warning about register_mem being deprecated, taking
inspiration from platforms/crosslink_nx_vip
2023-08-09 18:07:13 +02:00
8172a304b3
platforms/crosslink_nx_evn: allow use of OpenOCD
2023-08-08 23:25:41 +02:00
3903cdee92
Merge pull request #517 from bayi/master
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Digilent CMOD A7 ISSIRAM fix
2023-08-08 19:29:32 +02:00
4362cb23a1
Fix Digilent Cmod A7 ISSIRAM reading
2023-08-05 19:56:32 +02:00
a6b025f7f3
Fix Digilent Cmod A7 ISSIRAM reading
2023-08-05 19:56:15 +02:00
5412d0e0e9
platforms/crosslink_nx_evn: allow use of UARTBone
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This goes along a small resistor jumper modification and firmware flashing like
it is for the ECP5 board. A warning message is added as the default serial might
be affected (--serial serial by default). The FTDI modification software used
for the ECP5 seems to be requried and matching.
This can be tested this way:
targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load
litex_server --uart --uart-port /dev/ttyUSB1
litex_cli --regs
2023-08-04 20:47:32 +02:00
efc15a91a9
global: Use new WaitTimer integrated cast to int.
2023-08-01 14:56:35 +02:00
cbcf6df26f
lattice_ecp5_evn: add_jtagbone flag
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This follows https://github.com/enjoy-digital/litex/pull/1087 which
allows using the built-in JTAG for both the FPGA programming and the
internal core of the FPGA.
2023-07-31 13:53:24 +02:00
2d3b81a532
efinix_trion_t120_bga576: Add Ethernet through RGMII PMOD and switch to it.
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See https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-859366899 for the PMOD.
2023-07-27 11:52:40 +02:00
c1088befe5
targets/CRG: Add rst signal when missing.
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Allow properly reseting the PLL from the SoC.
2023-07-26 16:56:27 +02:00
ce121663ff
targets/uartbone: Update with LiteX change.
2023-07-20 15:42:47 +02:00
18a3909a9c
global: Switch to litex.gen.genlib.misc.
2023-07-06 22:11:45 +02:00
67be3ab677
targets: +x on alchitry_cu and vcu128.
2023-07-06 13:29:35 +02:00
e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu
2023-06-27 21:35:55 +05:30
58805f037c
avnet_aesku40: Expose ethernet/etherbone parameters.
...
To be able to test more easily usrgmii build.
2023-06-13 09:26:07 +02:00
4705a0274e
Support SPI Flash in Colorlight 5A-75x
2023-06-09 13:43:34 -04:00
765ee1a3ce
sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V
2023-06-07 10:12:55 +07:00
8a263c18f2
sitlinv_stlv7325: Rename to v1 and update VCCIO to fix --with-pcie generation.
2023-05-30 10:39:20 +02:00
2ae2dfa6a3
Add vcu128 target ( #497 )
...
Add initial VCU128 support.
2023-05-25 22:25:44 +02:00
e59d75f593
qmtech_xc7k325t: Fix build/CI.
2023-05-12 12:19:16 +02:00
ca6b607255
targets/qmtech: Add missing +x.
2023-05-12 12:09:20 +02:00
550bc0eee5
add QMTech XC7K325T board, add seven segment display to daughterboard
2023-05-08 11:51:51 +07:00
187080228c
add qmtech_xc7l325t
2023-05-08 05:17:35 +07:00
d33cf1a74c
mnt_rkx7: Cosmetic cleanups.
2023-05-05 09:48:06 +02:00
c05c494a82
targets/mnt_rkx7/usb_ohci: Use SoC.bus if SoC does not have a DMA bus.
2023-05-05 09:43:19 +02:00
6144966d24
Merge pull request #501 from mntmn/master
...
mnt_rkx7: RGB and USB fix, add HDMI terminal
2023-05-05 09:37:40 +02:00
9c222454cc
Merge pull request #503 from chmousset/add_colorlight_i5a-907
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Add colorlight i5a 907
2023-05-03 09:50:26 +02:00
2bff2d4260
target/stlv7325-v2: tune eth phy delay
2023-05-01 09:28:03 -04:00
31c680abf8
[enh] added option for uartbone
2023-04-30 09:42:31 +02:00
874532871f
[enh] taking advantage of pins directly connected
2023-04-30 09:24:49 +02:00
1202c387bf
[init] added colorlight i5a-907 support
2023-04-30 09:24:46 +02:00
fd5511f3fd
[fix] add pmod uart in default config
2023-04-30 09:24:15 +02:00
f5dfdf9abf
[enh] added doc about JTAG and ext. board
2023-04-29 19:39:51 +02:00
322cc5d45b
[init] added colorlight i9+ based on XC7A50 FPGA
2023-04-29 18:36:35 +02:00
1f6e7f36a5
target/stlv7325-v2: fix typo in eth phy delay
2023-04-28 16:56:37 -04:00
1185ff51f1
Initial support for STLV7325 (v2) Kintex-7 board.
...
This is the 2nd (2023) version of the board sold through
https://www.aliexpress.us/item/3256801088848039.html
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-04-28 10:24:21 -04:00
a9e3e3c050
Merge branch 'master' of https://github.com/litex-hub/litex-boards
2023-04-25 20:29:11 +02:00
17a5d3c130
mnt_rkx7: add HDMI terminal, default USB to true
2023-04-25 20:27:29 +02:00
68bfb325a5
Fix Memory test failure of Alveo U250
2023-04-24 17:35:58 +09:00
340da5393c
Fix Memory initialization of Alveo U200 failed #1606
2023-04-17 18:59:50 +07:00
2ed66317c7
efinix_xyloni_dev_kit: fix build error
2023-04-14 22:31:21 +10:00
c7077880b9
copyright notices on enclustra
2023-04-11 10:29:52 +07:00
ed947d1b55
enclustra: add baseboard ST1
2023-04-11 10:29:44 +07:00
a8eb0b20c1
Merge pull request #491 from hansfbaier/stlv7325-hdmi
...
STL7325: Add Video, and connectors (FMC, BTB, 2.54mm)
2023-04-07 09:06:55 +02:00
2f13decc49
stlv7325: make VCCIO configurable
2023-04-07 09:27:03 +07:00
566a753dd3
stlv7325: S7PLL is enough
2023-04-07 08:45:06 +07:00
7c99f0758d
stlv7325: fix video args
2023-04-07 08:35:49 +07:00
66cbd27bbf
stlv7325: fix video PHY
2023-04-07 08:25:59 +07:00
5067a2683f
sitlinv_stlv7325: add video HDMI, enable compressed bitstream
2023-04-07 07:31:42 +07:00
Florent Kermarrec
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Hans Baier
Sergey Anufrienko
rniwase
darryln
Josuah Demangeon
Icenowy Zheng
Bayi
Mark1626
Ilya Ostrovskiy
Chen
Gabriel Somlo
Charles-Henri Mousset
Lukas F. Hartmann
offNaria
Do Viet Thanh
Richard Tucker