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331 Commits

Author SHA1 Message Date
Florent Kermarrec 8c722db54e liteeth/phy/mii: assign tx_er only if exists (as it's done on GMII) 2015-04-12 14:43:35 +02:00
Florent Kermarrec 4329e3e1b9 liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705) 2015-04-12 14:28:17 +02:00
Florent Kermarrec 93ed3212f7 timer: revert prescaler (we will in fact use a software prescaler for uIP) 2015-04-10 18:57:06 +02:00
Florent Kermarrec 80ef7291c1 timer: add prescaler 2015-04-10 13:58:44 +02:00
Robert Jordens d6c19858fa s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE 2015-04-10 16:12:29 +08:00
Sebastien Bourdeauducq 603a4ef51e liteeth: adapt to new ModuleTransformer 2015-04-10 11:42:25 +08:00
Florent Kermarrec ea613cd8ee litesata: update build core target generation 2015-04-09 00:00:25 +02:00
Florent Kermarrec 03aa972bb6 lite*: finish ModuleTransformer adaptations (need to be tested on board) 2015-04-08 23:27:22 +02:00
Sebastien Bourdeauducq 3a2b677f85 soc,cpuif: support user defined constants 2015-04-09 00:34:36 +08:00
Sebastien Bourdeauducq 176b9240a9 soc: use new ModuleTransformer API 2015-04-06 23:52:34 +08:00
Robert Jordens 66f8dcbfaf lite*: adapt to new ModuleTransformer semantics 
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
 2015-04-04 19:17:24 +08:00
Florent Kermarrec 2583e975f0 soc/cpuif: fix CSR base generation for memories (name is already fullname) 2015-04-03 13:57:37 +02:00
Florent Kermarrec c9c11e7aa8 soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions 2015-04-03 12:45:32 +02:00
Sebastien Bourdeauducq 85b3cced22 use str.format 2015-04-03 17:43:46 +08:00
Florent Kermarrec 0db6e1d624 soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube) 2015-04-03 11:14:28 +02:00
Florent Kermarrec b437dc3185 remove use of _r prefix on CSRs 2015-04-02 12:18:43 +02:00
Sebastien Bourdeauducq 696819cc7f move gpio from cpu.peripherals to com 2015-04-02 17:17:33 +08:00
Sebastien Bourdeauducq 382ed013af minor cleanups 2015-04-02 14:40:29 +08:00
Sebastien Bourdeauducq bbdbf87599 Merge branch 'master' of github.com:m-labs/misoc 2015-04-02 10:14:24 +08:00
Florent Kermarrec 60124be293 adapt LiteSATA to new SoC 2015-04-01 22:52:19 +02:00
Florent Kermarrec dcdf5df4de adapt LiteEth to new SoC 2015-04-01 22:50:29 +02:00
Florent Kermarrec f65c0a3c95 adapt LiteScope to new SoC 2015-04-01 22:46:24 +02:00
Florent Kermarrec 2d23ab7a85 soc/sdram: fix do_finalize 2015-04-01 22:38:04 +02:00
Sebastien Bourdeauducq 2900429e65 soc: use set 2015-04-02 00:14:56 +08:00
Sebastien Bourdeauducq 369086a178 soc: simplify integrated memory parameters 2015-04-02 00:09:38 +08:00
Sebastien Bourdeauducq 273242b399 soc/sdram: minor cleanup 2015-04-01 23:41:55 +08:00
Sebastien Bourdeauducq 6e2a662dd7 litesata: adapt to new SoC API 2015-04-01 17:37:53 +08:00
Sebastien Bourdeauducq 9599eb6fae soc: remove cpu_boot_file argument 2015-04-01 17:32:45 +08:00
Sebastien Bourdeauducq fb86445d14 soc: remove cpu_or_bridge and with_cpu arguments 2015-04-01 17:29:51 +08:00
Sebastien Bourdeauducq a148af97ba soc: retrieve csr and memory regions using methods 2015-04-01 16:49:32 +08:00
Sebastien Bourdeauducq 8b19a11cd7 soc: use add_wb_master function 2015-04-01 15:56:54 +08:00
Sebastien Bourdeauducq 2a1112b912 soc: simplify/fix csr busword 2015-04-01 15:48:56 +08:00
Sebastien Bourdeauducq 04f29e97e2 soc: remove unnecessary imports 2015-04-01 15:15:09 +08:00
Sebastien Bourdeauducq 5113301130 soc: improve memory region conflict check 2015-04-01 15:14:02 +08:00
Sebastien Bourdeauducq 980791e2b8 soc: remove ns function 2015-04-01 14:33:12 +08:00
Florent Kermarrec b313772a0c sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0) 2015-03-29 12:34:40 +02:00
Florent Kermarrec be20fbabe4 soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!) 2015-03-28 23:35:44 +01:00
Florent Kermarrec 0649ded5fd soc: simplify main_ram_size computation and share it between LASMIcon and Minicon 2015-03-28 23:10:33 +01:00
Florent Kermarrec a8d91c0c1d sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue) 2015-03-28 16:35:15 +01:00
Florent Kermarrec 75ee8a5db9 sdram/phy/simphy: OK with DDR3 2015-03-28 01:59:55 +01:00
Florent Kermarrec 51ce7cad6f sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2 2015-03-28 01:18:35 +01:00
Florent Kermarrec a95b3f8f13 sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it) 2015-03-28 01:17:50 +01:00
Florent Kermarrec 7fe748e1b0 sdram/module: clean up tREFI. (use 64ms/8k or 4k) 2015-03-28 01:09:21 +01:00
Florent Kermarrec 9137b91e9e sdram: remove nbits from modules and databits from GeomSettings 2015-03-26 23:27:37 +01:00
Florent Kermarrec 9a9af17aca sdram/phy/simphy: remove use of iter 2015-03-26 23:02:23 +01:00
Florent Kermarrec e6de4b1bf9 sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16) 2015-03-26 22:28:32 +01:00
Florent Kermarrec 257706517e software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation 2015-03-26 00:01:42 +01:00
Florent Kermarrec ff11cb97a9 sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True 2015-03-25 17:22:26 +01:00
Florent Kermarrec ba8b24df57 sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00
Florent Kermarrec 7ea9e2ba89 sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-25 16:56:29 +01:00
Florent Kermarrec 20207c9c32 liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6) 2015-03-22 11:11:37 +01:00
Florent Kermarrec c77562f44b liteusb: make oe_n optional on ft2232h phy 2015-03-22 10:56:56 +01:00
Florent Kermarrec ed5746a1fe liteusb: fix imports 2015-03-22 10:56:29 +01:00
Florent Kermarrec 92f81409f2 sdram/module: fix tREFI on AS4C16M16 2015-03-22 03:20:02 +01:00
Florent Kermarrec 30c2521eb0 sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00
Florent Kermarrec 70469e1f37 sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit) 2015-03-21 21:32:39 +01:00
Florent Kermarrec 9bc71f374a rename sdram mapping to main_ram 2015-03-21 21:01:46 +01:00
Florent Kermarrec c55199deb9 misoclib/soc: add _integrated_ to cpu options to avoid confusion 2015-03-21 20:51:37 +01:00
Florent Kermarrec c60d99583d sdram/module: add tREFI uniformization to TODO 2015-03-21 18:59:16 +01:00
Florent Kermarrec 0f9b0c6f0f sdram/module: add MT47H128M8 DDR2 (used for a customer) 2015-03-21 18:52:10 +01:00
Florent Kermarrec 45eb5090db sdram/module: add speedgrate note for IS42S16160 and AS4C16M16 2015-03-21 18:41:59 +01:00
Florent Kermarrec a560ba35bd sdram/module: add AS4C16M16 for minispartan6 2015-03-21 18:38:53 +01:00
Florent Kermarrec 854058a8db sdram/module: add description and TODO list 2015-03-21 17:44:04 +01:00
Florent Kermarrec 52924ee1f2 sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705 2015-03-21 17:25:36 +01:00
Florent Kermarrec fd2f8d4bb4 sdram: define MT46V32M16 and use it on m1/mixxeo 2015-03-21 17:04:58 +01:00
Florent Kermarrec de2f1c31d5 sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
Florent Kermarrec 6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
 2015-03-21 12:55:39 +01:00
Florent Kermarrec 9107710f03 litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
Florent Kermarrec 82fe83a1c4 sdram: raise NotImplementedError if Minicon is used others memories than SDR (not functional for now) 2015-03-19 16:08:03 +01:00
Florent Kermarrec 84b631c929 liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc 2015-03-19 14:52:02 +01:00
Florent Kermarrec 6bdf60567c liteeth/mac/core: fix hw_preamble_crc register generation 2015-03-19 13:03:27 +01:00
Florent Kermarrec 236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00
Florent Kermarrec 70f1f96fda litescope/drivers: do not build regs when addrmap is None 2015-03-17 16:04:31 +01:00
Florent Kermarrec a266deb58e LiteXXX cores: fix frequency print in test/test_regs.py 2015-03-17 16:01:25 +01:00
Florent Kermarrec d2cb41bc63 LiteXXX cores: convert port parameter to int if is digit in test/make.py 2015-03-17 15:58:21 +01:00
Florent Kermarrec 2327710387 liteeth/phy/gmii : set tx_er to 0 only if it exits 2015-03-17 12:24:06 +01:00
Florent Kermarrec 408d0fd2dd liteeth: use default programmer in make.py 2015-03-17 12:12:21 +01:00
Florent Kermarrec ec6ae75065 liteeth: use CRG from Migen in base example 2015-03-17 12:11:51 +01:00
Florent Kermarrec a874f85854 litescope: use CRG from Migen 2015-03-17 11:52:54 +01:00
Florent Kermarrec faf185d58d liteeth: make gmii phy generic 2015-03-16 23:04:37 +01:00
Florent Kermarrec d8b59c03a2 litesata: avoid hack on kc705 platform with new mibuild toolchain management 2015-03-14 01:08:36 +01:00
Florent Kermarrec 28d04ec300 soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
Sebastien Bourdeauducq 32676fffd2 soc/sdram: sync with new mibuild toolchain management 2015-03-13 23:19:08 +01:00
Florent Kermarrec c3c7f627d9 liteeth/phy: typo (thanks sb) 2015-03-12 21:54:10 +01:00
Florent Kermarrec cd6c04b24f soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx 2015-03-12 17:12:56 +01:00
Florent Kermarrec 767d45727a uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty). 2015-03-12 16:57:38 +01:00
Florent Kermarrec b157031e8a uart/sim: add pty (optional, to use flterm) 2015-03-09 23:29:06 +01:00
Florent Kermarrec 6cbf13036b liteeth/mac: fix padding limit (+1), netboot OK with sim platform 2015-03-09 20:59:34 +01:00
Florent Kermarrec 47cceea222 liteeth/mac: use Counter in sram and move some logic outside of fsms 2015-03-09 20:22:14 +01:00
Florent Kermarrec b10836a8eb liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit 2015-03-09 17:21:29 +01:00
Florent Kermarrec 1b58813d13 soc: do_exit is now provided by modules 2015-03-09 17:18:42 +01:00
Florent Kermarrec 360c849f21 liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter) 2015-03-09 13:23:39 +01:00
Florent Kermarrec 5dbd8af4be liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap 2015-03-09 13:23:37 +01:00
Florent Kermarrec d20b9c2221 uart: pass *args, **kwargs to sim phy 2015-03-06 12:08:10 +01:00
Florent Kermarrec af66ca7bad uart: add phy autodetect function 2015-03-06 10:19:29 +01:00
Florent Kermarrec 95fa753149 liteeth: add phy autodetect function (phy can still be instanciated directly) 2015-03-06 10:10:34 +01:00
Florent Kermarrec bee8ccf6c7 soc: enforce cpu_reset_address to 0 when with_rom is True 2015-03-06 08:21:16 +01:00
Florent Kermarrec 2b9397ff5b targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) 2015-03-06 07:56:45 +01:00
Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
Sebastien Bourdeauducq 60e87f6e87 Merge branch 'master' of https://github.com/m-labs/misoc 2015-03-04 00:46:41 +00:00