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VexRiscv
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1454 Commits

Author SHA1 Message Date
chiangkd df52fab7d1 Fix incorrect comment 2022-12-24 20:41:57 +08:00
Dolu1990 8a6a926401
Merge pull request #288 from betrusted-io/expand-satp 
Expand SATP register to 22 bits per spec
 2022-12-20 16:05:13 +01:00
bunnie bf3521f86a Expand SATP register to 22 bits per spec 
Vex only implements a 32-bit PA which does not take advantage
of the potetnial 32-bit space in Sv32 mode. Very reasonably,
Vex simply discards the top two unused bits.

However, the spec does require that the register occupy all 22
bits and it is possible for the OS to use the extra bits up top
for some bookkeeping purpose. This commit proposes to expand the
register to occupy the full 22 bits in case an OS is written
to utilize the full width of the register as written in the spec.
 2022-12-20 19:25:47 +08:00
Dolu1990 51b69a1527 SpinalHDL 1.8.0 2022-12-05 20:10:58 +01:00
Dolu1990 773f268f37 Fix FPU test syntax 2022-12-01 12:04:16 +01:00
Dolu1990 fb084327da Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert 2022-11-28 16:30:47 +01:00
Dolu1990 eafeb5fe49 Add EmbeddedRiscvJtag.debugCd 2022-11-28 11:04:02 +01:00
Dolu1990 a25ae96d33 comment debug code 2022-11-21 14:02:35 +01:00
Dolu1990 572ca3fcfa Privileged debug fake maskmax to 31 2022-11-21 14:01:28 +01:00
Dolu1990 5a8cdee884 Fix CsrPlugin dcsr.stepie 2022-11-21 11:55:07 +01:00
Dolu1990 4ae7386904 Merge pull request #276 from LYWalker/master 
Add ability to debug over Intel Virtual JTAG
 2022-11-18 17:38:50 +01:00
Dolu1990 e19e59b55c Clear mprv on xretAwayFromMachine 2022-11-17 15:03:47 +01:00
Dolu1990 663174bc73 Privileged debug now implement stoptime stopcount 2022-11-17 13:58:29 +01:00
Dolu1990 36c3346e51 ensure rvc 0 is detected as a illegal instruction 2022-11-17 11:03:45 +01:00
Dolu1990 5e17ab62d6 Fix RISC-V debug hardware breakpoints 2022-11-14 14:45:11 +01:00
Dolu1990 fe68b8494e Fix a few RISC-V official debug support : 
- Disable interrupts in debug mode
- Ensure traps do not change CSR in debug mode
- step will also consider trapEvent
 2022-11-11 14:05:38 +01:00
Dolu1990 2504f9b9b9 RISC-V debug havereset implemented 2022-11-10 15:49:07 +01:00
Dolu1990 0bfaf06a4a main.cpp add VEXRISCV_JTAG=yes 2022-11-10 13:43:14 +01:00
Dolu1990 f71234786f Remove rv64 opcode (shift and lwu) 
Thanks Milan
 2022-10-27 15:44:50 +02:00
Dolu1990 d70794f252 fix regression 2022-10-27 15:38:34 +02:00
Dolu1990 5d0deb20b3 Fix regression compilation 2022-10-27 15:20:55 +02:00
Dolu1990 9f6186cd9a Add GenFullWithRiscvPrivilegedDebugJtag demo 2022-10-27 14:55:40 +02:00
Dolu1990 6289ebcbe4 Merge branch 'riscv-debug' into dev 2022-10-27 14:46:46 +02:00
Dolu1990 a6c29766da CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled 2022-10-26 15:48:34 +02:00
Dolu1990 ab7b2cff3b fix diagram name 2022-10-26 10:48:21 +02:00
Dolu1990 7fd55c7851 Add VexRiscvAxi4LinuxPlicClint diagram drawio 2022-10-26 10:47:23 +02:00
Dolu1990 0e531515ac cleaning 2022-10-26 10:25:50 +02:00
Dolu1990 63dd787bce VexRiscvAxi4Linux now integrate Plic and Clint 2022-10-26 10:15:21 +02:00
Dolu1990 220af95043 Add VexRiscvAxi4Linux (untested, but generate a netlist) 2022-10-24 10:35:59 +02:00
Dolu1990 0979f8ba80 Add whitebox example 2022-10-24 10:24:41 +02:00
Dolu1990 17d52ce58f privileged debug now access data cache with caching enable 2022-10-21 18:58:40 +02:00
Dolu1990 486d17d245 CsrOpensbi now add rvc to misa 2022-10-21 18:58:13 +02:00
Dolu1990 662943522f Fix privileged debug trigger decode break logic 2022-10-21 17:21:13 +02:00
Dolu1990 95c656ceef riscv debug multiple harts 2022-10-21 12:28:17 +02:00
Dolu1990 0313f84419 Fix RISCV debug step 2022-10-20 10:36:30 +02:00
Dolu1990 4cd3f65296 Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet) 2022-10-19 12:36:45 +02:00
Dolu1990 87c8822f55 Merge branch 'dev' (fix FPU dirty flag on csr write) 2022-10-13 09:35:55 +02:00
Dolu1990 959e48a353 Fpu now set csr status fs on FPU csr write 2022-10-06 11:13:57 +02:00
Dolu1990 7b9891829a More bus doc #266 2022-09-26 11:39:58 +02:00
Dolu1990 051d140c33 SpinalHDL 1.7.3 2022-09-19 13:27:22 +02:00
Dolu1990 fda7da00c2 add litex --wishbone-force-32b 2022-09-06 11:19:29 +02:00
Dolu1990 e3e21994b4 use SpinalHDL "dev" 2022-07-22 09:33:19 +02:00
Dolu1990 54412bde30 getDrivingReg() update 2022-07-21 09:10:26 +02:00
Dolu1990 24795ef09b SpinalHDL 1.7.1 2022-07-20 11:17:10 +02:00
Dolu1990 a650000f0b SpinalHDL 1.7.2 2022-07-11 12:03:06 +02:00
Dolu1990 b1252f47de csr opensbi now enable ebreak 2022-06-13 16:34:49 +02:00
Dolu1990 1303c0ca7c CfuPlugin.withEnable added 2022-06-09 17:57:31 +02:00
Dolu1990 1ce4c6e493 fix VexRiscvRegressionData url 2022-06-01 09:54:11 +02:00
Dolu1990 8ab9a9b12e fix VexRiscvRegressionData url 2022-06-01 09:53:41 +02:00
Dolu1990 0f6d0f022c VexRiscvBmbGenerator now also report bytesPerLine 2022-05-24 12:37:31 +02:00