537f04a13d
alinx_axu2gca: new board
...
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2022-01-25 07:35:42 +01:00
621d45cd9e
digilent_arty: Review and improve CRG to avoid specific yosys+nextpnr code.
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sys4x/sys4x_dqs/idelay clks can be disabled when integrated-main-ram is used.
2022-01-24 19:16:07 +01:00
c2276c1e6d
Merge pull request #338 from suarezvictor/master
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Add tweaks to Arty board to support yosys+nextpnr toolchain
2022-01-24 19:02:59 +01:00
1abb03e514
tang_nano_4k: Review/Cleanup:
...
- Revert abstractions on clk_name/period: Too much abstraction to avoid duplications makes the code more difficult to read.
ex:
- When constraining clk27, frequency is already in the name.
- In the target, we want to know we are using clk27 as the main clk.
- We need a default sys_clk_freq for project only importing BaseSoC.
- Revert SPI Flash import (for consistency with other targets).
- Keep VexRiscv as default CPU since this target is able to run it and also for consistency with other targets.
2022-01-24 18:46:51 +01:00
e357eb6d8f
Merge pull request #337 from sergachev/tang_nano_4k_emcu
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Enable LiteX BIOS on ARM core on Tang nano 4K
2022-01-24 18:36:10 +01:00
cc1b46f106
tang_nano_9k: Fix HyperRAM integration.
2022-01-24 18:35:12 +01:00
db77ea5c7a
Add tweaks to Arty board to support yosys+nextpnr toolchain
2022-01-24 02:06:34 -03:00
6238052b10
tang nano 4k: disable spi flash with gowin emcu, cleanup
2022-01-23 16:10:46 +01:00
6c81fc708c
tang nano 4k: add memory regions, set default cpu
2022-01-23 13:05:51 +01:00
787f44e7d9
Merge pull request #336 from tcal-x/cmod-a7-flash
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Digilent CMOD A7: add flash support.
2022-01-23 08:36:49 +01:00
6567af6f49
Digilent CMOD A7: add flash support.
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Add both "--flash" and "--with-spi-flash"; tested on board.
4MB flash mapped at 0x00400000.
Signed-off-by: Tim Callahan <tcal@google.com>
2022-01-22 18:50:12 -08:00
f533e7f8ba
sipeed_tang_nano_9k: enable copackaged PSRAM
...
Also enable SPI SDCard which was pending by the lack of main_ram
previously.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-23 03:37:03 +08:00
999dbd572f
Merge pull request #334 from Icenowy/tang9k
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sipeed_tang_nano_9k: new board
2022-01-22 15:49:08 +01:00
e699c377a5
sipeed_tang_nano_9k: new board
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 11:45:49 +08:00
e9d4d9066a
xilinx_zcu106: add DDR4 interface and fix reset error
2022-01-22 03:08:21 +08:00
b8aad4b030
Merge pull request #332 from tcal-x/prog-cmod-a7
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Add openocd programmer for Digilent CMOD A7.
2022-01-21 08:05:22 +01:00
e0c4c0fe39
Add openocd programmer for Digilent CMOD A7.
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Signed-off-by: Tim Callahan <tcal@google.com>
2022-01-20 20:54:03 -08:00
0e91013fc7
quickfeather: fix path to libeos library when board script called not from its directory; fix wget redownloads; add libeos to gitignore
2022-01-20 18:43:59 +01:00
5f2ccb2d32
targets: Switch from bridge to crossover.
2022-01-19 17:03:17 +01:00
abb54cebb3
trenz_c10lprefkit: Add Etherbone support.
2022-01-19 14:47:14 +01:00
1ce978806d
Merge pull request #328 from sergachev/fix/zedboard_software
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Fix Zedboard software
2022-01-19 10:05:49 +01:00
f11106e9c5
targets/digilent_cmod_a7: Simplify/Cleanup.
2022-01-19 10:03:20 +01:00
f8e3cc5361
Merge pull request #327 from bl0x/digilent_cmod_a7
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digilent_cmod_a7: Remove unused clocks.
2022-01-19 09:59:44 +01:00
bbf13f4439
zedboard: remove a hack
2022-01-19 02:41:11 +01:00
4f4d47dcdd
zedboard: correct memory map
2022-01-19 02:40:54 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
7114911cea
targets: --no-ident-version is now directly provided by LiteX, remove it on targets implementing it.
2022-01-18 16:47:38 +01:00
d92a2b82fb
targets/l2_cache_reverse: Now defaulting to False in LiteX, so setting it to False for correct Framebuffer operations is no longer required.
2022-01-18 11:37:55 +01:00
2c26f07a5a
digilent_cmod_a7: Remove unused clocks.
2022-01-17 22:49:10 +01:00
12fa844b56
decklink_mini_4k: Add dedicated SATA PLL to allow SATA + Framebuffer.
2022-01-17 18:11:52 +01:00
f97e48e4f3
decklink_mini_4k: Add SATA support (over PCIe2SATA).
2022-01-17 14:19:59 +01:00
3e187dea42
quicklogic_quickfeather: Make imports similar to other boards.
2022-01-17 10:00:58 +01:00
99752738b0
Merge pull request #326 from litex-hub/pr322
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quicklogic_quickfeather: add eos_s3 arm software support library
2022-01-17 09:56:41 +01:00
9984bb8ffb
quicklogic_quickfeather: add eos_s3 arm software support library
2022-01-17 09:47:38 +01:00
06fb73ace3
targets/digilent_nexys_video: Remove SATA Gen3 support (max linerate=3.75Gbps with -1 speedgrade).
2022-01-17 08:45:24 +01:00
ed04e5f95c
Merge pull request #325 from gsomlo/gls-sata-gen
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targets/digilent_nexys_video: add SATA generation argument
2022-01-17 08:41:29 +01:00
6103b3b234
targets/colorlight_5a_75x: List 8.0 in supported revision.
2022-01-17 08:27:19 +01:00
5c2d85e6a3
targets/digilent_nexys_video: add SATA generation argument
2022-01-16 19:59:36 -05:00
1077e23e62
digilent_cmod_a7: Also propagate here.
2022-01-16 11:58:14 +01:00
296c99f065
digilent_pynq_z1: Do minor cosmetic cleanups.
2022-01-14 09:39:42 +01:00
45cfe2be6b
qmtech_ecp4ce15/ecp4ce55: Merge in qmtech_ecp4cex5.
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Defaults to ecp4ce15, ecp4ce55 can be selected with --variant=ecp4ce55.
2022-01-14 09:33:29 +01:00
830757502f
Merge pull request #321 from r4d10n/master
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Support for Digilent Pynq Z1
2022-01-14 08:48:26 +01:00
a3d168e4c0
HDMI Terminal Support
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Copyright notice update.
2022-01-13 23:28:43 +05:30
e27d49114f
Add initial and minimal ZCU106 support (with Clk/Leds/UART).
2022-01-13 17:40:03 +01:00
ed50c84e0d
Support for Digilent Pynq Z1
2022-01-11 19:33:12 +05:30
c57ea732dd
Added QMTech EP4CE55 board - almost identical to EP4CE15 board but bigger FPGA.
2022-01-07 19:27:40 +00:00
8a33c2aa31
targets: Ensure litex.soc.cores.spi_flash is no longer imported/used.
2022-01-07 19:07:14 +01:00
4b6a9b2cf0
targets/spiflash: Simplify self.cpu.set_reset_address call.
2022-01-07 15:19:23 +01:00
30cacc19c2
efinix_xyloni_dev_kit: Update SPI Flash.
2022-01-07 15:00:39 +01:00
16171282c8
digilent_arty/CRG: Add with_rst parameter to be able to easily disable rst.
...
On Arty, cpu_rst pin is connected to a button but also to USB-UART which also
resets the SoC when USB-UART is connected which is in some case not wanted.
with_rst provides an easy way to disable rst by setting it to False.
2022-01-07 14:12:28 +01:00
3ebbebe750
Merge pull request #319 from antmicro/datacenter-updates
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antmicro-datacenter updates
2022-01-07 11:03:30 +01:00
8151bf7ffa
targets: Update and simplify SPI-Flash support (Address is now automatically allocated).
2022-01-07 10:34:47 +01:00
a4130556ac
gsd_butterstick: Add optional SYZYGY GPIO (--with-syzygy-gpio) to expose the 32 GPIOs on SYZYGY breakout board.
2022-01-06 18:37:42 +01:00
4ae7b5e4ff
antmicro_datacenter: extend eth reset
2022-01-06 17:40:44 +01:00
144c0dc27e
digilent_zedboard: +x.
2022-01-06 09:38:19 +01:00
28cdc8b914
spartan_edge_accelerator: Review/Simplify.
2022-01-06 09:37:46 +01:00
2c6ce12154
spartan_edge_accelerator: Add seeedstudio prefix and seeedsstudio to vendors list.
2022-01-06 09:06:27 +01:00
1ee619a455
Merge pull request #317 from primeshp/spartanacc
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Spartan Edge Accelerator Board support
2022-01-06 09:03:02 +01:00
db9173ad8b
targets/alchitry_mojo: Fix build.
2022-01-05 18:11:53 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
c836b57145
titanium_ti60_f225_dev_kit: Add HyperRAM separator.
2022-01-04 15:18:26 +01:00
28a6fad705
targets/efinix_titanium_ti60_f225: Defaults to 200MHz clock and increase HyperRam size to 32MB.
2022-01-04 11:25:18 +01:00
f5ac5200ff
Added Spartan Edge Accelerator board
2022-01-03 17:14:54 -05:00
713ae531f6
Add Spartan Edge Accelerator support
2022-01-03 16:31:13 -05:00
059563245d
Merge pull request #314 from sergachev/zedboard
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LiteX BIOS on Zedboard
2022-01-03 17:59:22 +01:00
c9816f2bc1
snicker_doodle: Add z7-10/z7-20 variants support.
2022-01-03 17:15:27 +01:00
dc61d383e6
snickerdoodle: Rename to krtkl_snicker_doodle and do minor cosmetic changes.
2022-01-03 17:09:17 +01:00
a118a0e499
Replaced Blinky with LedChaser.
2021-12-24 22:14:18 -05:00
bc3c42ab5f
zedboard: disable soc uart for all variants (zynq does not need it, for soft cpus there are no pins)
2021-12-22 03:28:13 +01:00
53ce00b3fd
zedboard: add target with bios on arm zynq cpu
2021-12-22 03:14:13 +01:00
154cb672da
Removed unused ext_freq parameter.
2021-12-20 21:42:21 -05:00
81404ff185
Improved PS7 support. Configured external clock.
2021-12-20 21:14:18 -05:00
d64207f8b6
Merge branch 'litex-hub:master' into master
2021-12-20 17:35:35 -05:00
94b4789286
Merge pull request #312 from trabucayre/arty_z7
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adding digilent_arty_z7 support
2021-12-20 21:50:41 +01:00
8772190177
Merge pull request #311 from tilk/icesugar_pro
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Option --with-spi-flash for iCESugar-Pro
2021-12-20 21:49:26 +01:00
8664b59f23
targets: Fix --bios-flash-offset support and other minor cleanups.
2021-12-20 21:41:12 +01:00
c6303480cb
Merge pull request #308 from hubmartin/tinyfpga_bx
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Fix bios-flash-offset for tinyFPGA
2021-12-20 21:29:37 +01:00
bb92bb00a8
adding digilent_arty_z7 support
2021-12-20 18:02:57 +01:00
4c76e12932
Merge branch 'litex-hub:master' into master
2021-12-20 10:54:09 -05:00
7fb225a162
Option --with-spi-flash for iCESugar-Pro
2021-12-19 15:50:52 +01:00
f18c1a033c
Efinix: ti60: add HyperRAM support
2021-12-17 10:23:10 +01:00
1c87c391c4
Initial release for Snickerdoodle
2021-12-14 16:00:42 -05:00
84f267e00c
Change bios-flash-offset for tinyFPGA
2021-12-14 19:10:03 +01:00
c2a840f777
Merge pull request #307 from fjullien/titanium_spi
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Titanium spi
2021-12-14 08:21:15 +01:00
9608cae2ee
efinix: Ti60f225 change spi_flash module
2021-12-13 23:01:48 +01:00
be7dbf3b1b
exfinix: efinix_titanium_ti60_f225_dev_kit: fix typo
2021-12-13 22:53:50 +01:00
179e9090d1
Rename efinix_titanium_ti60_bga225_dev_kit to efinix_titanium_ti60_f225_dev_kit and also exclude it from tested platforms/targets.
2021-12-13 15:54:56 +01:00
e84f32b918
efinix: add titanium Ti60 dev kit
2021-12-13 09:37:14 +01:00
35e0026875
Merge pull request #303 from sergachev/master
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sipeed_tang_nano_4k: add option to build with Gowin EMCU
2021-12-09 14:30:54 +01:00
14a8c50e97
sipeed_tang_nano_4k: connect Gowin EMCU UART, undo unnecessary changes
2021-12-09 00:17:48 +01:00
6274c4c425
sipeed_tang_nano_4k: connect Gowin EMCU UART
2021-12-09 00:12:31 +01:00
13c83ba532
sipeed_tang_nano_4k: add initial Gowin EMCU support
2021-12-08 23:50:14 +01:00
4287ab561e
sipeed_tang_nano_4k: allow non-vexriscv CPUs
2021-12-08 23:33:49 +01:00
9119250276
Merge pull request #300 from tilk/de1_soc
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Better support for DE1-SoC
2021-12-08 06:18:25 +01:00
2b7587632f
Merge pull request #299 from gregdavill/butterstick-updates
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Butterstick updates
2021-12-08 06:16:29 +01:00
8ad89881c2
fairwaves_xtrx: Add pcie_x2 definitions and switch to it.
2021-12-07 15:27:55 +01:00
cbeb2a3792
Add LedChaser to DE1-SoC
2021-12-05 20:16:10 +01:00
fd2ec534a7
butterstick: Add extra pins
2021-12-05 20:33:28 +10:30
c8a8e943b5
butterstick: add --sdram-device option
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Set 64M16 as default sdram-device.
Related to #298
2021-12-04 17:07:06 +10:30
bf8b23c19f
trenz_tec0117: Update target.
2021-12-02 18:23:11 +01:00
efa1f46356
Merge pull request #297 from sergachev/master
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Fix Sipeed Tang Nano 4k example compilation; adapt Gowin PLL class changes
2021-12-02 09:14:32 +01:00
666ef9dad3
sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs
2021-11-29 11:46:32 +01:00
2fb734a0f2
sipeed_tang_nano*: adapt Gowin PLL changes in litex
2021-11-29 11:45:13 +01:00
1829693877
fairwaves_xtrx: Integrate ICAP/SPIFlash (for update over PCIe).
2021-11-26 16:18:52 +01:00
fe14e16c1b
Merge branch 'master' into tang_primer
2021-11-23 19:04:09 +01:00
6954dd25eb
Set minimal core, since full does not work for some reason
2021-11-23 15:26:54 +01:00
0b7fabb864
FireAnt board support
2021-11-23 14:43:52 +01:00
2cc322e65d
Add initial support for Tang Primer board
2021-11-22 19:10:11 +01:00
70c0dbb185
targets/radiona_ulx3s: Remove SDRAM underflows debug pin.
2021-11-22 11:54:18 +01:00
60b769b624
efinix_trion_t120_bga576_dev_kit/ethernet: Disable software debug (RX now seems to be working fine).
2021-11-16 18:53:15 +01:00
996f5b2edd
efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC.
2021-11-16 18:12:42 +01:00
7ce6c4cf79
efinix_trion_t120_bga576_dev_kit: Switch to ctrl_type = "none" (Also seems to work fine, avoid ddr_reset_sequencer dependency).
2021-11-16 17:50:47 +01:00
99f4f97f00
efinix_trion_t120_bga576_dev_kit: Use new InterfaceWriterBlock/InterfaceWriterXMLBlock and move PLL/DRAM blocks definition to target.
2021-11-16 17:41:26 +01:00
e16fa193fc
qmtech 10cl006: remove all options which won't fit into the device. use uartbone as default
2021-11-15 10:23:01 +07:00
138dc1467e
quicklogic_quickfeather: Fix build with GPIOIn when cpu-type=None (IRQ not supported).
2021-11-14 09:30:52 +01:00
ed67b91fcc
quicklogic_quickfeather: Simplify cpu_type switch between None/EOS-S3.
2021-11-14 09:26:29 +01:00
2d3422869c
quicklogic_quickfeather: Update clocking.
2021-11-14 09:19:19 +01:00
df468fcf85
quicklogic_quickfeather: Avoid add_csr calls (not required).
2021-11-14 08:54:49 +01:00
06bae58f48
efinix_trion_t120_bga576: Do a bit a of cleanup on LPDDR3 now that working.
2021-11-12 19:43:28 +01:00
86f6d7e66b
efinix_trion_t120_bga576_dev_kit: Remove test command.
2021-11-12 18:06:11 +01:00
4e03f66fad
efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets.
...
Also lower sys_clk_freq since seems to cause issue with DRAM at 100MHz: Needs to be investigated.
2021-11-12 18:04:30 +01:00
77fffda9cd
efinix_trion_t120_bga576_dev_kit: Switch to UARTBone, Add LiteScope on Pseudo-AXI, fix addressing and do first successful LPDDR3 accesses :)
2021-11-12 16:41:42 +01:00
648d38da7e
quicklogic_quickfeather: add button and GPIOIn
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2021-11-12 13:21:00 +01:00
b6c5a85b98
Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash.
...
Tested with:
./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Nov 12 2021 08:37:48
BIOS CRC passed (2bec12a3)
Migen git sha1: 7507a2b
LiteX git sha1: f679992f
--=============== SoC ==================--
CPU: VexRiscv @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
FLASH: 4096KiB
--========== Initialization ============--
Initializing W25Q32JV SPI Flash @0x00400000...
Enabling Quad mode...
First SPI Flash block erased, unable to perform freq test.
Memspeed at 0x400000 (Sequential, 4.0KiB)...
Read speed: 2.6MiB/s
Memspeed at 0x400000 (Random, 4.0KiB)...
Read speed: 1.5MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-11-12 08:42:10 +01:00
d6fc4b412e
efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied).
2021-11-12 07:58:51 +01:00
7ce8567d9b
targets/efinix: Bitstreams now directly generated to gateware directory.
2021-11-11 11:19:39 +01:00
855fd7e3d7
efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration...
2021-11-10 19:40:35 +01:00
224f527baa
efinix_trion_t120_bga576_dev_kit: Go a bit further in DRAM integration.
2021-11-10 12:07:30 +01:00
040e7b3104
quicklogic_quickfeather: Use initial EOS-S3 support/integration.
2021-11-09 18:59:37 +01:00
8ce83ce92f
efinix_trion_t120_bga576_dev_kit: Add inital LPDDR3 integration (not yet working).
2021-11-09 16:13:40 +01:00
9a7e5f40b4
efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support.
...
Still not fully validated: TX seems OK but RX seems shifted/corrupted.
2021-11-09 11:32:32 +01:00
ccebae6f55
targets/hyperram: Update integration.
2021-11-08 16:39:49 +01:00
184f41e61a
sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds).
...
Working correctly on hardware with updated CH552 firmware & patched litex_server...
2021-11-08 09:23:44 +01:00
d6bf2fd00e
terasic_sockit: Use standard SDRAM module from litedram
2021-11-08 12:48:03 +07:00
a9847f15a7
qmtech_5cefa2: tuned the clock phase shift to be able to run the system at 105MHz
2021-11-06 09:58:10 +07:00
b2813cfb70
use the right DRAM chip for the QMTech Altera boards
2021-11-06 08:45:03 +07:00
6e7c76b71e
fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when no PCIe.
...
Fixes CI.
2021-11-05 15:22:55 +01:00
ceaaf67dfd
Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).
2021-11-05 14:52:45 +01:00
01463a81a4
Merge pull request #287 from hansfbaier/qmtech-fixes
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10cl006: add missing spiflash option
2021-11-05 07:11:27 +01:00
3a25af1c28
10cl006: add missing spiflash option
2021-11-05 09:57:04 +07:00
0edce3a176
Add support for QMTech 5CEFA2 board (Cyclone V)
2021-11-05 09:53:25 +07:00
a482d7f6de
targets/qmtech_xc7a35t: Use gpio_serial as serial when not mounted on daughterboard.
2021-11-04 18:52:36 +01:00
9543b5efae
marble/marble_mini: Add berkeleylab prefix.
2021-11-04 18:42:16 +01:00
5e5ae880a4
targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel.
...
Tested with:
./litex_acorn_baseboard.py --cpu-type=None --uart-name=uartbone --with-ws2812 --build --csr-csv=csr.csv --load
litex_server --uart --uart-port=/dev/ttyUSBX
And test script: https://gist.github.com/enjoy-digital/c32c679a9ee4429d7f38a5ca5016a45a
2021-11-04 16:36:25 +01:00
808befec3b
Merge pull request #283 from yetifrisstlama/master
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add Marble-board platform and target file
2021-11-04 15:20:11 +01:00
7aa639ac0f
QMTech boards: fix swapped RX/TX lines, remove double uart replacer
2021-11-02 09:34:25 +07:00
e645eb243b
add marble board platform and target file
2021-10-28 18:41:22 +02:00
207afb98fc
ego1: Switch to VideoTerminal (LiteVideo is no longer provided by default with LiteX).
2021-10-27 16:29:46 +02:00
91818bc5f0
targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments).
2021-10-26 17:01:55 +02:00
c7a91f9eab
efinix: Enable identifier on SoC (issue fixed in LiteX).
2021-10-25 19:33:49 +02:00
4bcfde8882
efinix: Avoid no_we on ROM/RAMs (no longer required).
2021-10-25 19:10:03 +02:00
d13a8d54b8
efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit.
...
Now possible with recent LiteX changes to support Tristate IOs.
2021-10-25 18:35:35 +02:00
f230eaf9bc
efinix_trion_t120_bga576: Add Tristate test code.
2021-10-25 15:01:34 +02:00
0ac0f9e75d
efinix_xyloni_dev_kit: Switch to openFPGALoader to load bitstream.
2021-10-25 12:49:48 +02:00
fc05379929
efinix_xyloni_dev_kit: Use PLL.
2021-10-25 12:16:47 +02:00
394ea23b99
efinix_xyloni_dev_kit: Only force variant to minimal for Vexriscv.
2021-10-22 14:47:12 +02:00
75fd276dbe
efinix_xyloni_dev_kit: Increase similarities with others boards and make target very similar to iceBreaker/Fomu/TangNano4k.
2021-10-21 11:34:55 +02:00
dc1328f1a5
efinix_xyloni_dev_kit: Fix copyrights.
2021-10-21 10:12:46 +02:00
012c1d9705
efinix_trion_t20: Minor changes (move serial to platform, fix platform copyright).
2021-10-21 10:10:35 +02:00
0cf9793be5
Merge pull request #282 from AndrewD/master
...
efinix: xyloni dev board basic support
2021-10-21 10:06:25 +02:00
7525132907
litex_acorn_baseboard/video: Switch to 800x600@60Hz.
2021-10-19 16:34:28 +02:00
c548b1c1e2
efinix: xyloni dev board basic support
...
* This works: efinix_xyloni_dev_kit.py --cpu-type None --build --load --flash
* issues with SPIflash - wrong generation for tristates miso mosi for
some reason
2021-10-19 11:23:29 +11:00
a53f17380f
Merge pull request #271 from antmicro/add-data-center-board
...
WIP: boards: added datacenter DDR4 RDIMM tester board
2021-10-18 13:36:37 +02:00
a4d330dd2c
Merge pull request #279 from mmicko/efinix_t20_flash
...
Enable writing to flash for T20
2021-10-15 18:38:08 +02:00
3730d96709
litex_acorn_baseboard: Add SPIFlash support.
2021-10-15 18:22:08 +02:00
1f65d37121
Enable writing to flash for T20
2021-10-15 16:44:35 +02:00
d9638c40b8
Initial support for Efinix Trion T20 BGA256 Dev Kit
2021-10-15 12:26:15 +02:00
914e330a86
efinix_trion_t120_bga576_dev_kit: Add Flash support (Through openFPGALoader).
2021-10-15 09:38:43 +02:00
195bf176cf
efinix_trion_t120_bga576: Add SPIFlash support (X1 for now).
2021-10-14 19:16:01 +02:00
03c34e31cd
efinix_trion_t120_bga576: Add PLL to CRG and increase default sys_clk to 100MHz.
2021-10-14 15:45:26 +02:00
2ea803b7d1
efinix_trion_t120_bga576: Set no_we on integrated_main_ram.
...
To allow --integrated-main-ram-size use.
2021-10-14 10:19:18 +02:00
430918756d
efinix_trion_t120_bga576: Add PMODs connectors and use USB-UART/PMOD_E as Serial.
2021-10-14 10:10:42 +02:00
36897f4646
efinix_trion_t120_bga576: Disable Identifier (crashes design) and move no_we, working.
...
./efinix_trion_t120_bga576_dev_kit.py --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS CRC passed (b23a7321)
Migen git sha1: 7507a2b
LiteX git sha1: 8316fbf1
--=============== SoC ==================--
CPU: VexRiscv @ 40MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-10-14 09:39:54 +02:00
ad773b6f2f
efinix_trion_t120_bga576: Fix argparse description.
2021-10-13 17:28:43 +02:00
6c17d76a92
targets/efinix_trion_t120_bga576: Switch to SoCCore (with CPU) and use button as reset (and AsyncResetSynchronizer).
2021-10-13 16:35:14 +02:00
a4d178a740
Add Efinix Trio T120 BGA576 Dev-Kit initial support (LedChaser).
2021-10-13 12:29:53 +02:00
83e64fbd64
targets/qmtech_10cl006: +x.
2021-10-13 12:16:41 +02:00
e29bcd30a6
litex_acorn_baseboard: Add some M2 signals and set devslp to 0.
2021-10-12 11:54:17 +02:00
a365362f5d
Rename litex_m2_baseboard to litex_acorn_baseboard and add link to repository.
2021-10-11 18:36:12 +02:00
fe08491e8d
litex_m2_baseboard: Add LCD.
2021-10-11 18:30:23 +02:00
393252ddc9
Merge pull request #277 from hansfbaier/master
...
Add support for QMTech 10CL006 board
2021-10-11 14:01:06 +02:00
79fe4a9199
Merge pull request #275 from alainlou/master
...
rz_easyfpga: cleanup and ease of use
2021-10-11 13:57:06 +02:00
2b2c7d3d68
trellisboard: Add PMOD GPIO support (for tests with MicroPython).
2021-10-11 11:33:13 +02:00
9e18d9bc34
gsd_butterstick: Remove ECLKBRIDGECS (not required).
2021-10-07 14:09:22 +02:00
d119b598c5
Add support for QMTech 10CL006 board
2021-10-05 12:06:41 +07:00
1b676f929a
cleanup and ease of use
...
- update README
- delete some unnecessary toolchain commands (copied from trenz boards)
- use minimal cpu_variant by default when vexriscv is selected
2021-10-03 13:21:45 -04:00
e8611794b4
Add initial QuickLogic QuickFeather support (Led Chaser).
...
Untested.
2021-10-01 10:58:26 +02:00
de4ad324cb
mnt_rkx7: Revert default sys_clk_freq to 100MHz.
2021-09-30 18:03:22 +02:00
1858273945
mnt_rkx7: Add SPI SDCard support.
2021-09-30 18:01:54 +02:00
05f3158311
mnt_rkx7: Increase default sys_clk_freq to 125MHz.
2021-09-30 16:22:18 +02:00
1217e94218
mnt_rkx7: Switch DDR3 to IS43TR16512B now added to LiteDRAM.
2021-09-30 15:45:40 +02:00
9bcae49629
mnt_rkx7: Add I2C (For the SiI9022A).
2021-09-30 15:33:53 +02:00
4f7c18a503
mnt_rkx7: Add Ethernet/Etherbone support.
2021-09-30 15:14:03 +02:00
84f0d715ff
mnt_rkx7: Add SDCard support.
2021-09-30 11:34:23 +02:00
31b404c42f
mng_rkx7: Add SPI Flash support.
2021-09-30 11:29:56 +02:00
df7fe5687e
Add initial MNT Reform Kintex-7 module (RKX7) support with Clk, UART and DDR3.
...
Compiles but untested on hardware.
2021-09-30 11:06:39 +02:00
82653cf66f
icebreaker/fomu: Fix SPRAM split.
2021-09-30 09:32:26 +02:00
5addd7f7d8
icebreaker/fomu: Split PSRAM in half: 64kB SRAM/64kB RAM).
...
Allows building bare metal demo and running it directly on these boards.
2021-09-29 19:33:22 +02:00
dfa572083a
Merge pull request #273 from ozbenh/wukong-v2
...
Wukong board improvements
2021-09-28 13:22:42 +02:00
228245075a
boards: added datacenter DDR4 RDIMM tester board
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-09-27 10:15:55 +02:00
4a52996106
Wukong board improvements
...
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.
Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.
This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-24 12:13:56 +10:00
f18b10d1ed
Merge pull request #249 from Quiddle11/atlys
...
Initial Digilent Atlys support
2021-09-23 10:21:49 +02:00
921c300b50
digilent_atlys: Simplify/Remove entropy...
...
Build tested with ./digilent_atlys.py --with-ethernet --build.
2021-09-23 10:17:54 +02:00
1333f89ed6
rz_easyfpga: adjust SDRAM clk phase
...
- also add 1:2 rate
2021-09-22 00:26:28 -04:00
610e82d774
Add initial RZ-EasyFPGA support! ( #270 )
2021-09-21 09:55:22 +02:00
5190c9c869
sipeed_tang_nano_4k: Initial Video Out support.
...
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
2021-09-20 09:32:20 +02:00
30756ce05e
targets: Update to VideoHDMIPHY.
2021-09-20 09:30:32 +02:00
7161ad18ec
sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL.
2021-09-20 08:40:19 +02:00
a5c5ba7652
sipeed_tang_nano_4k: Integrate HyperRam (not yet working).
2021-09-17 16:30:39 +02:00
376a836583
sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.
...
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 17 2021 15:54:08
BIOS CRC passed (6cc6de6d)
Migen git sha1: a5bc262
LiteX git sha1: 46cd9c5a
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 27MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
FLASH: 4096KiB
--========== Initialization ============--
Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
Read speed: 521.9KiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-09-17 15:57:55 +02:00
28571308bc
sispeed_tang_nano: Add simple UART loopback test... (Not working...)
2021-09-16 19:34:48 +02:00
5955a35372
Add initial Sipeed Tang Nano support (Clk/Leds/Buttons).
2021-09-16 19:22:30 +02:00
c0aed8a727
litex_m2_baseboard: Add Video Terminal support.
2021-09-16 18:54:50 +02:00
32a9256f3b
litex_m2_baseboard: Add SDCard support.
2021-09-16 18:17:34 +02:00
0854a5d234
litex_m2_baseboard: Add Ethernet/Etherbone support.
2021-09-16 18:02:55 +02:00
3ad0eb6992
Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons.
2021-09-16 17:44:50 +02:00
26943959b5
Merge pull request #268 from trabucayre/runber_support
...
Add runber support
2021-09-15 08:32:05 +02:00
7ccae3332d
Add runber support
2021-09-15 06:50:57 +02:00
68fb163a27
targets: Remove spiflash mapping on targets where it's no longer useful.
2021-09-14 18:35:13 +02:00
db91eda899
linsn_rv901t.py: Update Ethernet and add Etherbone support.
2021-09-13 19:35:05 +02:00
b8373a361d
alchitry_mojo: new board
2021-09-10 02:40:31 -07:00
cacb76450f
Merge pull request #264 from teknoman117/alchitry-au
...
Add Alchitry Au as new board
2021-09-09 11:42:37 +02:00
8d91489756
tang_nano_4k: Add more IOs.
2021-09-09 11:23:20 +02:00
9bbdb87130
alchitry_au: new board
2021-09-09 00:03:19 -07:00
88534c6689
tang_nano_4k: Fix typo in sipeed.
2021-09-08 23:02:39 +02:00
ce52c8c5ed
beaglewire: Fix typo in qwertyembedded.
2021-09-08 21:29:29 +02:00
ecebe7e267
Add initial SiSpeed Tang Nano 4K support (Led blink only for now...).
...
./sispeed_tang_nano_4k.py --build --load
Build with Gowin EDA.
Load with OpenFPGALoader.
2021-09-08 19:36:46 +02:00
129b95f9b5
sqrl_acorn: Update pre_placement_commands with new XilinxVivadCommands.
2021-09-08 16:27:30 +02:00
7fa22a494b
arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).
...
On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
2021-09-07 15:07:59 +02:00
aa2209729f
gsd_butterstick: Force uart_name to crossover when set to serial.
2021-09-02 15:23:05 +02:00
fddca1cd40
gsd_butterstick: Add SDCard (SPI & SD modes) support.
2021-09-02 14:06:09 +02:00
596f430326
gsd_butterstick: Add SPI Flash support.
2021-09-02 11:28:21 +02:00
55ea71bd01
gsd_butterstick: Add initial DDR3 support.
...
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 1 2021 19:09:52
BIOS CRC passed (3d349845)
Migen git sha1: 27dbf03
LiteX git sha1: 315fbe18
--=============== SoC ==================--
CPU: VexRiscv @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 15.6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-09-01 19:21:16 +02:00
1f25a98476
butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone).
2021-09-01 18:03:13 +02:00
1f149ece6b
Add intial ButterStick support (with just Clk, Buttons and Leds).
2021-09-01 17:33:54 +02:00
74c2178150
lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL
...
Setting MASTER_SPI_PORT=SERIAL causes the SPI flash pins to be reserved
for use by the sysCONFIG logic, and prevents user logic from assigning
them. This made it impossible to have a Litex design which accesses the
SPI flash on this board.
Remove the setting, so that we get the default behaviour which permits
user logic to assign these pins. In the unlikely event that someone
needs the pins to stay reserved for sysCONFIG after configuration (I'm
not sure why this would be needed) they could explicitly add this
command in their design.
2021-09-01 18:47:17 +10:00
4731c500fb
Merge pull request #258 from danc86/clnexevn-device-arg
...
lattice_crosslink_nx_evn: allow specifying the FPGA device
2021-09-01 10:22:42 +02:00
ce254208ff
beaglewire: Review/Cleanup for consistency with other targets.
...
- Now uses regular UART.
- Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build
- Can still be build with Crossover UART with --uart-name=crossover+bridge.
2021-09-01 10:18:11 +02:00
35df77258a
beaglewire: Rename to quertyembedded_beaglewire.
2021-09-01 09:36:09 +02:00
1e1f6a476d
Merge pull request #254 from ombhilare999/master
...
beaglewire platform and target added
2021-09-01 09:33:07 +02:00
4a18951651
tul_pynq_z2: Fix copyrights, remove PS7 part for now.
2021-09-01 08:50:56 +02:00
54c777a49c
Merge pull request #252 from developandplay/PYNQ-Z2
...
WIP: Initial PYNQ Z2 support
2021-09-01 08:46:44 +02:00
8f1c15bdb8
ebaz4205: Remove PS7 support for now (since untested and we'll avoid the .xci in LiteX-Boards repository).
2021-08-31 18:56:47 +02:00
781d83bab6
Add support for EBAZ4205 'Development' Board
...
Usage:
```
./ebaz4205.py --cpu-type=vexriscv --build --load
```
```
$ pwd
litex-boards/litex_boards/targets
```
Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.
References:
- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example
Note: The `PS7` stuff remains untested via LiteX for now.
2021-08-31 18:54:49 +02:00
b017a33f2b
targets: Fix SPI Flash mapping on target supporting --with-spi-flash.
2021-08-23 18:05:40 +02:00
cc9e39286a
lattice_crosslink_nx_evn: allow specifying the FPGA device
...
This board is documented as having the LIFCL-40-9BG400C part, but some
versions of the board exist which were fitted with LIFCL-40-8BG400CES,
an engineering sample part. The distinction is important because the
engineering sample requires a different device ID to be embedded in the
bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load
it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red
"INITN" LED on this board).
Accept --device to allow the user to specify which FPGA part their board
has.
2021-08-17 18:30:03 +10:00
db9c98b28a
beaglewire platform and target added
2021-08-16 20:14:45 +05:30
22e823d756
Initial PYNQ Z2 support
2021-08-13 16:23:39 +02:00
b77b1514ce
Merge pull request #250 from david-sawatzke/fullmemwe
...
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
2021-08-11 09:53:47 +02:00
9f5e8d4864
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
...
Leads to an increase in DP16KD, first noticed in
https://github.com/enjoy-digital/liteeth/issues/70 .
With full_mem_we:
```
Info: DP16KD: 41/ 56 73%
```
Without:
```
Info: DP16KD: 29/ 56 51%
```
2021-08-08 14:37:46 +02:00
Gwenhael Goavec-Merou
Florent Kermarrec
Victor Suarez Rovere
Ilia Sergachev
Tim Callahan
Icenowy Zheng
vacajk
Bastian Löher
Gabriel Somlo
Rakesh Peter
Alastair M. Robinson
Karol Gugala
Primesh
Derek Mulcahy
derekmulcahy
Marek Materzok
Franck Jullien
hubmartin
Ilia Sergachev
Greg Davill
Miodrag Milanovic
Hans Baier
Michael Betz
Andrew Dennison
alainlou
Alessandro Comodi
Benjamin Herrenschmidt
Nathaniel R. Lewis
Dan Callaghan
Dhiru Kholia
ombhilare999
Martin Troiber
David Sawatzke