Commit Graph

  • bd1cc3466f Updated eval data Clifford Wolf 2015-07-08 09:48:42 +0200
  • b6c4c2eeb9 Added TWO_CYCLE_COMPARE Clifford Wolf 2015-07-07 22:51:52 +0200
  • 54f89ba904 Updated RV32I tools instructions Clifford Wolf 2015-07-05 10:32:26 +0200
  • 8d404182b3 Improved IceStorm example script Clifford Wolf 2015-07-04 16:34:18 +0200
  • 4601fa23e9 Added -Werror Clifford Wolf 2015-07-04 16:31:26 +0200
  • 21da66db68 c++/c99-style for loops in firmware Clifford Wolf 2015-07-04 11:47:43 +0200
  • 91f75bdf1f Turned gcc warnings up to eleven Clifford Wolf 2015-07-04 11:47:19 +0200
  • 2df7aadc7a Fixed typo in Makefile Clifford Wolf 2015-07-03 18:43:37 +0200
  • 9c028fc965 Added missing LD_RS1 debug statements Clifford Wolf 2015-07-02 14:51:28 +0200
  • 686f77facb Updated area and timing stats Clifford Wolf 2015-07-02 14:41:15 +0200
  • ab503d5756 Being more aggressive with parallel cases Clifford Wolf 2015-07-02 12:55:05 +0200
  • c10125eb5c Added TWO_STAGE_SHIFT parameter Clifford Wolf 2015-07-02 12:29:06 +0200
  • 853ce91300 Added `debug macro Clifford Wolf 2015-07-02 12:17:45 +0200
  • 476046c177 Minor Makefile changes Clifford Wolf 2015-07-02 11:01:21 +0200
  • b6e8c15901 Removed trailing whitespaces in dhrystone code Clifford Wolf 2015-07-02 10:50:54 +0200
  • c48a3b2434 Removed trailing whitespaces Clifford Wolf 2015-07-02 10:49:35 +0200
  • 084056f729 Unsigned arguments for print_dec() Clifford Wolf 2015-07-02 10:46:21 +0200
  • a7f9b7fbf3 Some testbench-related improvements Clifford Wolf 2015-07-02 10:45:35 +0200
  • 9d3b0a9692 Updated evaluation Clifford Wolf 2015-07-02 00:54:11 +0200
  • 198c995c8f Back to Vivado 2015.1 Clifford Wolf 2015-07-01 22:42:25 +0200
  • 84e2202fef Vivado 2015.2 area evaluation Clifford Wolf 2015-07-01 22:18:20 +0200
  • e72abc0284 Added vivado synth_area_{small,regular,large}.tcl scripts Clifford Wolf 2015-07-01 21:51:15 +0200
  • 553b1ef143 Updated Xilinx 7-Series area stats Clifford Wolf 2015-07-01 21:48:51 +0200
  • 34193bf9df Added CATCH_MISALIGN and CATCH_ILLINSN Clifford Wolf 2015-07-01 21:20:51 +0200
  • f6fe27ecbf After some profiling: one-hot FSM encoding Clifford Wolf 2015-07-01 21:20:31 +0200
  • c22ea8fe0a Spelling fixes by Larry Doolittle Clifford Wolf 2015-07-01 08:18:10 +0200
  • 4a9fda0737 Improvements in PCPI MUL core Clifford Wolf 2015-06-30 16:51:26 +0200
  • 9d809eb0d9 Added TOC to README Clifford Wolf 2015-06-30 12:25:05 +0200
  • 997c5ce341 Added "make test_synth" Clifford Wolf 2015-06-30 01:46:25 +0200
  • 56b2b4971d Added Note about Icarus Verilog to README Clifford Wolf 2015-06-29 09:58:39 +0200
  • 7417a3e249 Added LATCHED_IRQ parameter Clifford Wolf 2015-06-29 07:54:47 +0200
  • 1321840665 Minor README change Clifford Wolf 2015-06-29 07:37:48 +0200
  • 46026ba985 Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMER Clifford Wolf 2015-06-28 22:09:51 +0200
  • e5e5494ca2 Improved start.S IRQ code Clifford Wolf 2015-06-28 20:52:52 +0200
  • 21157b8f1d Cleanups in PCPI interface Clifford Wolf 2015-06-28 15:41:55 +0200
  • e34dcf77e3 Fixed typo in firmware/start.S Clifford Wolf 2015-06-28 14:56:26 +0200
  • b076d72806 Fixed PCPI instr prefetching Clifford Wolf 2015-06-28 14:51:53 +0200
  • 094dc690bb Added resource utilization to xilinx eval Clifford Wolf 2015-06-28 13:49:36 +0200
  • 1f99de5117 Improvements in picorv32_pcpi_mul Clifford Wolf 2015-06-28 13:07:50 +0200
  • 923ac360ff More README stuff Clifford Wolf 2015-06-28 12:20:23 +0200
  • 4c15e05298 Moved ENABLE_MUL from picorv32_axi to picorv32 Clifford Wolf 2015-06-28 12:19:49 +0200
  • 818faffe25 Improved IRQ documentation, added assembler macros Clifford Wolf 2015-06-28 02:10:45 +0200
  • 792baeabcf Minor README changes Clifford Wolf 2015-06-28 01:18:19 +0200
  • df6b95fb87 Various README updates Clifford Wolf 2015-06-27 23:54:52 +0200
  • 034e1a6af7 Added PCPI to picorv32_axi Clifford Wolf 2015-06-27 23:54:11 +0200
  • 7d1a484812 Implemented picorv32_pcpi_mul Clifford Wolf 2015-06-27 23:53:51 +0200
  • ef8796de45 Minor vivado script changes Clifford Wolf 2015-06-27 23:05:00 +0200
  • d0100f72b5 Added ENABLE defines for individual tests Clifford Wolf 2015-06-27 22:31:24 +0200
  • 7b17773bfc Added mul tests from riscv-tests Clifford Wolf 2015-06-27 22:18:24 +0200
  • dee66e136e Added "make table.txt" vivado scripts Clifford Wolf 2015-06-27 13:55:33 +0200
  • 2bd43fff68 Updated TODOs Clifford Wolf 2015-06-26 23:56:43 +0200
  • 44571601c1 Added "make test_sp" Clifford Wolf 2015-06-26 23:54:12 +0200
  • 617fa9d80a Added PCPI to README Clifford Wolf 2015-06-26 23:49:16 +0200
  • dd8ed3c877 Added pcpi_wait interface Clifford Wolf 2015-06-26 23:48:50 +0200
  • 60fdba89d0 Updated vivado scripts Clifford Wolf 2015-06-26 23:41:13 +0200
  • 0be990bd04 Added Pico Co-Processor Interface (PCPI) Clifford Wolf 2015-06-26 23:14:38 +0200
  • d4331491a8 Test firmware refactoring Clifford Wolf 2015-06-26 22:02:22 +0200
  • f0b824ad9a Minor README changes Clifford Wolf 2015-06-26 16:15:39 +0200
  • c06286423b Added build instructions for RV32I toolchain Clifford Wolf 2015-06-26 13:48:16 +0200
  • f87d81287c More README changes Clifford Wolf 2015-06-26 11:01:34 +0200
  • 266ff03539 Minor README changes Clifford Wolf 2015-06-26 10:51:15 +0200
  • 1a664f9b97 Changed chip package in vivado examples Clifford Wolf 2015-06-26 10:46:51 +0200
  • 5d4ce82050 Implemented waitirq instruction Clifford Wolf 2015-06-26 10:39:08 +0200
  • 9a4a06d981 Refactoring of IRQ handling Clifford Wolf 2015-06-26 10:03:37 +0200
  • 9d26ebcf58 Improvements in README.md Clifford Wolf 2015-06-25 14:11:42 +0200
  • 23b700cf73 Added basic IRQ support Clifford Wolf 2015-06-25 14:08:39 +0200
  • 982e5cc600 Added simple icestorm script (not a real example yet) Clifford Wolf 2015-06-22 11:35:48 +0200
  • 8590c7d2a8 Updated Vivado SoC example Clifford Wolf 2015-06-10 16:48:06 +0200
  • 26127b45de Makefile for Vivado scripts Clifford Wolf 2015-06-09 12:45:45 +0200
  • b4b1d03b1c More Todos Clifford Wolf 2015-06-09 10:01:00 +0200
  • bb7f500489 Removed unnecessary "jal" complexity Clifford Wolf 2015-06-09 07:40:30 +0200
  • 0257d2cb08 Small improvements in vivado_soc demo Clifford Wolf 2015-06-08 19:58:28 +0200
  • 072e5ca2c5 Added osu018 yosys synthesis script Clifford Wolf 2015-06-08 09:31:56 +0200
  • a9532f81ed Refactored instruction decoder Clifford Wolf 2015-06-08 08:59:40 +0200
  • 32208c0b70 Improved timing for "decoded_imm_uj" Clifford Wolf 2015-06-07 22:50:49 +0200
  • 06ba3a1a57 README Updates Clifford Wolf 2015-06-07 20:59:20 +0200
  • 34d9dea8c7 Added support for dual-port register file Clifford Wolf 2015-06-07 20:53:19 +0200
  • 60867e10a9 minor optimizations Clifford Wolf 2015-06-07 20:08:04 +0200
  • 8e3e0bfba0 Improved "decoder_trigger" handling Clifford Wolf 2015-06-07 19:49:38 +0200
  • bbbcea2faa Added look-ahead write interface Clifford Wolf 2015-06-07 12:11:20 +0200
  • e84f044bc5 Major redesign of main FSM Clifford Wolf 2015-06-07 08:28:10 +0200
  • 491cd5e15d Using libc assembler code in dhrystone stdlib.c Clifford Wolf 2015-06-07 07:29:13 +0200
  • 44ea992fed Updated CPI table in README Clifford Wolf 2015-06-06 21:43:33 +0200
  • 90ff3380a4 Updated README Clifford Wolf 2015-06-06 21:27:58 +0200
  • 2107a328c4 Added insn timing hack to dryhstone testbench Clifford Wolf 2015-06-06 21:27:07 +0200
  • bc8ffd2ecb Added memory "look-ahead" read interface Clifford Wolf 2015-06-06 20:40:58 +0200
  • 9df9d7ff90 Improved Xilinx example Clifford Wolf 2015-06-06 20:14:58 +0200
  • abe0465753 Faster memory model in dhrystone testbench Clifford Wolf 2015-06-06 19:35:07 +0200
  • c55d537401 Improved AXI tests Clifford Wolf 2015-06-06 19:22:28 +0200
  • f9ae73066b Added license info to README Clifford Wolf 2015-06-06 17:24:11 +0200
  • 7fd24a96b2 Improved AXI Interface Testbench Clifford Wolf 2015-06-06 17:15:09 +0200
  • 77ba5a1897 Initial import Clifford Wolf 2015-06-06 14:01:37 +0200