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885 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
fa6d96bb9a test/examples: do not attempt to run deleted examples 2015-09-12 15:13:45 +08:00
Sebastien Bourdeauducq
7bd72a16df sim: support clock domains without sync 2015-09-12 15:12:57 +08:00
Sebastien Bourdeauducq
fd986210f8 simulator: support generators 2015-09-10 21:44:14 -07:00
Sebastien Bourdeauducq
10d89d81f4 new simulator: basic execution 2015-09-10 20:33:45 -07:00
Sebastien Bourdeauducq
49ef182305 fhdl/tools: add input lister 2015-09-10 20:33:10 -07:00
Sebastien Bourdeauducq
f9849fb8be style 2015-09-10 20:32:47 -07:00
Sebastien Bourdeauducq
714ae43ab8 fhdl: remove features new simulator won't use 2015-09-10 18:29:57 -07:00
Sebastien Bourdeauducq
91ab3f0d01 remove genlib.misc.optree (use reduce instead) 2015-09-10 13:56:56 -07:00
Yves Delley
1dcd2ac1c0 fixed bug in value_bits_sign of mul operatiors 2015-09-10 10:53:26 -07:00
Sebastien Bourdeauducq
86f34e82c3 mibuild -> migen.build 2015-09-10 10:53:15 -07:00
Sebastien Bourdeauducq
f1dc008d32 Simulator will be rewritten 2015-09-05 15:07:00 -06:00
Sebastien Bourdeauducq
dec2e23fc7 Remove code that will be into MiSoC or other packages. 2015-09-05 15:06:04 -06:00
Florent Kermarrec
5253b0c06e migen/actorlib/packet: fix source.error in Depacketizer 2015-08-19 01:12:07 +02:00
Florent Kermarrec
646667213e migen/flow/actor: fix sop/eop validation in PipelinedActor (stb can be inactive when pipe_ce is active) 2015-08-09 19:54:38 +02:00
Sebastien Bourdeauducq
f32f9be17a resetless -> reset_less 2015-07-27 11:46:11 +08:00
Sebastien Bourdeauducq
cc6877df9e fhdl: allow use of ResetSignal() on resetless clock domains 2015-07-27 01:51:52 +08:00
Sebastien Bourdeauducq
5a535ef347 Revert "migen/actorlib/fifo: add FIFO wrapper function" 
This reverts commit d0a19c4be8.
 2015-07-24 19:25:36 +08:00
Florent Kermarrec
d0a19c4be8 migen/actorlib/fifo: add FIFO wrapper function 
Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
 2015-07-24 13:02:54 +02:00
Florent Kermarrec
1f1ff5a5e9 migen/fhdl/tools: fix rename_clock_domain when new == old 
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
 2015-07-24 12:48:51 +02:00
Florent Kermarrec
5713ae381a actorlib/packet/Depacketizer: manage layouts without error signal 2015-07-22 21:43:21 +02:00
Florent Kermarrec
d77a5fc5ac fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
Florent Kermarrec
71627cf9f0 bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant) 2015-06-19 08:37:16 +02:00
Florent Kermarrec
f8b1152b98 wishbone: add Cache (from WB2LASMI) 2015-06-17 15:31:49 +02:00
Florent Kermarrec
33b536e505 migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter) 2015-06-02 19:29:38 +02:00
Florent Kermarrec
79624ce849 migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters) 2015-06-02 19:26:42 +02:00
Sebastien Bourdeauducq
fd16b66bdf genlib/cdc: add BusSynchronizer 2015-06-02 17:40:42 +08:00
Florent Kermarrec
a5f495aeac fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
Florent Kermarrec
9cabcf14e9 migen/genlib/record: add leave_out parameter to connect 
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
 2015-05-23 13:59:09 +02:00
Florent Kermarrec
f6624b34f0 migen/actorlib/spi: apply missing CSR renaming 2015-05-13 10:17:31 +02:00
Florent Kermarrec
76302d7aa6 vpi: cleanup (thanks sb) 2015-05-13 10:13:14 +02:00
Florent Kermarrec
98cf103c65 vpi: fix and simplify windows simulation (ends of msg were ignored) 2015-05-13 03:03:34 +02:00
Florent Kermarrec
88a406ebec migen/genlib/misc: replace Timeout with WaitTimer from artiq 2015-05-12 16:14:58 +02:00
William D. Jones
fe6eef7069 Windows simulation support 2015-05-09 21:09:52 +08:00
Alain Péteut
96bff77c36 add examples tests 2015-05-01 00:50:17 +08:00
Florent Kermarrec
1cbc468bda migen/actorlib/packet: add Packetizer and Depacketizer 2015-04-28 18:44:05 +02:00
Florent Kermarrec
0da9311d70 migen/genlib: avoid use of floating point in reverse_bytes 2015-04-27 21:04:18 +02:00
Florent Kermarrec
3ce5ff3722 migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer) 2015-04-27 15:14:38 +02:00
Florent Kermarrec
f976b1916a migen/actorlib/misc: add BufferizeEndpoints 
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
 2015-04-27 15:12:01 +02:00
Florent Kermarrec
e96ba1e46f migen/genlib/misc: add reverse_bytes 2015-04-27 15:08:10 +02:00
Florent Kermarrec
73a1687562 migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?) 2015-04-24 13:24:52 +02:00
Florent Kermarrec
67702f25ab migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb) 2015-04-24 12:54:08 +02:00
Florent Kermarrec
bc30fc57e7 migen/fhdl: give explicit names to syntax specialization when asic_syntax is used 2015-04-24 12:14:14 +02:00
Florent Kermarrec
61c3efc5f5 migen/test: rename asic_syntax to test_syntax and simplify 2015-04-24 12:00:46 +02:00
Guy Hutchison
7ec0ecae11 test: add test for asic_syntax 2015-04-22 12:29:07 +08:00
Guy Hutchison
28dde1e38f fhdl/verilog: add flag to produce ASIC-friendly output 2015-04-21 09:52:14 +08:00
Florent Kermarrec
3f15699964 revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue) 2015-04-13 21:47:55 +02:00
Florent Kermarrec
d83e170872 global: more pep8 
we will have to continue the work... volunteers are welcome :)
 2015-04-13 21:33:44 +02:00
Florent Kermarrec
f97d7ff44c global: pep8 (E261, E271) 2015-04-13 21:21:30 +02:00
Florent Kermarrec
5f225c0475 global: pep8 (E225) 2015-04-13 21:11:13 +02:00
Florent Kermarrec
37ef9b6f3a global: pep8 (E231) 2015-04-13 20:50:03 +02:00
Florent Kermarrec
1051878f4c global: pep8 (E302) 2015-04-13 20:45:35 +02:00
Florent Kermarrec
17e5249be0 global: pep8 (replace tabs with spaces) 2015-04-13 20:07:07 +02:00
Florent Kermarrec
a2c17cdcef Merge branch 'master' of https://github.com/m-labs/migen 2015-04-13 09:37:03 +02:00
Sebastien Bourdeauducq
c6904f9d63 sim: fix to support ConvOutput 2015-04-12 14:06:57 +08:00
Florent Kermarrec
ff23960657 fhdl/verilog: avoid reg initialization in printheader when reset is not an int. 
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
 2015-04-10 17:18:07 +02:00
Sebastien Bourdeauducq
a69741b24e forgot other cordic files 2015-04-09 12:00:20 +08:00
Sebastien Bourdeauducq
e1702c422c introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
Sebastien Bourdeauducq
90c5512b25 genlib: remove cordic (will live in pdq2) 2015-04-08 11:35:53 +08:00
Robert Jordens
25e4d2a2db decorators: remove deprecated semantics 2015-04-05 18:47:45 +08:00
Robert Jordens
8798ee8d73 decorators: fix stacklevel, export in std 2015-04-05 18:47:45 +08:00
Robert Jordens
f26ad97624 decorators: fix ControlInserter 2015-04-05 14:44:03 +08:00
Sebastien Bourdeauducq
db76defa2a fhdl/visit: remove TransformModule 2015-04-04 20:12:22 +08:00
Robert Jordens
e702fb7727 decorators: fix class/instance logic 2015-04-04 19:16:58 +08:00
Robert Jordens
4091af69fd fhdl/decorators: make the transform logic more idiomatic 
* the transformers work on classes and instances.
  you can now do just do:

    @ResetInserter()
    @ClockDomainRenamer({"sys": "new"})
    class Foo(Module):
        pass

  or:

    a = ResetInserter()(FooModule())

* the old usage semantics still work
* the old DecorateModule is deprecated,
  ModuleDecorator has been refactored into ModuleTransformer
  (because it not only decorates things)
 2015-04-04 19:16:50 +08:00
Florent Kermarrec
ce0ff1e341 remove use of _r prefix on CSRs 2015-04-02 12:15:56 +02:00
Florent Kermarrec
d67f24ddc7 migen/bank/description: remove support of _r prefix in CSRs 2015-04-02 12:13:22 +02:00
Sebastien Bourdeauducq
c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions" 
This reverts commit f03aa76292.
 2015-03-30 19:41:16 +08:00
Sebastien Bourdeauducq
dc88295338 Revert "migen/fhdl: pass fdict filename --> contents to specials" 
This reverts commit ea04947519.
 2015-03-30 19:41:13 +08:00
Sebastien Bourdeauducq
b1c811a3d1 Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method" 
This reverts commit 95cfc444e6.
 2015-03-30 19:41:04 +08:00
Florent Kermarrec
95cfc444e6 migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method 2015-03-30 11:37:59 +02:00
Florent Kermarrec
ea04947519 migen/fhdl: pass fdict filename --> contents to specials 2015-03-30 11:37:57 +02:00
Florent Kermarrec
f03aa76292 migen: create VerilogConvert and EDIFConvert classes and return it with convert functions 2015-03-30 11:37:55 +02:00
Robert Jordens
14b1da4018 test_actor: add unittests for SimActor 
* also implicitly tests for the access of signals during simulation that are
not referenced in any statements

* before, if the busy signal is never used, it is stripped
  and could not be accessed in simulation
 2015-03-21 10:02:10 +01:00
Robert Jordens
5f045b7649 sim: keep track of unreferenced items 
* items that are never referenced in any statements do not end up in the
namespace or in the verilog

* this memorizes items if they can not be found in the namespace and keeps
track of their values
 2015-03-21 10:02:10 +01:00
Sebastien Bourdeauducq
7fa1cd72a8 fhdl/verilog: fix dummy signal initial event 2015-03-19 00:24:30 +01:00
Florent Kermarrec
5a9afee234 fhdl/specials/memory: use $readmemh to initialize memories 2015-03-18 15:27:01 +01:00
Florent Kermarrec
c0fb0ef600 fhdl/verilog: change the way we initialize reg: reg name = init_value; 
This allows simplifications (init in _printsync and _printinit no longer needed)
 2015-03-18 15:05:26 +01:00
Florent Kermarrec
ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" 
This probably breaks simulation with Icarus Verilog (and others simulators?)
 2015-03-18 14:59:22 +01:00
Florent Kermarrec
2fc2f8a6c0 migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb) 2015-03-18 14:41:43 +01:00
Sebastien Bourdeauducq
bdc47b205a Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)" 
This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e453.
 2015-03-18 12:08:25 +01:00
Florent Kermarrec
89fefef3f8 genlib/io: add optional external rst to CRG 2015-03-17 16:22:22 +01:00
Florent Kermarrec
b7d7fe1a4c fhdl/special: add optional synthesis directive (needed by Synplify Pro) 2015-03-17 14:59:05 +01:00
Florent Kermarrec
9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code 
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
 2015-03-17 00:40:26 +01:00
Florent Kermarrec
e946f6e453 fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) 2015-03-16 23:47:07 +01:00
Florent Kermarrec
69ce6dd48c migen/genlib/io: add DDRInput and DDROutput 2015-03-16 22:47:13 +01:00
Sebastien Bourdeauducq
beeaefccea move pytholite to separate repos 2015-03-14 22:48:03 +01:00
Sebastien Bourdeauducq
c824379878 fhdl/visit: fix TransformModule 2015-03-14 17:45:11 +01:00
Sebastien Bourdeauducq
6a979a8023 mibuild: sanitize default clock management 2015-03-14 00:10:08 +01:00
Florent Kermarrec
ff266bc2ee migen/genlib/io: add DifferentialOutput and Xilinx implementation 2015-03-12 19:30:57 +01:00
Florent Kermarrec
bf28664cb4 genlib/io.py: fix copy/paste error (thanks rjo) 2015-03-12 18:49:49 +01:00
Florent Kermarrec
c8ba8cde8e migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild 2015-03-12 18:38:53 +01:00
Florent Kermarrec
8e09a86e4f genlib/misc: add increment parameter to Counter 2015-03-09 20:20:25 +01:00
Florent Kermarrec
ebcea3c000 fhdl/module: use r.append() in _collect_submodules 2015-03-09 19:45:02 +01:00
Florent Kermarrec
ee1091f491 fhdl/module: avoid flushing self._submodules and create do_exit. 2015-03-09 17:17:21 +01:00
Sebastien Bourdeauducq
7b00141a0c genlib/cordic: fix typos 2015-03-06 00:47:23 +01:00
Florent Kermarrec
06f3c46e35 genlib/misc: fix missing *args in Counter 2015-03-04 23:49:15 +01:00
Florent Kermarrec
7d68ecbd86 move dma_lasmi to MiSoC 2015-03-02 08:23:02 +01:00
Florent Kermarrec
58290f3c43 lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks) 2015-03-01 22:04:20 +01:00
Florent Kermarrec
8f81ae6826 genlib/misc: add FlipFlop, Counter, Timeout 2015-03-01 16:33:46 +01:00
Florent Kermarrec
e82531cdf8 move dfi/lasmibus/wishbone2lasmi to MiSoC sdram 2015-02-27 16:54:22 +01:00