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Author SHA1 Message Date
Florent Kermarrec
31661e9e2d soc/interconnect/packet: connect error/last_be only present on both sink and source 2019-11-15 14:57:31 +01:00
Florent Kermarrec
2946581e50 soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple 
To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
 2019-11-15 14:39:55 +01:00
Florent Kermarrec
86662b54d0 soc/interconnect/packet: update copyright 2019-11-15 11:25:38 +01:00
Vamsi K Vytla
5c19b133ac soc/interconnect/packet: add > 8-bit support to Packetizer/Depacketizer 
With high speed link (10gbps XGMII ethernet for example), stream data_width is generally
> 8-bit which make header/data un-aligned on bytes boundaries. The change allows the
Packetizer/Depacketizer to work on stream with a data_width > 8-bit.
 2019-11-15 11:24:17 +01:00
Florent Kermarrec
a17e307acf bios/flash: minor cleanup on serialboot flashing, add flash address support 2019-11-09 00:05:36 +01:00
enjoy-digital
2d6100bdbe
Merge pull request #305 from FrankBuss/master 
adding support to flash an FBI image
 2019-11-08 23:51:49 +01:00
Florent Kermarrec
05e8abfee3 soc_core: add integrated-rom-file parameter to allow initializing rom from command line 2019-11-08 23:32:10 +01:00
Florent Kermarrec
0a030fe17d cores/code_8b10b/Decoder: add basic invalid symbols detection 
Check that we have 4,5 or 6 ones in the symbol. This does not report all
invalid symbols but still allow detecting issues with the link.
 2019-11-08 19:43:01 +01:00
fb@frank-buss.de
9857d9d9d2 adding support to flash an FBI image 2019-11-08 17:16:28 +01:00
Florent Kermarrec
c96f31a9ad software/bios: rename ef command to fe (for consistency) 2019-11-08 13:14:21 +01:00
Florent Kermarrec
4a12a92d62 software/libbase/spiflash: rename CHIP_ERASE_CMD to CE_CMD (for consistency) 2019-11-08 13:13:54 +01:00
enjoy-digital
7fb9cfeb64
Merge pull request #302 from FrankBuss/master 
erase flash command added
 2019-11-08 13:04:33 +01:00
Florent Kermarrec
db4739df81 soc_core: remove add_cpu method (when no real CPU but only wishbone masters, self.cpu is declared as CPUNone) 2019-11-08 12:55:29 +01:00
fb@frank-buss.de
468df3c857 erase flash command added 2019-11-07 19:19:54 +01:00
Florent Kermarrec
f1714405c3 integration/export: do not include soc.h in csr.h when with_access_functions=False 
Idealy we should have another parameter for that.
 2019-11-07 09:02:31 +01:00
Florent Kermarrec
b52dcde9ba soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB. 
CSR map will need to be updated to support the 2GB.
 2019-11-07 09:00:54 +01:00
Florent Kermarrec
9053d0803a soc_sdram: remove use_full_memory_we parameter (always used as True) 2019-11-07 08:56:52 +01:00
Florent Kermarrec
1b94699d12 soc_sdram: update copyrights 2019-11-07 08:44:34 +01:00
Gabriel Somlo
28708f4208 cpu/rocket: parameterize axi interface data width 
Rocket variants can be configured with axi port data widths that
are multiples of the native word size (64 bits in our case). In
the future, we will add variants with mem_axi data width > 64 bit,
to match the native data width of the LiteDRAM controller on
various development boards (e.g., 128 bits on the ecp5versa, and
256 bits on the trellisboard).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-11-01 08:55:27 -04:00
Gabriel Somlo
014db66444 soc_sdram: remove upper limit on usable main RAM 
Revert commit #68a503174.
 2019-11-01 08:55:15 -04:00
Gabriel Somlo
ec831f5b63 cpu/rocket, soc_sdram: Connect mem_axi to LiteDRAM, bypass WB bus 
Connect Rocket's dedicated port for cached RAM accesses (mem_axi)
directly to the LiteDRAM data port, bypassing the shared LiteX
(Wishbone) bus.

When both Rocket's mem_axi and LiteDRAM's port have the same data
width, use a native point-to-point AXI connection.

Otherwise, convert both ends to Wishbone, and use the Wishbone
data width converter to bridge the gap.
FIXME: In the future, this part should be replaced with a native
AXI data width converter!

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-11-01 08:52:39 -04:00
Florent Kermarrec
9c3c43c94a interconnect/csr_bus/SRAM: add mem_size check 
Memory size is limited to 512 bytes:
- CSR region size is 0x800 (4096)
- default csr_data_width is 8
maximum size = 4096/8 = 512 bytes.
 2019-11-01 11:33:50 +01:00
Florent Kermarrec
edb1731ef9 soc_core/soc_core_args: specify default cpu (vexriscv) 2019-11-01 11:30:50 +01:00
Florent Kermarrec
59acf0ea1c cpu/minerva: elaborate minerva verilog to build directory 2019-11-01 09:59:13 +01:00
Florent Kermarrec
a762d29b19 soc/integration/builder: pass output_dir to platform, make sure gateware/software directory are created before finalizing 2019-11-01 09:59:06 +01:00
Florent Kermarrec
855d0e925d cpu/minerva: generate minerva.v near core.py not in submodule 2019-10-31 21:16:27 +01:00
Florent Kermarrec
85d6607257 cpu/minverva: give more explicit error message when not able to elaborate cpu 2019-10-31 08:52:04 +01:00
Tim 'mithro' Ansell
4408dad9d2 Improve the error message on memory region conflict. 
Before;
```
ValueError: Memory region conflict between rom and main_ram
```

After;
```
ValueError: Memory region conflict between rom (<SoCMemRegion 0x10000000 0x10000 cached>) and main_ram (<SoCMemRegion 0x0 0x20000000 cached>)
```

Fixes #296.
 2019-10-30 19:32:20 -07:00
Tim 'mithro' Ansell
607e1cc4f6 Fix file names for the mor1kx processor. 
Fixes #292.
 2019-10-30 13:50:01 -07:00
Florent Kermarrec
a0c0a6fd05 integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json 
Supported types: "cached", "io", "cached+linker", "io+linker", default="cached"
 2019-10-30 16:42:26 +01:00
Florent Kermarrec
9fcf297387 soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions) 2019-10-28 18:34:03 +01:00
Florent Kermarrec
4014fbffe1 soc_core/add_memory_region: fix memory overlap detection 2019-10-28 17:07:37 +01:00
Florent Kermarrec
ab8af28213 cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier 2019-10-28 10:23:08 +01:00
enjoy-digital
b6d35c92ae
Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address 
bios: Increment address when writing to flash
 2019-10-20 15:30:22 +02:00
Konrad Beckmann
ef78ae951f bios: Increment address when writing to flash 2019-10-19 22:58:24 +02:00
Florent Kermarrec
4cf346a1d4 soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1 2019-10-18 10:27:37 +02:00
Jan Kowalewski
8b5da9c623 cores/icap/ICAPBitstream: add source ready signal. 2019-10-18 09:33:31 +02:00
Florent Kermarrec
626533ce9d soc/integration/__init__: remove imports (not used and causing issues 2019-10-17 12:44:37 +02:00
Florent Kermarrec
97a77b950c cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it. 2019-10-16 15:00:58 +02:00
Florent Kermarrec
14dae8bd73 soc_core: fix default --uart_name 2019-10-14 22:15:02 +02:00
Florent Kermarrec
ba26441889 integration/soc_core: expose more SoC parameters 2019-10-14 09:12:25 +02:00
Konrad Beckmann
0e467168fd picorv32: Fix minimal variant params 
The param p_ENABLE_COUNTERS was misspelled.
 2019-10-13 12:56:55 +02:00
Florent Kermarrec
ef504f62af soc_core: fix soc_core_argdict 2019-10-12 23:05:53 +02:00
Florent Kermarrec
cd8213b988 cpu/lm32: add missing buses 2019-10-12 19:20:50 +02:00
Florent Kermarrec
5a0358754d soc_core/soc_core_argdict: use inspect to get all parameters and simplify 2019-10-12 19:18:57 +02:00
Florent Kermarrec
96c369f3e4 integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) 2019-10-11 21:55:26 +02:00
Florent Kermarrec
29e51f5e97 interconnect/wishbone: fix Converter case when buses are identical 2019-10-11 21:49:11 +02:00
Florent Kermarrec
9a82933858 cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore) 2019-10-11 09:01:50 +02:00
Florent Kermarrec
ca81cc209b soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed) 2019-10-11 09:01:08 +02:00
Florent Kermarrec
03faf06c82 soc/interconnect/axi: re-align to improve readability 2019-10-11 08:41:05 +02:00
Florent Kermarrec
7dea9afd7d software/bios: simplify banners 2019-10-11 08:38:12 +02:00
Florent Kermarrec
6bd1889330 cpu/picorv32: remove obsolete comment 2019-10-10 22:29:54 +02:00
Florent Kermarrec
28517d20ca cpu/picorv32: use a single idbus 2019-10-10 22:02:04 +02:00
Florent Kermarrec
5daf1a2296 cpu: cleanup/re-align 2019-10-10 21:52:09 +02:00
Florent Kermarrec
467d35edee cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix 2019-10-10 21:40:29 +02:00
Florent Kermarrec
1045cda39e cpu: add buses list and use it in soc_core to add bus masters 2019-10-10 21:35:06 +02:00
Florent Kermarrec
42ccc91f74 integration: move soc constants to soc.h of csr.h 
software retro-compat with soc.h included in csr.h
 2019-10-10 21:15:49 +02:00
Florent Kermarrec
b25194826e integration/soc_zynq: shadow_base no longer recommended (replace with io_regions) 2019-10-10 19:23:01 +02:00
Florent Kermarrec
496ba7e594 bios/main: use same banner than README (MiSoC cited in README/LICENSE) 2019-10-10 19:21:32 +02:00
Florent Kermarrec
840f01b6d5 software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf 2019-10-10 19:18:28 +02:00
Gabriel Somlo
f8f643a02f cpu/rocket: swap main_mem and io regions 
The total size of RAM (main_mem) can be expected to vary significantly,
and often exceed the size needed for MMIO allocations by a large margin.

As such, place Rocket's MMIO (io regions) below 0x8000_0000, and start
the RAM (main_mem) at 0x8000_0000, with nothing above it to limit its
future growth.

Also, bump the pre-built Rocket verilog submodule to an updated version,
which also comes with matching changes to the way MMIO and RAM accesses
are mapped and routed to their respective AXI interfaces.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-10-09 14:25:41 -04:00
Florent Kermarrec
b627a8fe71 cpu: add default io_regions to CPUNone (all address range can be used as IO) 2019-10-09 12:06:21 +02:00
Florent Kermarrec
a6b3aa3c62 soc_core: improve check_io_region error message 2019-10-09 10:47:19 +02:00
Florent Kermarrec
10146abf0a cpu/rocket: move csr to IO region 2019-10-09 10:24:01 +02:00
Florent Kermarrec
a4ef9b29b9 soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) 
The shadow_base parameter has always been difficult to apprehend, replace it with
io_regions (uncached regions) defined user or the CPU.

The equivalent of a shadow_base parameter of 0x80000000 in the old API is:
io_regions = {0x80000000: 0x80000000} # origin, length

It's still possible to use shadow_base with retro-compat, but user is encouraged
to update and features will be removed in the future.
 2019-10-09 10:15:42 +02:00
Gabriel Somlo
53777391e8 builder: use the SoC's existing shadow base with get_csr_header() 
Both the SoC and get_csr_header() have independently set defaults
for the value of 'shadow_base'. If the SoC's value was modified,
ensure that get_csr_header() uses the modified value instead of
its own default.

Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
 2019-10-08 14:28:50 -04:00
Florent Kermarrec
975bd9be8b cpu/vexriscv: use specific mem_map for linux variant 2019-10-07 08:50:03 +02:00
Ilia Sergachev
2f7bd97129 fix comments 2019-10-06 10:47:28 +02:00
enjoy-digital
960b25a541
Merge pull request #270 from gsomlo/gls-csr-upper 
soc/integration: ensure CSR constants are in uppercase
 2019-10-01 21:40:56 +02:00
Florent Kermarrec
41ad08e8ef soc/cores/icap: simplify ICAPBitstream (untested) 2019-10-01 21:30:14 +02:00
Florent Kermarrec
0c2993866c soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP 2019-10-01 21:04:49 +02:00
enjoy-digital
4bb2827e05
Merge pull request #269 from antmicro/rework_icap 
soc: cores: support sending custom bitstream to ICAP
 2019-10-01 20:55:28 +02:00
Gabriel Somlo
c8790d342a soc/integration: ensure CSR constants are in uppercase 
Fixup over commit 8be5824e.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-10-01 12:15:25 -04:00
Jan Kowalewski
4423a46ba2 soc: cores: support sending custom bitstream to ICAP 
This adds FIFO that can be used to send any
sequence of commands to the ICAP controller.
 2019-10-01 13:44:45 +02:00
Florent Kermarrec
427d7af767 soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00
Florent Kermarrec
59bf04d965 soc/interconnect/stream: add separators, mode Actor modules just after Endpoint 2019-09-30 23:33:25 +02:00
Florent Kermarrec
59995c5359 soc_zynq: update get_csr_header 2019-09-30 16:00:11 +02:00
Florent Kermarrec
4d90058b18 soc/integration: move cpu_interface retro-compatibility to litex/__init__ 2019-09-30 11:32:07 +02:00
Florent Kermarrec
8be5824e25 soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses 2019-09-30 10:59:36 +02:00
Florent Kermarrec
7b72148c4e cpu: remove initial SERV support (we'll work in a branch to experiment with it) 2019-09-30 08:35:18 +02:00
Florent Kermarrec
63a813af9c soc_core: fix cpu_type=None case and add test for it 2019-09-30 08:26:38 +02:00
Florent Kermarrec
3d257d7266 soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. 
Proper AXI support will be added in the future for SoCs.
 2019-09-29 17:33:16 +02:00
Florent Kermarrec
e8e57b4f87 soc_core: cleanup/re-align 2019-09-29 17:31:37 +02:00
Florent Kermarrec
334ae336bf soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators 2019-09-29 17:23:26 +02:00
Florent Kermarrec
48e5a1d140 soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
Florent Kermarrec
e9ed4761b5 soc/cores/gpio: uniformize with others cores 2019-09-29 16:10:44 +02:00
Florent Kermarrec
78cecbe36b soc/cores: rename frequency_meter to freqmeter and uniformize with others cores 2019-09-29 16:08:39 +02:00
Florent Kermarrec
7575ecc6ad soc/cores/ecc: improve readibility, uniformize with others cores 2019-09-29 16:02:04 +02:00
Florent Kermarrec
c6fe3f3145 soc/cores/clocks: improve readibility 2019-09-29 15:58:22 +02:00
Florent Kermarrec
6fcb12a98f soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) 2019-09-29 15:47:10 +02:00
Florent Kermarrec
b826c1705f soc/cores/cpus: improve ident/align, uniformize between cpus 2019-09-29 15:41:36 +02:00
Florent Kermarrec
355072c285 soc/cores/cpu: add CPU class and make all CPU inheritate from it 
Also rename reserved_interrupts to interrupts (empty dict is no reserved interrupts)
 2019-09-29 15:27:41 +02:00
Florent Kermarrec
2c3ad3f96d soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) 2019-09-29 14:44:44 +02:00
Florent Kermarrec
101f1b1cef soc/integration: add common.py and move helpers from soc_core to it 2019-09-29 14:22:26 +02:00
Florent Kermarrec
68ba1c60be soc_core: avoid manual listing of support CPUs, just use CPU.keys() 2019-09-28 22:19:23 +02:00
Florent Kermarrec
9095b80e89 soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) 2019-09-28 19:01:41 +02:00
Florent Kermarrec
8dd2dc1ce8 integration/soc_core: remove csr_map_update (no longer used) 2019-09-28 18:59:30 +02:00
Florent Kermarrec
da91aa43f7 soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done 2019-09-28 14:15:48 +02:00
Florent Kermarrec
8099b0beb6 soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter 2019-09-28 12:35:41 +02:00
Florent Kermarrec
7660dc22e1 soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) 2019-09-28 12:09:55 +02:00
Florent Kermarrec
a3816096a7 cores/cpu: define CPUS and simplify instance 2019-09-28 00:55:08 +02:00
Florent Kermarrec
9f6a2ae73e soc_core/serv: use UART_POLLING (no interrupt support) 2019-09-28 00:42:00 +02:00
Florent Kermarrec
49594ed7d4 software/libbase/uart: add polling mode 2019-09-28 00:35:26 +02:00
Florent Kermarrec
3f95b9c0de add SERV CPU initial support (not working) 2019-09-28 00:34:55 +02:00
Florent Kermarrec
1425a68d9e wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) 
Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.
 2019-09-24 17:55:29 +02:00
Florent Kermarrec
ffd2be2ba0 csr: add we signal to CSR, CSRStatus 
Doing actions on register read is generally not a good design practice (it's
better to do separate register write to trigger actions) but in some very
specific cases being able to know that register has been read can solve cases
that are difficult to do with the recommended practives and that can justify
doing an exception.


This commit add a we signal to CSR, CSRStatus and this allow the logic to know
when the CSR, CSRStatus is read.
 2019-09-24 17:51:06 +02:00
Florent Kermarrec
ed9bff2eb9 soc/integration/doc: replace "== None" by "is None" 2019-09-24 10:11:31 +02:00
enjoy-digital
836d5b88c5
Merge pull request #266 from xobs/add-moduledoc-autodoc 
Add ModuleDoc and AutoDoc
 2019-09-24 10:09:22 +02:00
Benjamin Herrenschmidt
0ea7a1fd05 soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty 
For example a standalone controller with no exposed CSRs (probably not
a very useful configuration but I really don't like python backtraces)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-24 08:41:59 +02:00
Sean Cross
68cea8c32f timer: inherit ModuleDoc 
With the new ModuleDoc class, we can inherit `ModuleDoc` and
automatically get module-level documentation.

This patch also corrects a typo in `timer` that causes an error in
sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-24 14:34:41 +08:00
Sean Cross
131971986c integration: add ModuleDoc and AutoDoc 
It is important to be able to document modules other than CSRs.
This patch adds ModuleDoc and AutoDoc, both of which can be used
together to document modules.

ModuleDoc can be used to transform the __doc__ string of a class into a
reference-manual section.  Alternately, it can be used to add additional
sections to a module.

AutoDoc is used to gather all submodule ModuleDoc objects in order to
traverse the tree of documentation.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-24 14:30:28 +08:00
enjoy-digital
742da31bc0
Merge pull request #264 from antmicro/mor1kx_linux 
Enable to run Linux on mork1x
 2019-09-23 23:19:45 +02:00
Florent Kermarrec
06d0806494 soc_core: set csr to 0x00000000 when there is no wishbone 2019-09-23 15:57:14 +02:00
Florent Kermarrec
ad8830d977 soc_sdram: Don't add the L2 Cache when there's no wishbone bus 2019-09-23 15:53:07 +02:00
Filip Kokosinski
5844376d53 soc_core: adapt memory map for mainline Linux with mor1kx 
Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.
 2019-09-23 15:34:52 +02:00
Florent Kermarrec
ae38fd4244 soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter 2019-09-23 12:59:43 +02:00
Florent Kermarrec
8c979565a8 soc_sdram: change l2_size checks order 2019-09-23 10:15:27 +02:00
Florent Kermarrec
a9acab99b3 soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) 2019-09-23 09:58:47 +02:00
Florent Kermarrec
dde6dd027b integration/builder: avoid specific _generate_standalone_includes 2019-09-23 09:26:47 +02:00
Benjamin Herrenschmidt
735ea196dd This will allow it to be built for microwatt out of tree 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-23 08:40:54 +02:00
Benjamin Herrenschmidt
c28086cde8 soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-23 08:35:50 +02:00
Benjamin Herrenschmidt
f909e4d706 integration/builder: When the CPU is "None", we used to not generate any code. 
With this change, we will now generate csr.h and sdram_phy.h, which
will be needed by the initialization code running on the host CPU.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-23 08:31:21 +02:00
Sean Cross
1a6dddd57c spi_flash: document register fields 
Document the various fields present in the SPI flash bitbang interface.
This adds documentation for the Single and DualQuad modules.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 12:42:43 +08:00
Sean Cross
60d8572c3e csr_eventmanager: add name and description args 
Add `name` and `description` as optional arguments to the various
EventSource types.  These default to `None`, so this should be a
backwards-compatible change.

Use the same trick as CSRs, where we default the `name` to be the
instantiated object name as read from the Migen `get_obj_var_name()`
call.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-19 17:23:03 +08:00
Florent Kermarrec
e2c78572a2 cores/timer: add general documentation on Timer implementation and behavior. 2019-09-19 09:27:24 +02:00
Florent Kermarrec
e97c1e36fb soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower 2019-09-19 05:36:57 +02:00
Florent Kermarrec
99ed0877ac csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) 2019-09-18 10:47:54 +02:00
Florent Kermarrec
f2e84a5800 soc/cores/timer: fix typo (thanks xobs) 2019-09-18 10:45:38 +02:00
Florent Kermarrec
28885064f7 soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. 2019-09-18 10:14:47 +02:00
Sean Cross
cb7d941aaa timer: add documentation 
Now that CSRs have documentation support, add documentation to the basic
`Timer` module.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-18 15:06:20 +08:00
Florent Kermarrec
cca0478a5e soc/cores/spi: use new CSRField (no functional change) 2019-09-16 17:02:55 +02:00
Florent Kermarrec
80b2bef387 soc/cores/bitbang: use new CSRField (no functional change) 2019-09-16 16:56:00 +02:00
Florent Kermarrec
9bda614a3e csr: update copyrights 2019-09-16 08:49:00 +02:00
Florent Kermarrec
29134cc659 csr: more documentation 2019-09-16 08:45:29 +02:00
Florent Kermarrec
74e756aa30 csr/CSRStorage: remove storage_full (was only needed by alignment_bits) 2019-09-16 08:38:26 +02:00
Florent Kermarrec
5dc440e80d csr: use IntEnum for CSRAccess 2019-09-16 08:36:25 +02:00
Florent Kermarrec
d2646f138e csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful 2019-09-15 19:47:48 +02:00
Florent Kermarrec
8e14694eb5 csr/fields: document, add separators, 100 characters per line 2019-09-15 19:11:25 +02:00
Florent Kermarrec
4e84729cf9 csr/fields: add access parameter 2019-09-14 22:16:18 +02:00
Florent Kermarrec
23b01f8f02 csr/fields: add pulse mode support 2019-09-14 21:49:34 +02:00
Florent Kermarrec
8c080e5fb6 soc/interconnect/csr: add initial field support 2019-09-13 20:01:31 +02:00
Florent Kermarrec
16b6b357ca soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found 2019-09-11 18:30:28 +02:00
Florent Kermarrec
62f53d5035 soc/integration/builder: call do_exit with vns when build is done. 2019-09-10 12:41:05 +02:00
Florent Kermarrec
cb5f1467cf Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-09-09 15:12:24 +02:00
Florent Kermarrec
004c96b508 soc/itnegration: update litedram 2019-09-09 15:12:08 +02:00
Ilia Sergachev
2400f0f43d fix crc32 2019-09-09 13:19:43 +02:00
Florent Kermarrec
19f58dd971 interconnect/wishbone: add FlipFlop to allow UpConverter to be used 
Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up
 2019-09-09 11:47:36 +02:00
Florent Kermarrec
b356204f95 soc_core: add JTAG UART support (uart_name="jtag_uart) 2019-09-06 11:56:42 +02:00
Florent Kermarrec
d0ebbda4b3 soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) 2019-09-06 11:55:41 +02:00
Florent Kermarrec
2638393b53 soc_zynq: fix indent 2019-09-05 15:59:35 +02:00