Dolu1990
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fb084327da
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Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert
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2022-11-28 16:30:47 +01:00 |
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Dolu1990
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eafeb5fe49
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Add EmbeddedRiscvJtag.debugCd
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2022-11-28 11:04:02 +01:00 |
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Dolu1990
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a25ae96d33
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comment debug code
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2022-11-21 14:02:35 +01:00 |
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Dolu1990
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572ca3fcfa
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Privileged debug fake maskmax to 31
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2022-11-21 14:01:28 +01:00 |
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Dolu1990
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5a8cdee884
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Fix CsrPlugin dcsr.stepie
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2022-11-21 11:55:07 +01:00 |
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Dolu1990
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4ae7386904
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Merge pull request #276 from LYWalker/master
Add ability to debug over Intel Virtual JTAG
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2022-11-18 17:38:50 +01:00 |
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Dolu1990
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e19e59b55c
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Clear mprv on xretAwayFromMachine
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2022-11-17 15:03:47 +01:00 |
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Dolu1990
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663174bc73
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Privileged debug now implement stoptime stopcount
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2022-11-17 13:58:29 +01:00 |
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Dolu1990
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36c3346e51
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ensure rvc 0 is detected as a illegal instruction
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2022-11-17 11:03:45 +01:00 |
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Dolu1990
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5e17ab62d6
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Fix RISC-V debug hardware breakpoints
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2022-11-14 14:45:11 +01:00 |
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Dolu1990
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fe68b8494e
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Fix a few RISC-V official debug support :
- Disable interrupts in debug mode
- Ensure traps do not change CSR in debug mode
- step will also consider trapEvent
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2022-11-11 14:05:38 +01:00 |
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Dolu1990
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2504f9b9b9
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RISC-V debug havereset implemented
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2022-11-10 15:49:07 +01:00 |
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Dolu1990
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0bfaf06a4a
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main.cpp add VEXRISCV_JTAG=yes
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2022-11-10 13:43:14 +01:00 |
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Dolu1990
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f71234786f
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Remove rv64 opcode (shift and lwu)
Thanks Milan
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2022-10-27 15:44:50 +02:00 |
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Dolu1990
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d70794f252
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fix regression
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2022-10-27 15:38:34 +02:00 |
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Dolu1990
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5d0deb20b3
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Fix regression compilation
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2022-10-27 15:20:55 +02:00 |
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Dolu1990
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9f6186cd9a
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Add GenFullWithRiscvPrivilegedDebugJtag demo
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2022-10-27 14:55:40 +02:00 |
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Dolu1990
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6289ebcbe4
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Merge branch 'riscv-debug' into dev
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2022-10-27 14:46:46 +02:00 |
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Dolu1990
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a6c29766da
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CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled
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2022-10-26 15:48:34 +02:00 |
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Dolu1990
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ab7b2cff3b
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fix diagram name
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2022-10-26 10:48:21 +02:00 |
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Dolu1990
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7fd55c7851
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Add VexRiscvAxi4LinuxPlicClint diagram drawio
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2022-10-26 10:47:23 +02:00 |
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Dolu1990
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0e531515ac
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cleaning
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2022-10-26 10:25:50 +02:00 |
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Dolu1990
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63dd787bce
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VexRiscvAxi4Linux now integrate Plic and Clint
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2022-10-26 10:15:21 +02:00 |
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Dolu1990
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220af95043
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Add VexRiscvAxi4Linux (untested, but generate a netlist)
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2022-10-24 10:35:59 +02:00 |
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Dolu1990
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0979f8ba80
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Add whitebox example
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2022-10-24 10:24:41 +02:00 |
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Dolu1990
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17d52ce58f
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privileged debug now access data cache with caching enable
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2022-10-21 18:58:40 +02:00 |
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Dolu1990
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486d17d245
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CsrOpensbi now add rvc to misa
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2022-10-21 18:58:13 +02:00 |
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Dolu1990
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662943522f
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Fix privileged debug trigger decode break logic
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2022-10-21 17:21:13 +02:00 |
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Dolu1990
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95c656ceef
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riscv debug multiple harts
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2022-10-21 12:28:17 +02:00 |
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Dolu1990
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0313f84419
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Fix RISCV debug step
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2022-10-20 10:36:30 +02:00 |
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Dolu1990
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4cd3f65296
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Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet)
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2022-10-19 12:36:45 +02:00 |
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Dolu1990
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959e48a353
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Fpu now set csr status fs on FPU csr write
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2022-10-06 11:13:57 +02:00 |
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Dolu1990
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fda7da00c2
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add litex --wishbone-force-32b
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2022-09-06 11:19:29 +02:00 |
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Dolu1990
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e3e21994b4
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use SpinalHDL "dev"
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2022-07-22 09:33:19 +02:00 |
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Dolu1990
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54412bde30
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getDrivingReg() update
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2022-07-21 09:10:26 +02:00 |
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Dolu1990
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a650000f0b
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SpinalHDL 1.7.2
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2022-07-11 12:03:06 +02:00 |
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Dolu1990
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b1252f47de
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csr opensbi now enable ebreak
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2022-06-13 16:34:49 +02:00 |
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Dolu1990
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1303c0ca7c
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CfuPlugin.withEnable added
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2022-06-09 17:57:31 +02:00 |
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Dolu1990
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1ce4c6e493
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fix VexRiscvRegressionData url
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2022-06-01 09:54:11 +02:00 |
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Dolu1990
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0f6d0f022c
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VexRiscvBmbGenerator now also report bytesPerLine
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2022-05-24 12:37:31 +02:00 |
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Dolu1990
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771eaf431e
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Better cache invalidation doc
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2022-05-24 12:15:57 +02:00 |
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Dolu1990
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e6dfcac0be
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Add D$ single line flush support
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2022-05-24 12:13:37 +02:00 |
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Dolu1990
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4c4913c703
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Fix MPP to only retain legal values
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2022-05-24 11:14:34 +02:00 |
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Dolu1990
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209fc719e8
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VexRiscvBmbGenerator export more info
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2022-05-24 10:19:35 +02:00 |
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Dolu1990
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48cf4120f2
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Add VexRiscvSmpCluster forceMisa/forceMscratch
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2022-05-23 15:49:32 +02:00 |
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Dolu1990
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0872852387
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Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254
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2022-05-17 20:44:17 +02:00 |
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Dolu1990
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a553d3b476
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Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254
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2022-05-17 15:27:50 +02:00 |
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Dolu1990
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78f0a7f13e
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Fix CfuPlugin/VfuPlugin fork duplication
https://github.com/google/CFU-Playground/issues/582
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2022-05-16 10:36:21 +02:00 |
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Dolu1990
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8df2dcbd40
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Fix RVC step by step triggering next instruction branch predictor
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2022-05-11 14:10:32 +02:00 |
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Dolu1990
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6326736401
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Update build.sbt
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2022-05-04 00:03:54 +02:00 |