694608688d
terasic_sockit: fix: make video clock also optional as video terminal is optional
2021-04-27 08:52:11 +07:00
5bfeb999e4
targets/digilent_arty/flash: Simplify, use Quad mode and sys_clk (fast enough ~5MB/s).
2021-04-26 16:30:35 +02:00
2854df5028
Arty: move spiflash PHY do 4x faster clk domain
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-04-26 12:52:36 +02:00
84ae2b2bbc
arty: add option to use litespi QSPI controller
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-04-26 12:52:30 +02:00
2d2a10621f
antmicro_lpddr4_test_board: fix ethernet rx delay issue
2021-04-23 15:25:47 +02:00
228a9650d4
sqrl_acorn: Add flashing/reload support when used with PCIe, fix JTAG flash.
2021-04-21 17:00:40 +02:00
d2eabd112d
Add E-Elements Ego1 initial board support.
2021-04-12 08:20:46 +02:00
cd3d4c826e
Add Trenz te0725 initial board support.
2021-04-12 08:16:45 +02:00
5519c931f8
xilinx_alveo_u280: Fix DDR4 (tested with 8 modules on C0 and C1).
2021-04-12 08:07:16 +02:00
d5318dcb03
Qmtech Wukong: updates
...
fix ethernet clock (it's a GMII), add FB support over the HDMI connector (hdmi clock set from the resolution)
2021-04-10 16:26:25 +02:00
03accabc25
lpddr4_test_board: Add antmicro vendor prefix.
2021-03-31 09:48:23 +02:00
a834985e00
Add target for LPDDR4 Test Board
2021-03-30 14:50:02 +02:00
d5ce1901d8
targets/digilent_nexys_video: Add specific Video PLL to give more flexibility on supported Video Timings.
2021-03-30 10:17:50 +02:00
9417044584
targets: Minor cleanup, make sure all targets can be built with default settings.
2021-03-29 16:22:39 +02:00
1ca8ef97a1
targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
2021-03-29 16:03:19 +02:00
ba01776432
targets/add_sdram: Simplify call by removing useless arguments.
...
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
2021-03-29 15:28:31 +02:00
58286ce29e
minispartan6: Change video resolution to 640x480, framebuffer working with Linux-on-LiteX-Vexriscv.
2021-03-29 14:36:34 +02:00
09700b28d0
ulx3s: Change video resolution to 640x480, framebuffer working with Linux-on-LiteX-Vexriscv.
2021-03-29 11:35:55 +02:00
73ce7f9df1
ztex213 fix; propagate variant from targets to platform
2021-03-27 11:04:51 +01:00
7c537748a0
colorlight_i5: Remove PRBS (too specific to application).
...
If useful for several boards, this should probably be provided directly by LiteX.
2021-03-27 09:31:48 +01:00
7737575b88
terasic_deca: Remove --integrated-ram-size parameter (--integrated-main-ram-size provides the same functionnality).
2021-03-27 08:58:49 +01:00
f714e1210a
terasic_deca: Remove enforced CPU variant/debug: --cpu-variant=imac or --cpu-variant=imac+debug can be used for this.
...
The default CPU/Variant is defined in LiteX, enforcing the variant on the target
prevent usage of the other CPUs and also complicate maintenance.
2021-03-27 08:56:46 +01:00
a48def1352
rhsresearchllc_litefury: Remove since already supported by ./acorn.py --variant=cle-101.
2021-03-26 23:54:56 +01:00
4329a69128
sqrl_acorn_cle_215: Rename to sqrl_acorn and add support for all variants (CLE-101, 215 and 215+).
2021-03-26 23:52:36 +01:00
87df45e625
siglent_sds1104xe: Allow build without Etherbone.
2021-03-26 23:25:42 +01:00
c6ced293d4
targets/siglent_sds1104xe: Integrate VideoTerminal/VideoFrameBuffer.
2021-03-26 22:55:25 +01:00
b54eed0859
terasic_sockit: Review/Cleanup for consistency with other boards.
2021-03-26 22:39:19 +01:00
53a767c85c
terasic_deca: Review/Cleanup for consistency with other boards.
2021-03-26 22:12:13 +01:00
be4965ca78
Merge pull request #192 from hansfbaier/deca_fixes
...
terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 21:52:31 +01:00
9fea5a7fc6
targets/digilent_nexys_video: Cleanup/Simplify #191 .
2021-03-26 21:49:22 +01:00
df58639916
nexys_video: choose VADJ value with arguments
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-26 14:50:05 +01:00
8c0ddd140b
terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 10:46:37 +07:00
e2de69496a
targets/lattice_crossing: Avoid direct override of SoCCore.mem_map (break default SoCore.mem_map with updated imports).
2021-03-25 22:41:26 +01:00
b284fe47c3
targets/terasic_sockit: Fix compilation.
2021-03-25 19:35:44 +01:00
22f167dde4
targets/sqrl_acorn_cle_215: Add missing false path constraints.
2021-03-25 18:19:20 +01:00
7d130d6981
targets/pcie: Cleanup.
2021-03-25 17:47:06 +01:00
333fb362ca
Move import Compat directly to litex_boards.__init__.py and simplify.
2021-03-25 16:47:47 +01:00
062b899e29
platforms/targets: Add mode Vendor prefixes.
2021-03-25 16:19:11 +01:00
7633eae360
targets/colorlight_i5: Remove l2-size args (already provided by soc_core_args.
2021-03-25 14:44:52 +01:00
5253a3c43e
test/ci: Fix/Update.
2021-03-25 14:21:13 +01:00
9a45c49918
targets/versa_ecp5: Also add Vendor prefix.
2021-03-25 14:13:32 +01:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
219067ed3a
Merge pull request #190 from kazkojima/colorlight_i5-video
...
colorlight_i5: Integrate Video Terminal and Video Framebuffer with ne…
2021-03-25 10:28:52 +01:00
47bdf5f759
targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
2021-03-25 10:11:24 +01:00
b3786c5e52
fomu/icebreaker: Update Up5KSPRAM import (litex.soc.cores.up5kspram deprecated, still supported for now but triggers a compat notice).
2021-03-24 17:22:55 +01:00
5995769b46
targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).
2021-03-24 17:22:51 +01:00
cb4e00c3f2
colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-20 07:56:59 +09:00
ddd46205aa
ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-18 15:06:35 +01:00
4330769add
minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY.
2021-03-18 14:10:42 +01:00
8b69ee57a6
arrow_sockit: get video terminal working on VGA
2021-03-16 12:31:41 +07:00
75f7120ff9
targets/Ultrascale: Fix build since idelay's reset is now handled by the PLL (with_reset=True).
2021-03-11 10:00:06 +01:00
8d3aaa8ea9
targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).
2021-03-11 09:48:26 +01:00
0e2d9a571e
alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).
2021-03-10 11:23:27 +01:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
...
Alveo U280 board
2021-03-10 11:16:32 +01:00
61f44739d7
Merge pull request #185 from stffrdhrn/arty-jtagbone
...
arty: Add an option to enable jtagbone
2021-03-10 11:12:20 +01:00
47faaf20d5
deca: Integrate Video Terminal (untested, resource issue).
2021-03-09 15:02:30 +01:00
8fb80053f7
targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).
2021-03-08 17:39:13 +01:00
9cdcb8cb43
ecpix5: Add Etherbone (--with-etherbone).
2021-03-08 13:45:09 +01:00
52ce49cf0c
arty: Add an option to enable jtagbone
...
Then adds jtagbone for arty. I have tested with the following
litex_server and it seems to work fine.
litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg
Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.
2021-03-08 07:05:54 +09:00
e280bff1ec
targets/video: Simplify/Cleanup integration.
2021-03-05 14:40:27 +01:00
ce669ac8cd
targets/nexys_video: Add optional VideoTerminal/VideoFramebuffer.
2021-03-05 14:33:22 +01:00
21207533b0
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
2021-03-04 19:49:03 +01:00
71652e8d44
icebreaker: Lower VideoTerminal resolution to use default 24MHz sys_clk.
2021-03-04 18:29:21 +01:00
253d8129af
nexys4ddr: Integrate simple VideoFrameBuffer.
2021-03-03 20:00:31 +01:00
51a0bbfa65
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
2021-03-03 18:05:24 +01:00
465a95d2a6
icebreaker/nexys4ddr: Use new LiteXSoC's add_video_terminal method to add the Video Terminal.
2021-03-03 17:47:20 +01:00
3af8ec0c8d
targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal.
2021-03-03 17:10:22 +01:00
7e3b8ab3b5
icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
...
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash
https://twitter.com/enjoy_digital/status/1365324823447171074
2021-03-03 16:21:04 +01:00
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod
2021-02-25 09:37:34 +01:00
768c10c630
targets/arty: rebase/merge PR179, rename adaptor to adapter.
2021-02-25 09:36:26 +01:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
98c80f0b2b
Merge pull request #177 from antmicro/arty-dynamic-ip
...
target/arty: add eth_ip_configurable switch
2021-02-24 09:29:55 +01:00
08ccf384aa
targets/arty: Allow selection of sdcard mod adaptor
...
The default stays with the Digilent/Antmicro layout, but the user can
optionally provide --sdcard-adaptor numato to use the Numato layout.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
ae0d4dc0d8
target/arty: add eth_dynamic_ip switch
2021-02-23 21:01:27 +01:00
aad8154e3a
targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.
2021-02-23 15:27:50 +01:00
11405d9ee3
targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.
2021-02-18 19:30:05 +01:00
9a94e835c3
sockit: Add an option to plug in an UART via the GPIO daughter board
2021-02-10 14:52:19 +07:00
ea58ef94a7
Merge pull request #170 from hansfbaier/master
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arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-04 16:44:58 +01:00
38242b713f
Merge pull request #171 from antmicro/symbiflow_nexys_video_support
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nexys_video: enable symbiflow toolchain
2021-02-04 16:42:34 +01:00
e6d05001aa
use parameter for dram channel 0 or 1 and LedChaser
2021-02-03 17:29:30 -05:00
cdff5e3ca3
nexys_video: enable symbiflow toolchain
...
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 14:52:54 +01:00
c64e13f687
arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-03 09:37:03 +07:00
8692ed462f
targets/colorlight_i5: use .bit stream instead of .svf when loading.
2021-02-03 08:17:24 +09:00
31d7f810e7
use SDRAM C1 sysclk and constraints
2021-02-02 11:15:25 -05:00
f32c61d5d2
Merge pull request #163 from garytwong/friendly-incompatible-options
...
Be friendlier about incompatible options.
2021-02-02 08:51:46 +01:00
7c48af9b50
tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
...
./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
2021-02-01 13:32:01 +01:00
51c5d69586
targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources.
2021-02-01 13:31:56 +01:00
538878ce13
tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?).
2021-02-01 13:31:51 +01:00
6cce07d9db
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
2021-02-01 13:31:44 +01:00
0831b33285
tec0117: fix copyrights.
2021-02-01 13:31:39 +01:00
5e4b29c0b5
sockit: Fix cable name, default to jtag_atlantic
2021-02-01 11:48:06 +07:00
601c297c8f
Merge pull request #164 from rdolbeau/ztex213
...
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 21:43:07 +01:00
31df53ef0a
Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)
2021-01-30 13:19:08 +01:00
027e57b851
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 05:19:18 -05:00
99e2f04ee5
Be friendlier about incompatible options.
...
Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s. That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.
2021-01-29 18:08:38 -07:00
abccd12058
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
...
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
2021-01-29 22:28:40 +01:00
edb99797aa
targets/tec0117: minor cleanups.
2021-01-29 21:25:10 +01:00
3deeb69531
targets/fpc_iii: review/cleanup to increase similarities with others targets to ease maintenance.
2021-01-29 08:46:31 +01:00
4e5bb1bf1e
Add FPC-III board support.
...
FPC-III is the Free Permutable Computer; details on the board are
available from:
https://repo.or.cz/fpc-iii.git
2021-01-28 09:51:42 -07:00
9bd667720d
targets/ecpix5: add LedChaser with red leds.
...
Fits nicely LambdaConcept colors and Blue/Green leds are too bright and would need to be controlled through a PWM.
2021-01-28 14:29:07 +01:00
bd716d956f
netv2: add device variant to allow 100T as well
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-01-28 13:19:53 +01:00
aef78831c8
colorlight_i5: Use tx_delay=0 for LiteEthPHYRGMII instead of target specifig bios initialization
2021-01-27 18:19:27 +09:00
84656a9c2e
re-compare and adjust to u250
2021-01-26 23:03:09 -05:00
c3fa0eac8b
Add colorlight i5 board support
2021-01-27 11:44:59 +09:00
5fd04a97ea
targets/netv2/pcie: reduce max_pending_requests to 2 to reduce resource usage.
2021-01-26 11:01:51 +01:00
d256cc8bd6
camlink_4k: disable leds when serial is used (since pin is shared).
2021-01-25 12:19:29 +01:00
1e1bec10c4
orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.
2021-01-25 11:52:59 +01:00
537f494cbb
arrow_sockit: review/harmonize with others boards.
2021-01-25 09:14:46 +01:00
bbaa2fdc98
Merge pull request #149 from hansfbaier/master
...
Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
2021-01-25 08:55:48 +01:00
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash
...
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-24 21:22:35 +01:00
72985c72ca
Merge pull request #153 from Disasm/ecpix5-add-45f
...
ECPIX-5: add option to select ECP5 device
2021-01-24 21:14:14 +01:00
cae51c0c24
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-23 14:44:26 -06:00
c9f0745d54
sockit: add board definitions for Terasic SocKit
2021-01-23 20:17:38 +07:00
23760e2eae
orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC).
2021-01-22 22:55:02 +01:00
a678672fc9
ecpix5: add option to select ECP5 device
2021-01-19 01:22:52 +03:00
e71a4940c0
nexys4ddr: etherbone support
2021-01-15 12:14:40 -05:00
7a738245af
fix bitstream problem
2021-01-14 21:53:25 -05:00
5a73eb0b6d
initiate target and platform for alveo_u280 board
2021-01-14 18:35:43 -05:00
6a5f2f59a6
targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands.
...
This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.
Also remove un-needed cd_sys2x_eb.
2021-01-12 18:57:22 +01:00
9ff90eb9fe
targets/c10lprefkit: fix default sys-clk-freq.
2021-01-12 16:15:52 +01:00
0a7443d273
targets/orangecrab: make usr_btn optional to fix compilation with revision 0.1.
2021-01-08 19:30:37 +01:00
ae5494d7b6
orangecrab: defaults to USB-ACM UART.
2021-01-08 19:01:41 +01:00
c6e75122d9
sds1104xe: defaults to Crossover UART.
2021-01-08 19:00:41 +01:00
ab72f69937
targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.
2021-01-08 18:50:01 +01:00
0ee62dd681
add etherbone ip address option for relevant boards
2021-01-08 18:44:31 +01:00
869cce2bba
targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip.
...
eth-ip will also be used to configure Ethernet IP addresss.
2021-01-07 09:26:38 +01:00
c829a47c31
targets/colorlight_5a_75x: Automatically disable Led Chaser when serial is used.
2021-01-07 09:17:28 +01:00
adbcc81ecf
Merge pull request #145 from hansfbaier/master
...
colorlight: Add option for etherbone ip address and LED chaser
2021-01-07 09:08:43 +01:00
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard
...
genesys2: LiteSDCard support
2021-01-07 08:12:24 +01:00
d73bd2f7ce
targets/xilinx: add comment on sys_clk to pll.clkin false path.
2021-01-07 08:01:54 +01:00
1ac1c6857f
targets/xilinx: add false path constraint between sys_clk and pll.clkin.
...
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
2021-01-07 00:02:46 +01:00
0d69cfa6b0
colorlight: make LEDs optional
2021-01-05 08:03:26 +07:00
4bec17e1a7
colorlight: Add option for etherbone ip address
2021-01-05 07:49:44 +07:00
2589d9f704
genesys2: add (spi-)sdcard build options
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:57:21 -05:00
fe67766fb7
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
2021-01-04 11:38:07 +01:00
0e3c03f2f6
mercury_xu5: remove unneeded cmd_latency=0 (now defaulting to 0).
2021-01-04 10:48:34 +01:00
5cc49bafbd
orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press).
2021-01-04 09:42:05 +01:00
1fb24d4c71
orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset.
...
Allows the USB-ACM link to stay up during reset.
2021-01-04 09:05:19 +01:00
06cb49af37
targets/arty: add variant support through --variant args.
...
./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
2020-12-29 18:43:14 +01:00
02a81d54e2
targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01).
2020-12-29 16:01:12 +01:00
84098d2de5
targets/qmtech_wukong: submitted target was the platform file, update with target shared in #133 .
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Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.
2020-12-29 14:13:11 +01:00
e380f24655
targets/qmtech_wukong: +x.
2020-12-29 13:24:41 +01:00
4b721eded7
add QmTech Wukong board support.
2020-12-29 13:20:42 +01:00
9beaf25822
nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue.
2020-12-24 10:15:29 +01:00
2a04c5c74e
nexys4ddr: add support for litexvideo VGA Terminal
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This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.
The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
2020-12-23 02:24:18 +05:30
f6a106cdf4
Fix orangecrab target
2020-12-20 01:07:43 +03:00
00fc2c5166
targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM.
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Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
2020-12-16 11:52:58 +01:00
bb58258fd4
Fix de10nano target
2020-12-14 15:27:33 +03:00
519f9449fa
targets/sds1104: litex_term now directly supports crossover uart.
2020-12-10 13:56:01 +01:00
18337cdf25
targets/arty: sync with litex repository
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-07 17:32:40 +01:00
Hans Baier
Florent Kermarrec
Karol Gugala
Jędrzej Boczar
Shinken Sanada
Sergiu Mosanu
Romain Dolbeau
Alessandro Comodi
Kaz Kojima
Stafford Horne
Joel Stanley
Aleksandra Swierkowska
Jan Kowalewski
Guillaume REMBERT
Gary Wong
Blake Smith
Vadim Kaushan
Gabriel Somlo
Sahaj Sarup
Robert Winkler