4fc9df8414
colorlight_5a_75b/v6.1: Add eth_clock & serial pins
2020-04-09 05:06:08 +02:00
4ddde31429
colorlight_5a_75b/v6.1: Fix bank activate pin
2020-04-09 05:05:29 +02:00
9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios
...
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-04-08 09:00:12 +02:00
db67dff0ea
targets/de10lite: use Max10PLL, remove 50MHz limitation.
2020-04-08 08:55:30 +02:00
8ccab03358
targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
2020-04-08 08:34:59 +02:00
4cdc121327
targets/de10nano: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:11:04 +02:00
2d8a4ef9ec
targets/de1_soc: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:07:37 +02:00
cec4cbb6dc
targets/de2_115: use CycloneIVPLL, remove 50MHz limitation.
2020-04-08 08:03:41 +02:00
1fac6077fb
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:01:58 +02:00
5f629c203b
targets/vcu118: fix clk500 typo.
2020-04-07 13:53:22 +02:00
a7fbe0a724
colorlight_5a_75b: add SoC with regular UART (on J19).
2020-04-03 10:28:53 +02:00
19e5366ad1
targets/colorlight_5a_75b: update sys/sys_ps phases.
2020-03-31 18:18:45 +02:00
9ae8a0cc11
colorlight_5a_75b/v7.0: add spiflash pins.
2020-03-31 16:18:12 +02:00
a43072ac40
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-03-28 13:08:46 +01:00
ccfc021c1a
Merge pull request #61 from ilya-epifanov/ecp5-evn-programming
...
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 12:59:19 +01:00
8afc9a5b03
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 11:27:34 +01:00
89dd00d3a2
platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms).
2020-03-27 13:01:36 +01:00
d2edf54ab3
zcu104: add fully working SO-DIMM config
2020-03-26 16:37:11 +01:00
3b91e96c42
targets/add_constant: avoid specifying value when value is None (=default)
2020-03-26 09:47:22 +01:00
555bf6c4dc
targets/Ultrascale(+): enable USDDRPHY_DEBUG.
2020-03-26 09:17:09 +01:00
4053c02d7e
targets/orangecrab: add USB PLL for USB CDC with ValentyUSB.
2020-03-25 19:38:36 +01:00
85f38876c2
targets: update PCIe on Numato targets.
...
Should be compatible with software from: https://github.com/enjoy-digital/netv2 .
2020-03-25 11:53:52 +01:00
6e6b6dac55
platforms/orangecrab: add spisdcard pins.
2020-03-25 10:21:57 +01:00
87fd4dc059
platforms/minispartan6: add spisdcard pins.
2020-03-25 09:53:04 +01:00
24033e331c
targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 19:59:42 +01:00
92f793f9c5
platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 19:58:12 +01:00
eb35ec92ba
orangecrab: combine revisions in target
2020-03-23 09:20:01 +10:30
159360da2c
orangecrab: Add r0.2 support
2020-03-22 21:04:07 +10:30
bf3c9dc9bf
orangecrab: Add sdram selection option
2020-03-22 20:41:12 +10:30
88d3f1d63e
orangecrab: r0.1 OrangeCrab fixes
2020-03-22 20:14:29 +10:30
78224b1e56
targets/colorlight_5a_75b: add SDRAM.
2020-03-21 22:11:47 +01:00
a95a4eed3f
targets/colorlight_5a_75b: switch to add_ethernet/add_etherbone methods.
2020-03-21 21:50:05 +01:00
7bba5caab0
targets/c10prefkit: remove keep attributes (no longer needed, added automatically).
2020-03-21 21:44:44 +01:00
6c31933e89
targets: switch to add_etherbone method.
2020-03-21 21:40:45 +01:00
159386e3d3
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 20:00:56 +01:00
3fb3ba18e8
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-21 18:29:52 +01:00
83e6fb29f8
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-21 12:43:39 +01:00
33bf1d3ee2
Merge pull request #58 from gsomlo/gls-trellisboard-spisdcard
...
Move trellisboard target to SoCCore, add SPI-mode SDCard support
2020-03-20 19:07:00 +01:00
fb1cab857a
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:59:17 +01:00
f021c1de5f
targets/trellisboard: add '--with-spi-sdcard' build option
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-20 07:14:13 -04:00
69a78c8c66
targets/trellisboard: switch to SoCCore, use add_ethernet() method
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
396b0383c8
platforms/trellisboard: fix "sdcard" pads, add "spisdcard" pads
...
Add support for SPI-mode SDCard interface. Also, add pull-up and
slew constraints to the standard sdcard interface.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
d0d047dfa4
platforms/ulx3s: add spisdcard pins.
2020-03-19 15:14:05 +01:00
6ab13a0661
de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target.
2020-03-19 11:09:48 +01:00
db9d5489ec
Merge pull request #56 from rob-ng15/master
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de10nano add in support for MiSTer secondary sd card
2020-03-19 11:07:40 +01:00
57bcadb5b4
platforms/nexys4ddr: add spisdcard pins.
2020-03-19 11:04:11 +01:00
f3d7f5880f
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:09:52 +01:00
bc6ef0bc48
Allow access to secondary sd card via hardware spi bitbanging
2020-03-18 12:13:37 +00:00
a6f80694cb
Add in support for secondary sd card via spi hardware bitbanging
2020-03-18 12:11:57 +00:00
a99d258411
targets/icebreaker: use simplified version closer to the others targets.
...
Add description of the board, link to the crowdsupply campaign and to the more complete example.
2020-03-13 09:43:43 +01:00
74a5ffb9ef
targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
...
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
2020-03-10 16:58:30 +01:00
e2a66090ee
targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
2020-03-10 16:55:22 +01:00
cf58550bba
targets/Ultrascale+: use USPDDRPHY.
2020-03-10 16:06:48 +01:00
ce922613a7
Merge pull request #55 from antmicro/jboc/mercury-xu5
...
platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:30:12 +01:00
90de99eb46
platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:03:31 +01:00
75286f8a9b
platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31)
2020-03-10 14:57:39 +01:00
95e1a05bf1
platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:29:49 +01:00
3f191c8561
mercury_xu5: set INTERNAL_VREF to 0.84. (similar to others Ultrascale boards with DDR4).
2020-03-09 09:28:25 +01:00
f4ae21a7a2
zcu104: fix copyrights.
2020-03-09 09:24:06 +01:00
5031c11d57
mercury_xu5: add missing copyrights.
2020-03-09 09:23:08 +01:00
8c535d15f2
platforms/mercury_xu5: replace ' with ".
2020-03-09 09:21:27 +01:00
dc1371108d
Merge pull request #52 from antmicro/jboc/mercury-xu5
...
add Enclustra Mercury XU5 board
2020-03-09 09:11:15 +01:00
2b1b9684de
targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset.
2020-03-07 18:25:26 +01:00
9416ddd84a
targets/icebreaker: simplify arguments and make it closer to others targets.
2020-03-07 18:13:02 +01:00
992f7066fa
targets/icebreaker: simplify leds.
2020-03-07 18:12:59 +01:00
682316214c
targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy.
2020-03-07 18:12:52 +01:00
f777d4b08c
targets/icebreaker: +x
2020-03-05 23:11:35 +01:00
6f517ad1d6
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 10:57:59 +01:00
d002059e0b
add Enclustra Mercury XU5 board
2020-03-05 10:52:32 +01:00
745c99ba14
icebreaker: Updated to build on newer litex. Disabled bios building.
2020-03-05 00:12:18 -08:00
3ac9d927a9
targets: icebreaker: Minor style fixes.
2020-03-05 00:12:18 -08:00
738967176c
targets: icebreaker: set the boot address to point to SPI flash
...
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
093e4913c4
targets: icebreaker: hack to get boot working
...
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
77b780eb4b
targets: icebreaker: switch to single SPI
...
The Icebreaker doesn't have the QE/ bit set in config, so default to
using single SPI.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
e6dcdc31ed
targets: icebreaker: fix cpu and add spi flash
...
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
0185095782
targets: icebreaker: fix argument parsing for cpu
...
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
f0dd31f6c8
target: targets: add crg and begin getting it working
...
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
ce9b67e2ee
Added icebreaker platform and target.
...
Target is heavily based on Fomu.
2020-03-05 00:12:18 -08:00
7b4ca20ff4
platforms.colorlight_5a_75b: add J1-J8 connectors
2020-02-28 06:09:44 -08:00
be5ed35871
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:46:54 +01:00
b44885d222
vc707: fix copyrights (Michael Betz is the initial author)
2020-02-28 08:39:52 +01:00
b89af28a05
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 12:58:52 +01:00
aaa10c69eb
platforms/colorlight_5a_75b: add default_clk_name/period
2020-02-27 11:16:49 +01:00
d8de4fbdfb
platforms/targets: keep in sync with LiteX
2020-02-27 11:06:53 +01:00
18f65a7f9d
platforms/kc705: cleanup ddram.
2020-02-27 11:06:35 +01:00
d4460c11a5
platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm.
2020-02-27 10:43:41 +01:00
58f588f69e
platforms/zcu104/ddram: add PRE_EMPHASIS/EQUALIZATION settings
2020-02-27 10:43:01 +01:00
d87b8b3c66
zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
...
Ease switching between ddram_32 and ddram_64.
2020-02-27 10:05:17 +01:00
8ecfb13f3c
zcu104: add copyrights
2020-02-27 09:57:26 +01:00
22b0449509
Merge pull request #47 from antmicro/zcu104
...
Add support for ZCU104 board
2020-02-27 09:51:54 +01:00
608541d5b8
add ZCU104 board
2020-02-26 13:53:21 +01:00
e516ff3452
vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:51 +01:00
9d2ca50c5f
kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins.
2020-02-26 10:16:35 +01:00
83d2c71099
platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks
2020-02-25 18:32:42 +01:00
4a84e9b08a
targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool
2020-02-25 12:47:08 +01:00
f279fe9d33
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
2020-02-25 10:35:18 +01:00
3581df5af6
vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported)
2020-02-25 09:41:53 +01:00
88a1f80db1
vc707/vcu118: use proper copyrights
2020-02-25 09:03:52 +01:00
373e74f435
add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
2020-02-24 14:20:47 -05:00
2cf4e084ec
platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins
2020-02-23 10:01:41 +01:00
f72e7bd314
Merge pull request #41 from lromor/fix-wrong-import
...
Changed wrong imports for fomu board.
2020-02-12 18:48:13 +07:00
ec30cc05c3
Changed wrong imports for fomu board.
2020-02-12 12:40:07 +01:00
c94360c2e0
targets: avoid direct use of mem_decoder.
2020-02-11 21:59:42 +01:00
4edf196911
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:45:35 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
7a24406b2e
targets: fomu: fix compatibility for when a cpu is added
...
Things weren't quite right for adding a CPU. This fixes that by
correcting the placer arguments, memory map, and USB type.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-03 08:58:54 +08:00
0627f55dca
de10nano: cleanup a bit, rename SDRAMSoC to MiSTerSDRAMSoC and argument to --with-mister-sdram to make it clear that it's using the MiSTer SDRAM extension board.
2020-01-31 09:29:02 +01:00
cf9a9ff91b
de10nano: update copyrights, remove trailing whitespaces
2020-01-31 09:13:36 +01:00
36e1f1fe75
rename sw to user_sw
2020-01-30 05:01:46 -08:00
1631b071c3
finish up sdram, passes memtest
2020-01-30 03:41:44 -08:00
5091a1b40a
WIP sdram module option
2020-01-29 13:59:57 -08:00
3a6a9258ce
add de10 nano board
...
add iostandard to hdmi
2020-01-29 00:21:51 -08:00
2ec6bc0bdc
colorlight_5a_75b: add disclaimer
2020-01-23 14:13:13 +01:00
55c0b781e4
colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt)
2020-01-23 13:16:36 +01:00
4fb89fc9c5
colorlight_5a_75b: set RGMII tx/rx_delay to 0ns in the FPGA (added by PCB/PHY)
2020-01-23 09:39:48 +01:00
dcc65b347d
targets/colorlight_5a_75b: switch to SoCCore, CPU and Etherbone working :)
...
Tested with:
./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv
Load with following script:
#!/usr/bin/env python3
# Load ---------------------------------------------------------------------------------------------
def load():
import os
f = open("openocd.cfg", "w")
f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
f.close()
os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
exit()
if __name__ == "__main__":
load()
Then start lxserver:
lxserver --udp
And run following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
while True:
if wb.regs.uart_xover_rxempty.read() == 0:
print(chr(wb.regs.uart_xover_rxtx.read()), end="")
sys.stdout.flush()
# # #
wb.close()
2020-01-22 15:57:52 +01:00
c07e4a6b3a
colorlight_5a_75b: fix rst_n
2020-01-22 14:57:48 +01:00
8da8ed7a0e
colorlight_5a_75b/v7.0: update eth_clocks/rx pinout, remove FIXME
2020-01-22 14:56:17 +01:00
bb805999cb
platforms/colorlight_5a_75b: fix 6.1 used_led_n/user_btn_n thanks @smunaut
2020-01-22 12:43:37 +01:00
43badd162e
colorlight_5a_75b/v6.1: add led/btn and remove FIXME on sdram now that clarified
2020-01-22 11:05:08 +01:00
1d9e349093
partner: add colorlight_5a_75b initial support
2020-01-22 09:51:00 +01:00
07067301d5
targets/linsn_rv901t: cleanup arguments
2020-01-22 09:04:28 +01:00
8113b491db
aller/nereid/tagus: update litepcie
2020-01-21 21:26:23 +01:00
684c1640bb
add Linsn RV901T support
2020-01-18 21:40:04 +01:00
0e4569a48a
platforms/camlink_4k: remove #!/usr/bin/env python3
2020-01-18 21:35:18 +01:00
e72cd1468c
platforms/ac701: fix eth indent
2020-01-18 21:34:50 +01:00
908539d49f
targets/nexys4ddr: fix typo
2020-01-17 13:15:22 +01:00
bb99a8dd0c
targets/kcu105: remove main_ram_size_limit
2020-01-17 12:09:53 +01:00
eca9bf10ae
mimas_v7: cleanup, make it similar to others boards
2020-01-16 11:24:09 +01:00
54f39b600a
mimas_a7: fix copyrights
2020-01-16 11:02:11 +01:00
8d298951a8
Merge pull request #37 from feliks-montez/master
...
Add Mimas A7 board support
2020-01-16 11:00:32 +01:00
f9619c4a8f
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
2020-01-16 10:51:35 +01:00
fd1e655700
targets: cleanup EthernetSoC
2020-01-16 10:28:09 +01:00
206ec34551
platforms/mimas_a7: add support
2020-01-14 23:31:03 -05:00
9f1c3305b6
targets/mimas_a7: add support
2020-01-14 23:30:49 -05:00
50d550c911
kx2: cleanup, fix copyright
2020-01-13 17:22:33 +01:00
3811b58f32
Merge pull request #36 from Marrkson/master
...
ADD: KX2 and DDR3 support
2020-01-13 17:07:16 +01:00
c109b36fb9
travis: update/fix
2020-01-13 17:00:01 +01:00
028d4a78aa
targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
2020-01-13 15:20:37 +01:00
13e5ca03a5
ADD: KX2 and DDR3 support
2020-01-13 14:21:54 +01:00
beccf670e5
hadbadge: fix _CRG
2020-01-11 10:46:23 +01:00
15f3457aea
platforms/de0nano/serial: add gpio names in comment
2020-01-10 18:53:52 +01:00
94ba343daf
targets/ac701: cpu_reset is active high
2020-01-10 18:53:14 +01:00
ab01f70e5c
platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq
2020-01-09 21:56:01 +01:00
7afe3dc674
platforms/targets: sync with litex
2020-01-09 21:10:59 +01:00
4192b20f09
targets: cleanup Altera CRGs
2020-01-09 19:46:39 +01:00
9e9fc5ef78
platforms: always use 1e9/clk_freq for default_clk_period
2020-01-09 19:28:50 +01:00
fe23881348
Merge pull request #33 from msloniewski/master
...
targets/de10lite: use external clock for sys directly
2020-01-09 19:23:55 +01:00
aaf8d54c6a
targets/de10lite: use AsyncResetSynchronizer for clock domains
...
At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
2020-01-09 18:47:13 +01:00
d08dfdb808
platforms/nexys4ddr: add sdcard pins (sync w. litex commit #e99740e8)
2020-01-09 09:25:19 -05:00
David Sawatzke
enjoy-digital
Ilya Epifanov
Piotr Binkowski
Greg Davill
Gabriel Somlo
rob-ng15
Jędrzej Boczar
Piotr Esden-Tempski
Sean Cross
Tom Keddie
Fei Gao
Gwenhael Goavec-Merou
Leonardo Romor
Paul Sajna
Feliks
Mark
Marcin Sloniewski