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533 Commits 42 Branches 14 Tags 30 MiB
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428 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 5c0cc6292c fhdl: export log2_int 2012-03-14 12:19:42 +01:00
Sebastien Bourdeauducq bfcd4e636b fhdl: handle negative constants correctly 2012-03-08 20:49:24 +01:00
Sebastien Bourdeauducq ab800fa2ed bus: generic transaction model 2012-03-08 18:14:06 +01:00
Sebastien Bourdeauducq 678a89d572 sim: fix zero encoding 2012-03-08 15:34:08 +01:00
Sebastien Bourdeauducq decbd069fa sim: fix message debug formatting 2012-03-08 15:27:35 +01:00
Sebastien Bourdeauducq 98e96b3952 sim: make initialization cycle optional (selectable by function attribute) 2012-03-06 19:43:59 +01:00
Sebastien Bourdeauducq 8160ced2e9 sim: memory access 2012-03-06 19:29:39 +01:00
Sebastien Bourdeauducq db8f8bf2e3 fhdl: register memory objects with namespace 2012-03-06 18:33:44 +01:00
Sebastien Bourdeauducq 6f829c7afc sim: support for signed numbers 2012-03-06 16:46:18 +01:00
Sebastien Bourdeauducq 90184b22d2 fhdl/verilog: fix signed constant conversion 2012-03-06 16:45:44 +01:00
Sebastien Bourdeauducq 9da512dbf5 sim: VCD generation 2012-03-06 15:26:04 +01:00
Sebastien Bourdeauducq 22b3c11b93 sim: clean startup/shutdown 2012-03-06 15:00:02 +01:00
Sebastien Bourdeauducq 06de17b16c sim: remove temporary files and socket 2012-03-06 14:20:26 +01:00
Sebastien Bourdeauducq 7230508e7c fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles 2012-03-06 14:18:22 +01:00
Sebastien Bourdeauducq 2c375e900f sim: remove default sockaddr 2012-03-06 13:58:49 +01:00
Sebastien Bourdeauducq 8d16fde48c fhdl: add simulation functions in fragment 2012-03-06 13:58:22 +01:00
Sebastien Bourdeauducq aac9752558 sim: basic functionality working 2012-03-05 20:31:41 +01:00
Sebastien Bourdeauducq 29859acc34 sim: two way IPC working 2012-03-04 19:17:03 +01:00
Sebastien Bourdeauducq 8586daf2dd sim: IPC module (lacks str/int encoding) 2012-03-03 18:55:38 +01:00
Sebastien Bourdeauducq 1b8cb5b46c bus/dfi: fix multiphase naming 2012-02-19 17:57:04 +01:00
Sebastien Bourdeauducq d8d4e81b6e bank/csrgen: fix RE generation 2012-02-18 18:56:18 +01:00
Sebastien Bourdeauducq 55a265d967 bank: add RE signal for registers made of fields 2012-02-17 23:52:06 +01:00
Sebastien Bourdeauducq 92dfbb92dd bus: add interconnect statements function 2012-02-17 23:51:32 +01:00
Sebastien Bourdeauducq f995e8b92e fhdl: check we pass BV to signals 2012-02-17 23:50:54 +01:00
Sebastien Bourdeauducq a1ad30faab fhdl/verilog: properly connect instance inouts 2012-02-17 11:08:41 +01:00
Sebastien Bourdeauducq ca7056b07f fhdl: support forwarding of bidirectional signals from instance ports 2012-02-16 18:34:32 +01:00
Sebastien Bourdeauducq c08687b9c6 bus/dfi: filter signals by direction 2012-02-15 21:48:05 +01:00
Sebastien Bourdeauducq ef7aea0f31 bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY 2012-02-15 18:23:31 +01:00
Sebastien Bourdeauducq fa9cf3e466 bus: add DFI 2012-02-15 18:09:14 +01:00
Sebastien Bourdeauducq 91e279ee04 bank/csrgen: use new bus API 2012-02-15 16:42:17 +01:00
Sebastien Bourdeauducq af5230c8ee bus: fix simple interconnect 2012-02-15 16:42:05 +01:00
Sebastien Bourdeauducq 0493212124 bus: simplify and cleanup 
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
 2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq 46b1f74e98 bus/asmibus/hub: forward data and tag_call 2012-02-14 14:00:17 +01:00
Sebastien Bourdeauducq 0c214b484e Use double quotes for all strings 2012-02-14 13:12:43 +01:00
Sebastien Bourdeauducq e11d9b9322 bus/wishbone2asmi: cache hits working 2012-02-13 23:11:16 +01:00
Sebastien Bourdeauducq 1662e1b3bc corelogic: support reverse in displacer/chooser 2012-02-13 23:10:27 +01:00
Sebastien Bourdeauducq 264be80f2d Fix syntax errors and other stupid problems 2012-02-13 22:28:02 +01:00
Sebastien Bourdeauducq 8a61d9d121 bus/csr: Rename a->adr d->dat to be consistent with the other buses 2012-02-13 21:46:39 +01:00
Sebastien Bourdeauducq 060426cb59 bus/wishbone2asmi: set WM, and send 0 when inactive 2012-02-13 16:49:43 +01:00
Sebastien Bourdeauducq cad9d3b960 bus: Wishbone to ASMI caching bridge (untested) 2012-02-13 16:29:38 +01:00
Sebastien Bourdeauducq 244bf17db7 corelogic/misc: displacer + chooser 2012-02-11 20:57:08 +01:00
Sebastien Bourdeauducq e10e4360f3 corelogic/misc/multimux: less confusing variable name 2012-02-11 20:56:51 +01:00
Sebastien Bourdeauducq 7894411418 bus/asmibus: fix typo 2012-02-11 20:56:01 +01:00
Sebastien Bourdeauducq 28b0c340af corelogic/record: add to_signal convenience function 2012-02-11 20:55:23 +01:00
Sebastien Bourdeauducq e62ac1d3a1 corelogic/misc: contiguous split 2012-02-11 11:52:15 +01:00
Sebastien Bourdeauducq ef436a1ec9 bus/asmibus: add get_slots, fix get_fragment 2012-02-10 17:49:06 +01:00
Sebastien Bourdeauducq 945d655d45 bus: ASMI hub (untested) 2012-02-10 15:21:04 +01:00
Sebastien Bourdeauducq 47883675db bus/wishbone2csr: truncate WB data 2012-02-06 18:43:34 +01:00
Sebastien Bourdeauducq 1eb348c573 fhdl: do not attempt slicing non-array signals to keep Verilog happy 2012-02-06 18:07:02 +01:00
Sebastien Bourdeauducq fcd6583cbb bank: event manager 2012-02-06 17:39:32 +01:00
Sebastien Bourdeauducq 3a2a0c4dd8 bank: support registers larger than the bus word width 2012-02-06 16:15:27 +01:00
Sebastien Bourdeauducq f3ddfffc47 bank: refactoring 2012-02-06 13:55:50 +01:00
Sebastien Bourdeauducq 1a86f26a66 bank/csrgen: use enumerate 2012-02-06 11:18:30 +01:00
Sebastien Bourdeauducq 629e771fc0 fhdl/structure: binary constant builder 2012-02-05 19:32:11 +01:00
Lars-Peter Clausen 8380318e84 Use enumerate(x) instead of zip(range(x), x) 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2012-02-02 21:28:00 +01:00
Lars-Peter Clausen 2b3f00cbc1 fhdl/namer: Add support for STORE_DEREF opcode 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2012-02-02 21:15:10 +01:00
Sebastien Bourdeauducq 6a9b59786b fhdl/namer: extract variable names with bytecode inspection 2012-01-28 23:17:44 +01:00
Sebastien Bourdeauducq 5c2df45577 fhdl: do not prefix instance signal names 2012-01-28 11:39:28 +01:00
Sebastien Bourdeauducq a99c2acfa8 Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
Sebastien Bourdeauducq 685b5eb08f fhdl: support memory read enable 2012-01-27 21:39:23 +01:00
Sebastien Bourdeauducq 0cc7e2ac1e fhdl: make WRITE_FIRST default 2012-01-27 21:35:58 +01:00
Sebastien Bourdeauducq 5405a83ff9 fhdl: memories working 2012-01-27 20:22:17 +01:00
Sebastien Bourdeauducq a5bd111370 fhdl/verilog: clean up signal classification and support memory descriptions 2012-01-27 16:54:48 +01:00
Sebastien Bourdeauducq 6b1d775e9f fhdl/structure: memory description 2012-01-27 16:53:34 +01:00
Sebastien Bourdeauducq 1966117e17 flow/ala: fix typo for And (thanks Lars) 2012-01-22 00:32:02 +01:00
Sebastien Bourdeauducq 076c171c7b Use meaningful class names 2012-01-20 23:07:32 +01:00
Sebastien Bourdeauducq d3d5b481fe Include fragment pads in pre-naming dictionary 2012-01-20 22:59:40 +01:00
Sebastien Bourdeauducq 039c6d8eb4 namer/trace_back: behave on None code_context 2012-01-20 22:52:50 +01:00
Sebastien Bourdeauducq e9be3241f6 Fix instance support 2012-01-20 22:36:17 +01:00
Sebastien Bourdeauducq e4f531a739 Include unused I/Os in pre-naming dictionary and register signals with name_override 2012-01-20 22:20:32 +01:00
Sebastien Bourdeauducq 904d14d4cf Remove NoContext 2012-01-20 22:15:44 +01:00
Sebastien Bourdeauducq 05b20d4987 Only include context prefix when necessary 2012-01-19 19:25:04 +01:00
Sebastien Bourdeauducq fc473e31eb Fix disjoint namespace test 2012-01-19 19:24:43 +01:00
Sebastien Bourdeauducq 00d3eb7989 Always include last step in names 2012-01-19 18:42:43 +01:00
Sebastien Bourdeauducq 4eac60d181 New naming system: second attempt 2012-01-19 18:25:25 +01:00
Sebastien Bourdeauducq 4c85d921b3 corelogic/record: empty default name 2012-01-16 19:38:14 +01:00
Sebastien Bourdeauducq bdde97f5fd New naming system beginning to work 2012-01-16 18:42:55 +01:00
Sebastien Bourdeauducq ab8e08a2ed fhdl: new naming system (broken) 2012-01-16 18:09:52 +01:00
Sebastien Bourdeauducq e6bfad498d actorlib/control: 'for' generator 2012-01-15 22:08:33 +01:00
Sebastien Bourdeauducq c3d7b98b43 dma_wishbone: small syntax simplification thanks to None statements 2012-01-15 17:46:15 +01:00
Sebastien Bourdeauducq aa8b8da684 fhdl: allow None statements 2012-01-15 17:45:54 +01:00
Sebastien Bourdeauducq 85491efc68 wishbone_dma: convert to new endpoint API and fix some bugs 2012-01-15 16:41:15 +01:00
Sebastien Bourdeauducq 77b3c8e3bb bus: list signals 2012-01-15 15:48:51 +01:00
Sebastien Bourdeauducq 3c7161cc34 flow: saner endpoint management 2012-01-15 15:09:44 +01:00
Sebastien Bourdeauducq 20425703fa Wishbone: omit fixed LSBs 2012-01-13 17:29:05 +01:00
Sebastien Bourdeauducq 077fd9fdbc actorlib: Wishbone DMA read master (WIP) 2012-01-10 17:10:18 +01:00
Sebastien Bourdeauducq c93eb5f482 record: return offset 2012-01-10 17:10:03 +01:00
Sebastien Bourdeauducq a6e5f3e766 flow: simplify actor fragment interface 2012-01-10 15:54:51 +01:00
Sebastien Bourdeauducq 683e6b4a6c record: support aligned flattening 2012-01-09 19:16:11 +01:00
Sebastien Bourdeauducq b06e70d849 corelogic: FSM 2012-01-09 16:28:48 +01:00
Sebastien Bourdeauducq 47ae303846 record: cleanup 2012-01-09 15:20:09 +01:00
Sebastien Bourdeauducq cef1c5d3af record: better exception code 2012-01-09 15:17:24 +01:00
Sebastien Bourdeauducq 89bf704b2b record: preserve order 2012-01-09 15:14:42 +01:00
Sebastien Bourdeauducq bdcaeb159b flow: draw network graph 2012-01-09 14:21:54 +01:00
Sebastien Bourdeauducq d26ded93d8 flow: actor busy signal 2012-01-09 14:21:45 +01:00
Sebastien Bourdeauducq d2d55372d8 Composer (WIP) 2012-01-08 13:56:11 +01:00
Sebastien Bourdeauducq 34c69db14a endpoint: add _i/_o suffix on signal names 2012-01-07 21:21:46 +01:00
Sebastien Bourdeauducq cdd9977a40 fhdl: better signal naming heuristic 2012-01-07 15:30:14 +01:00
Sebastien Bourdeauducq b6763c28ea constant: equality 2012-01-07 12:29:47 +01:00
Sebastien Bourdeauducq 7b395b565e verilog: split comb block, use assign statements 2012-01-07 12:19:06 +01:00
Sebastien Bourdeauducq f209bf6b33 convtools -> tools 2012-01-07 00:39:28 +01:00
Sebastien Bourdeauducq 0b195a244d flow: network 2012-01-07 00:33:28 +01:00
Sebastien Bourdeauducq 3c1dada9cf record: compatibility check 2012-01-06 23:00:23 +01:00
Sebastien Bourdeauducq 588f1a259e flow: plumbing 2012-01-06 17:24:05 +01:00
Sebastien Bourdeauducq 8f1bf508ca actor: simplified automatic control 2012-01-06 15:35:17 +01:00
Sebastien Bourdeauducq a3bf877802 ALA: use records for tokens 2012-01-06 14:32:00 +01:00
Sebastien Bourdeauducq 038992e7d2 corelogic: record 2012-01-06 11:20:44 +01:00
Sebastien Bourdeauducq d7a3bed44c Signal repr 2012-01-06 11:20:33 +01:00
Sebastien Bourdeauducq 9366a226bb Convert -> convert 2012-01-05 19:27:33 +01:00
Sebastien Bourdeauducq edf90870c2 flow: sum and division actors 2011-12-23 00:35:53 +01:00
Sebastien Bourdeauducq 76db20cd9f fhdl: encapsulate replicated constants 2011-12-23 00:35:13 +01:00
Sebastien Bourdeauducq f0aac4b50f flow: actor class 2011-12-22 19:37:16 +01:00
Sebastien Bourdeauducq 566295dea3 csr: use optree 2011-12-22 19:36:56 +01:00
Sebastien Bourdeauducq ba40f58491 corelogic: operator tree 2011-12-22 15:46:19 +01:00
Sebastien Bourdeauducq 8a394f9159 verilog: comb reset 2011-12-22 00:04:53 +01:00
Sebastien Bourdeauducq 4d6be55e9f verilog: break down Convert function 2011-12-21 23:08:50 +01:00
Sebastien Bourdeauducq 26e0b817e8 verilog: ignore variable property in combinatorial block 2011-12-21 23:00:36 +01:00
Sebastien Bourdeauducq 7456195775 Consistent names 2011-12-21 22:57:07 +01:00
Sebastien Bourdeauducq 94c5fba067 corelogic: fix signal exports 2011-12-18 21:54:28 +01:00
Sebastien Bourdeauducq 4f4d809a4e fhdl: better matching of assignment 2011-12-18 21:49:48 +01:00
Sebastien Bourdeauducq 107f03fd4b Remove uses of declare_signal 2011-12-18 21:47:48 +01:00
Sebastien Bourdeauducq dd42b2daff fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal 2011-12-18 21:47:29 +01:00
Sebastien Bourdeauducq 41e2430e2b fhdl: automatic signal name from assignment 2011-12-18 21:26:51 +01:00
Sebastien Bourdeauducq 135a2eb868 bank: support raw registers 2011-12-18 00:28:04 +01:00
Sebastien Bourdeauducq d21e095397 fhdl: fix series of if/elif/else 2011-12-17 20:31:42 +01:00
Sebastien Bourdeauducq 1a845d4553 32-device, 8-bit CSR bus 2011-12-17 15:54:49 +01:00
Sebastien Bourdeauducq 6f8a6db40a verilog: get the simulator to run the combinatorial process at the beginning 2011-12-17 15:20:22 +01:00
Sebastien Bourdeauducq ec47394012 verilog: support for float parameters in instances 2011-12-17 14:59:27 +01:00
Sebastien Bourdeauducq ee6ca729a2 verilog: user-definable reset and clock 2011-12-16 22:25:05 +01:00
Sebastien Bourdeauducq c7b9dfc203 fhdl: simpler syntax 2011-12-16 21:30:14 +01:00
Sebastien Bourdeauducq 39b7190334 Pay a bit more attention to PEP8 2011-12-16 16:02:55 +01:00
Sebastien Bourdeauducq 929cc98070 wishbone2csr: wait for WB deack 2011-12-13 17:38:59 +01:00
Sebastien Bourdeauducq 22d03b4943 timeline: only trigger in rest state 2011-12-13 15:25:46 +01:00
Sebastien Bourdeauducq c840848dba verilog: use blocking assignment in combinatorial process 2011-12-13 14:09:12 +01:00
Sebastien Bourdeauducq 92f24b784d wishbone: decoder: fix slave cyc generation in registered mode 2011-12-13 14:08:39 +01:00
Sebastien Bourdeauducq 0ea7a9b2e6 wishbone2csr: fix double-write bug 2011-12-13 00:25:46 +01:00
Sebastien Bourdeauducq 923fc52e68 wishbone: only send ack to the active master in arbiter 2011-12-13 00:25:25 +01:00
Sebastien Bourdeauducq a72faaecdd fhdl: allow a namespace to be specified for Verilog conversion 2011-12-13 00:24:40 +01:00
Sebastien Bourdeauducq eee6980a36 fhdl: support Constant parameters for Verilog conversion 2011-12-11 20:17:51 +01:00
Sebastien Bourdeauducq dafef5d744 fhdl: fix list references (thanks Lars) 2011-12-11 20:17:29 +01:00
Sebastien Bourdeauducq 16a6029a1b bus: fix CSR interconnect data readback 2011-12-11 20:17:12 +01:00
Sebastien Bourdeauducq dad9120653 bus: 14-bit CSR addresses 2011-12-11 20:16:50 +01:00
Sebastien Bourdeauducq 7582b76406 bank: fix csrgen address decoder 2011-12-11 20:15:30 +01:00
Sebastien Bourdeauducq 05d91c7104 bus: Wishbone to CSR bridge 2011-12-11 15:04:34 +01:00
Sebastien Bourdeauducq af74a89b8a corelogic: timeline module 2011-12-11 01:11:13 +01:00
Sebastien Bourdeauducq 019ef16db4 fhdl: remove broken fragment iadd 2011-12-11 01:10:59 +01:00
Sebastien Bourdeauducq b00581616e convtools: insert reset on variables 2011-12-11 01:10:37 +01:00
Sebastien Bourdeauducq d3127fd5d8 autofragment: remove debug 2011-12-10 20:48:23 +01:00
Sebastien Bourdeauducq 44f44b8a05 fhdl: autofragment 2011-12-10 20:47:21 +01:00
Sebastien Bourdeauducq 4b15a84505 fhdl: fix += for empty fragment 2011-12-10 20:47:06 +01:00
Sebastien Bourdeauducq a49ecc4331 fhdl: pad support in fragments 2011-12-10 20:25:24 +01:00
Sebastien Bourdeauducq 4d1a960308 wishbone: decoder + shared bus interconnect 2011-12-09 13:11:52 +01:00
Sebastien Bourdeauducq fa63cc1ec8 fhdl: replication support 2011-12-09 13:11:34 +01:00
Sebastien Bourdeauducq 5c7131dc86 wishbone: arbiter 2011-12-08 23:21:25 +01:00
Sebastien Bourdeauducq c1041b9a5f simplebus: export GetSigName function 2011-12-08 23:06:04 +01:00
Sebastien Bourdeauducq b2bc5ad4f4 corelogic: multimux module 2011-12-08 23:04:34 +01:00
Sebastien Bourdeauducq b0c5b74c22 verilog: handle default in case statements 2011-12-08 23:04:20 +01:00
Sebastien Bourdeauducq 512655c108 fhdl: improve automatic signal naming 2011-12-08 21:28:20 +01:00
Sebastien Bourdeauducq 5034af3038 Corelogic conversion example 2011-12-08 21:25:05 +01:00
Sebastien Bourdeauducq 62f70a54f0 corelogic: MC divider module 2011-12-08 21:19:40 +01:00
Sebastien Bourdeauducq 84eb964adc fhdl: support negation operator 2011-12-08 21:15:44 +01:00
Sebastien Bourdeauducq bf021efa2b verilog: fix unary operator conversion 2011-12-08 21:15:24 +01:00
Sebastien Bourdeauducq 78f18ad593 corelogic: round-robin module 2011-12-08 21:15:02 +01:00
Sebastien Bourdeauducq 7c99e51b90 Named buses 2011-12-08 19:16:08 +01:00
Sebastien Bourdeauducq 5720a51dad wishbone: add missing SEL 2011-12-08 19:09:32 +01:00
Sebastien Bourdeauducq ed05ec5f6a instances: signal override 2011-12-08 18:56:14 +01:00
Sebastien Bourdeauducq c43f3da534 Wishbone declarations 2011-12-08 18:47:41 +01:00
Sebastien Bourdeauducq a6b86168ce Simple bus base class 2011-12-08 18:47:32 +01:00
Sebastien Bourdeauducq 1b637cea61 Instance support 2011-12-08 16:35:32 +01:00
Sebastien Bourdeauducq fab02f84cb fhdl: fix implicit slice index 2011-12-07 22:21:30 +01:00
Sebastien Bourdeauducq 82f77180d5 fhdl: cleanup value bv 2011-12-07 22:21:10 +01:00
Sebastien Bourdeauducq 0e8d894a35 Variable conversion 2011-12-05 22:00:06 +01:00
Sebastien Bourdeauducq 4340680704 Cleanup 2011-12-05 19:25:32 +01:00
Sebastien Bourdeauducq ec51f09c98 Case support + register bank generator 2011-12-05 17:43:56 +01:00
Sebastien Bourdeauducq 458cfc8623 CSR bus definitions 2011-12-05 00:16:44 +01:00
Sebastien Bourdeauducq e099f4d52f Reset insertion 2011-12-04 22:41:50 +01:00
Sebastien Bourdeauducq cd8544c758 Verilog generator 2011-12-04 22:26:32 +01:00
Sebastien Bourdeauducq 499b95a519 Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00