58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
a8c92cd86f
targets/simple: Switch back to old version for now.
2022-11-08 11:55:06 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
f1e24046fd
xilinx_alveo_u250: Fix.
2022-11-06 22:17:28 +01:00
9a2028a9ba
targets: Remove useless argparse imports.
2022-11-06 22:09:21 +01:00
30723b1bb0
targets: Update targets that were still using argparse.ArgumentParser.
2022-11-06 22:07:17 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
d7184fb043
stlv7325, a_e115fb: use the proper vendor name Sitlinv
...
The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.
Use this vendor name instead of where it's bought.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-30 10:51:13 +08:00
4dc8f7223c
Merge pull request #443 from trabucayre/arty_z7_bios
...
targets/digilent_arty_z7: adding software support
2022-10-28 10:42:35 +02:00
3e809c3a1e
targets: Fix some LiteXModule imports.
2022-10-28 10:35:57 +02:00
ab3ed624cc
fpgawars_alhambra2: +x.
2022-10-28 10:31:49 +02:00
5f1b80fac4
targets/digilent_arty_z7: adding software support
2022-10-27 21:47:32 +02:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
f9d3a39001
chore fix target, args processing
2022-10-26 20:45:53 +02:00
189ee3de39
fix target
2022-10-26 20:36:18 +02:00
54af30a4be
fix: arg cpu-variant
2022-10-26 20:23:14 +02:00
32be05cfb1
chore default CPU variant
2022-10-25 21:14:25 +02:00
125569b2cb
add FPGAWars Alhambra II
2022-10-25 21:12:02 +02:00
bd2f1c2553
targets/isx_im1283: Fix CI.
2022-10-22 16:23:50 +02:00
8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region
...
targets/redpitaya: fix csr & reset region
2022-10-22 16:00:22 +02:00
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283
...
Add ISX iM1283 board
2022-10-22 15:56:43 +02:00
5a8d846a86
targets: Remove add_csr calls (no longer required).
2022-10-21 08:42:24 +02:00
4a5d5318d7
targets/redpitaya: fix csr & reset region
2022-10-20 16:35:57 +02:00
745ebbbfa1
Add ISX iM1283 board
...
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.
This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-14 22:50:43 +08:00
e44e63f65d
targets/digilent_arty_z7: add flash region
2022-10-13 19:48:41 +02:00
3ec18c3583
Add qmtech Cyclone IV Starter Kit
2022-10-09 16:34:44 +02:00
e6762e228c
targets/mnt_rkx7: Make USB-Host optional and disable by default (for CI).
2022-10-04 09:45:51 +02:00
d0dd009329
targets/mnt_rkx7: Integrate specific eDP video timings in target (Avoid LiteX patch).
2022-10-04 09:29:59 +02:00
c38b8b1d8c
MNT RKX7: update platform and target for D-2 release
2022-10-03 20:09:48 +02:00
85ba931a3d
targets/litex_acorn_baseboard: fix pn_swap
2022-09-28 21:17:16 +02:00
9cd1c1cbd5
targets/digilent_arty: Switch with_buttons to False by default (To fix #426 ).
2022-09-23 10:07:17 +02:00
9dbee62eac
add option to use ecpprog for crosslink-nx eval board
2022-09-15 12:27:08 -07:00
f1899954e9
Add initial NewAE CW305 board support.
2022-09-13 12:38:30 +02:00
25c28d2c03
fixed issue with default programmer option
2022-09-10 18:16:04 +01:00
6768be7f66
changed use example comment
2022-09-10 17:56:02 +01:00
6d0a4c788e
Added DFU support to Butterstick
2022-09-10 17:45:57 +01:00
756e4f73fc
sipeed_tang_primer_20k: Cleanup CRG.
2022-09-08 17:27:41 +02:00
fadc5619f1
sipeed_tang_primer_20k/ddr3: Add litescope debug.
2022-09-07 17:46:46 +02:00
6c7157f799
sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status.
2022-09-07 17:07:07 +02:00
d39d87b701
sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules.
2022-09-07 12:06:22 +02:00
1663ded641
sipeed_tang_primer_20k: Add initial DDR3 integration (WIP).
2022-09-07 11:53:24 +02:00
c9b8579ea3
sipeed_tang_primer_20k: Drive hdmi hdp to 1.
2022-09-07 11:22:02 +02:00
abd20f560b
sipeed_tang_primer: Minor cleanups (Rename standard dock to standard, reduce margin on hdmi5x).
2022-09-07 10:56:17 +02:00
1d92443604
targets/sipeed_tang_nano_9k: replace VideoHDMIPHY by VideoGowinHDMIPHY
2022-09-06 20:22:32 +02:00
0f242629ab
targets/sipeed_tang_nano_4k: replacing VideoHDMIPHY by VideoGowinHDMIPHY and adding with-video-terminal arg
2022-09-06 19:08:01 +02:00
ce5977bc1a
targets/sipeed_tang_primer_20k: fix CLKDIV (disable reset and calibration)
2022-08-31 13:32:23 +02:00
0c14bbf0dc
sipeed_tang_primer_20k: adding dock lite support
2022-08-26 08:43:57 +02:00
feff243f8f
Merge pull request #416 from shenki/artix-dc-scm
...
Add Antmicro Artix DC-SCM board
2022-08-24 15:22:52 +02:00
6314b34dbe
targets/digilent_arty: Cosmetic cleanup.
2022-08-24 15:17:06 +02:00
f48ed3d9e7
Add Antmicro Artix DC-SCM board
...
Based on commits by:
- Jedrzej Boczar <jboczar@antmicro.com>
- Karol Gugala <kgugala@antmicro.com>
Tested serial and networking on a DC-SCM with mor1k and vexriscv.
2022-08-24 13:03:36 +10:00
94ad22aceb
digilent_arty: make GPIOs interrupt-capable if SoC has IRQs enabled
...
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2022-08-17 15:55:39 +02:00
bf458e388e
digilent_arty: Add buttons support.
2022-08-05 15:25:42 +02:00
f143fae2d0
digilent_arty: Add XADC/DNA and do minor cleanups.
2022-08-05 13:00:07 +02:00
f2cb211432
sipeed_tang_primer_20k: Add buttons and prepare RGB Led.
...
Synthesis issue with WS2812/GowinEDA for now.
2022-08-04 16:32:50 +02:00
09b0c975f3
sipeed_tang_primer_20k: Add Ethernet/Etherbone (compiles but not yet working).
2022-07-26 12:53:42 +02:00
abe08a96aa
sipeed_tang_primer_20k: Add Video (Colorbars), compiles but does not seems to be working.
2022-07-26 12:25:10 +02:00
12b8063941
sipeed_tang_primer_20k: Add LedChaser through 204 pin SODIMM connector/Dock.
2022-07-26 11:44:03 +02:00
99c1e52664
targets/sipeed_tang_primier_20k: Add SPI Flash support (X1).
2022-07-26 10:35:44 +02:00
6677c1d0bd
sipeed_tang_primer_20k: Enable SDCard (SPI and SD modes).
2022-07-26 10:27:19 +02:00
cf030402d4
machdyne_krote: Fix build.
2022-07-19 12:17:14 +02:00
67ffe095cc
Merge branch 'master' of https://github.com/machdyne/litex-boards
2022-07-15 17:13:22 +02:00
22dcadcfa1
rename ld board prefix to machdyne
2022-07-15 17:13:00 +02:00
9deef65445
Merge branch 'litex-hub:master' into master
2022-07-14 16:02:00 +02:00
8e577662bd
Merge pull request #408 from trabucayre/lattice_nexus_ecp5_toolchain
...
targets: ecp5 & nexus: add toolchain argument
2022-07-11 19:33:54 +02:00
3ecec8cd16
Merge branch 'litex-hub:master' into master
2022-07-08 16:59:55 +02:00
756d019571
add support for schoko
2022-07-08 16:58:55 +02:00
4b678da142
ti60_f225_dev_kit: Add debug on ethernet.
2022-07-08 12:17:41 +02:00
3f4676c288
targets: ecp5 & nexus: add toolchain argument
2022-07-05 21:36:02 +02:00
bc66e63bad
lambdaconcept_ecpix5/flash: Switch to .svf.
2022-07-05 18:03:06 +02:00
32f507cc08
Merge pull request #406 from chmousset/fix/icebreaker_bitsy
...
[fix] instanciate PLL for valentyUSB
2022-06-29 10:31:42 +02:00
190f272c14
targets/sipeed_tang_primer_20k: Update build.
2022-06-29 10:00:47 +02:00
b61c471058
targets/avnect_aesku040: Update build.
2022-06-29 09:41:18 +02:00
d3597dea21
[fix] instanciate PLL for valentyUSB
2022-06-28 21:17:02 +02:00
6b02ea024a
ti60_f225_dev_kit: Fix ethernet build and enable debug. Now needs testing.
2022-06-28 19:54:00 +02:00
1a71932599
ti60_f225_dev_kit: Switch to Titanium RGMII PHY.
2022-06-27 19:47:22 +02:00
46ddc36b3c
target: basys3: Remove redundand sdcard additions
2022-06-27 14:34:49 +02:00
eadea43fa1
honours lattice toolchain args
2022-06-22 21:05:35 +02:00
29b72fac7e
taobao_a_e115fb: Minor cleanups.
2022-06-15 11:55:22 +02:00
0ae1417eb5
a_e115fb: Add taobao prefix (Similar to what we do on aliexpress's boards from unknown vendors).
2022-06-15 11:53:11 +02:00
4e0e381f47
Merge pull request #398 from Icenowy/a-e115fb
...
a_e115fb: new board
2022-06-15 11:37:36 +02:00
13fbcbb159
a_e115fb: new board
...
It's a core board with EP4CE115 by a random vendor on Taobao.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-13 23:13:29 +08:00
e02bee4265
efinix_ti60_f225: Prepare 1Gbps Ethernet support through RGMII extension board.
2022-06-13 16:02:26 +02:00
b32969c29f
targets/Ultrascale(+): Remove BUFGCE name overrides.
...
Not required, was only useful on a specific project.
2022-06-10 19:21:04 +02:00
4a22f6bf17
targets/avnet_aesku40: Fix compilation and minor cleanups.
2022-06-07 13:08:02 +02:00
d37af4aece
Merge pull request #395 from AEW2015/master
...
Support for "discontinued" Avnet aes-ku040-db-g development board
2022-06-07 12:13:47 +02:00
313e758ffe
Updated copywrite and renamed to avnet_aesku40
2022-06-03 20:49:52 -06:00
5188b17a71
sipeed_tang_nano_9k: Switch to old HyperRAM core until issue with new one is investigated. Also do some cleanup and disable video_terminal by default.
2022-06-03 12:28:38 +02:00
ddc6140e25
sipeed_tang_primer_20k: Swithc to GW2APLL.
2022-06-03 12:01:49 +02:00
6e33d9249f
sipeed_tang_primer_20k: Cleanup/Fix.
2022-06-03 11:40:10 +02:00
68733c6e92
Merge pull request #396 from Icenowy/tang20k
...
sipeed_tang_primer_20k: new board
2022-06-03 10:14:55 +02:00
b97d9cd9e8
sipeed_tang_primer_20k: new board
...
Only initial support is added.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-03 00:24:20 +08:00
4d98dd38a7
Merge branch 'litex-hub:master' into master
2022-06-01 23:01:43 -06:00
1b96067113
added aesku40 dev board
2022-06-01 22:54:03 -06:00
48353735fa
Merge pull request #393 from swetland/ethernet
...
muselab icesugar pro: add ethernet/etherbone support
2022-05-20 22:10:02 +02:00
5a714167ed
muselab icesugar pro: add ethernet/etherbone support
...
- use P4 header for a waveshare ethernet phy module
- add --with-ethernet, --with-etherbone, --eth-ip, and --eth-dynamic-ip
target configuration options
2022-05-19 14:46:09 -07:00
64773b4085
Merge pull request #390 from hansfbaier/hpc-xc7k420t
...
HPC Store xc7k420t
2022-05-16 11:20:15 +02:00
f14865fa42
Merge branch 'hpc-xc7k420t' of github.com:hansfbaier/litex-boards into hpc-xc7k420t
2022-05-16 12:34:30 +07:00
c5d292c7f9
Get 4 DDR modules working with Vivado
2022-05-16 12:33:04 +07:00
efa5740811
Move HDMI Support From Sipeed Tang Nano 4K.
2022-05-15 10:53:09 +08:00
26c0f546c7
Merge branch 'litex-hub:master' into hpc-xc7k420t
2022-05-14 21:40:12 +07:00
006b54e7ea
Get 3 DDR modules working with Vivado
2022-05-14 21:38:25 +07:00
1e77c28ed0
muselab_icesugar_pro/VideoHDMIPHY: Remove obsolete drive_both.
2022-05-12 16:09:40 +02:00
ee58e5dbc7
Merge pull request #388 from swetland/hdmi
...
muselab: icesugarpro: fix HDMI output
2022-05-12 15:09:03 +02:00
dabf2cff06
sqrl_acorn: Switch back to PCIe Gen2 X4 and enable 64-bit addressing (Not really useful except for 64-bit addressing tests).
2022-05-12 13:32:41 +02:00
f383ad3938
Support HPC Store XC7K420T board
2022-05-12 12:55:46 +07:00
d1096a2cd0
Add HPC Store XC7K420T board
2022-05-11 08:58:50 +07:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
0ce7f8354c
Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)).
...
python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 3 2022 18:59:46
BIOS CRC passed (5f29afcc)
LiteX git sha1: a4cc859d
--=============== SoC ==================--
CPU: VexRiscv @ 80MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
2022-05-03 19:04:06 +02:00
c93b4dc4dc
targets: Fix targets that not using full imports.
2022-05-03 18:41:18 +02:00
ec220e4b5b
muselab: icesugarpro: fix HDMI output
...
- enable data_n outputs
- use drive_both property of updated VideoHDMIPHY to drive both
differential outputs
- adjust default clocking to successfully close timing
(sysclk at 50Mhz, HDMI at 25MHz, HDMIx5 at 125MHz)
2022-05-03 04:04:26 -07:00
28da4f83eb
targets: Use new HyperRAM's sys_clk_freq parameter.
2022-05-02 16:43:52 +02:00
3ebc9877ad
1bitsquared_icebreaker: Rename to icebreaker (Python does not like number as prefix for imports).
2022-05-02 13:20:40 +02:00
877bc4b45e
targets: Use full imports (vendor_board).
2022-05-02 12:55:11 +02:00
9914478854
xilinx_ac701: Add SPI-Flash support.
2022-04-28 11:05:51 +02:00
ae8bdb74a9
xilinx_kc705: Add SPI-Flash support.
2022-04-28 10:27:54 +02:00
b778ba5f70
sqrl_acorn: Add XADC/DNA (For LitePCIe driver test).
2022-04-27 15:01:09 +02:00
74db821f67
colorlight_5a_75x: Switch ethernet/etherbone to 32-bit.
2022-04-25 18:50:21 +02:00
adb0922e8f
Delete additional "o" in "builder" object
...
Delete an additional "o" in "builder" object. It makes not possible to program the Basys 3 out-of-the-box.
2022-04-23 18:06:19 -06:00
575d681891
targets: Use "" for strings.
2022-04-21 15:48:29 +02:00
353aba0359
targets: Move USB-ACM/ValentyUSB clone directly to LiteX to avoid duplication in targets.
2022-04-21 15:43:50 +02:00
4fbf2fc7de
targets: Replace self.add_wb_master with self.bus.add_master.
2022-04-21 15:32:19 +02:00
39a314cdae
Rename aliexpress_u420t to aliexpress_xc7k420t.
2022-04-21 14:28:26 +02:00
88f2625c3d
targets: Fix typos.
2022-04-21 12:29:54 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
06396a2cb6
Merge pull request #384 from hansfbaier/qmtech-ep4cgx150
...
add board support for QMTech EP4CGX150
2022-04-21 10:36:51 +02:00
b2a346edc8
aliexpress_u420t: Review/Simplify.
...
Specific integrated ROM/SRAM/MAIN_RAM size can be passed through command line parameters.
2022-04-21 10:32:18 +02:00
3e9e970076
Add aliexpress prefix to boards from aliexpress that seem to be from the same unknown vendor.
2022-04-21 10:06:11 +02:00
8c51cb12c8
Merge pull request #383 from sysmanalex/master
...
Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
2022-04-21 10:02:05 +02:00
f986855926
Merge pull request #372 from mkj/butterstick-ethdelay
...
butterstick: set ethernet rx_delay to 0ns
2022-04-21 09:00:13 +02:00
53e9e0914e
qmtech_ep4cgx150 80MHz default works well
2022-04-16 15:00:01 +07:00
b41d72e1d0
add board support for QMTech EP4CGX150
2022-04-16 06:36:24 +07:00
23b1b15486
Add initial/minimal Pluto SDR support.
2022-04-14 12:13:03 +02:00
1e00a43fdd
board u420t kintex update v0.2
2022-04-13 00:12:59 +03:00
89570b005c
Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
2022-04-12 22:38:14 +03:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
...
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
867489d855
xilinx_zcu106: Add PCIe Gen3 X4 support.
2022-04-01 10:01:06 +02:00
13e5062793
Merge pull request #379 from chmousset/add_t8_devkit
...
[enh] added efinix t8f81 dev kit
2022-03-28 14:58:21 +02:00
e6a9f44580
Merge pull request #378 from antmicro/add-missing-peripherals
...
DDR4 datacenter: add missing peripherals
2022-03-28 14:40:22 +02:00
83d7c3fb39
Merge pull request #377 from Johnsel/arduino_mkrvidor4000
...
Board support for Arduino MKR Vidor 4000
2022-03-28 14:34:59 +02:00
7a68dcc79b
[enh] added efinix t8f81 dev kit
2022-03-26 09:52:20 +01:00
33516a40f4
antmicro_datacenter: add missing peripherals
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-25 13:49:41 +01:00
77cb866233
antmicro_datacenter: add HDMI output
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-25 10:03:07 +01:00
901942bda6
Cleanup for pushing. This commit combined with my litedram fork produces a running basic SoC + bios --=============== SoC ==================--
...
CPU:BUS:E 32-bit @ 4GiB
CSR:16-bit @ 48MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 21.3MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
2022-03-24 07:39:14 -07:00
c081177d77
pynq_z1/zybo_z7: Update .xci (With changes from #99 ).
2022-03-24 09:15:36 +01:00
bb974ae1af
decklink_quad_hdmi_recorder: Add pcie_lanes parameter and 4x/8x support.
2022-03-23 15:24:49 +01:00
ce4b627e3c
targets: Remove l2_size workaround (no longer required).
2022-03-22 19:13:23 +01:00
2a206def0f
targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less).
2022-03-22 17:32:35 +01:00
53c221a1fa
butterstick: set ethernet rx_delay to 0ns
...
The Microchip KSZ9031RNX PHY on the Butterstick has a default 1.2ns
internal RX delay so we shouldn't add the default 2ns MAC delay.
In testing with Linux on vexriscv I haven't seen any difference either
way, but with liteeth in Microwatt I have seen 30%+ packet loss when
receiving from certain ethernet devices (RTL8153 and AX88179 usb-gige
adapters, a GS105 switch didn't show the problem). Setting RX delay=0
resolves the problem. A TX delay is still required by the PHY.
2022-03-22 13:51:03 +08:00
b8b0aead28
Added basic support for Arduino MKR Vidor 4000
2022-03-21 18:54:29 -07:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
d90e260414
targets/digilent_atlys: Fix target.
2022-03-21 17:38:02 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
eb8657f515
gsd_orangecrab: Revert dm_remapping (Useful when built with VexRiscv-SMP and native LiteDRAM interface).
2022-03-18 12:56:13 +01:00
9faa805ab9
alinx_ax7010: Review/Cleanup.
2022-03-17 11:31:02 +01:00
3aa1042f5f
Merge pull request #367 from ggangliu/zynq_xc7z010
...
Add ALINX AX7010 board support
2022-03-17 09:52:04 +01:00
496b2cfab9
targets/gowin: Switch to get_bitstream_filename.
2022-03-17 09:40:10 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
94786cae19
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py
2022-03-17 11:24:24 +08:00
0745162a29
xilinx_zcu102: Review/Cleanup for consistency with others boards.
...
Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
2022-03-16 18:47:05 +01:00
adbcc2e547
add zcu102 target file
2022-03-16 15:55:37 +01:00
9dad1cb244
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py
2022-03-15 15:51:13 +08:00
9c55773275
Add files via upload
...
Add zynq_xc7z010 board support
2022-03-12 12:33:41 +08:00
9f9afeaafa
targets/nexys-video: Add support for sata pll refclk
2022-03-11 14:40:21 -05:00
3b74673a93
Merge pull request #363 from curliph/master
...
add Gowin programmer support
2022-03-08 17:26:50 +01:00
f52a915487
lambdaconcept_ecpix5: Add initial Video support at 640x480 (with Terminal/Framebuffer).
...
I2C intialization code adapted from https://github.com/ultraembedded/ecpix-5 .
Tested with:
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-terminal --build --load
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-framebuffer --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 8 2022 15:34:22
BIOS CRC passed (c7fe9ecd)
Migen git sha1: ac70301
LiteX git sha1: 7ebc7625
--=============== SoC ==================--
CPU: FireV-STANDARD @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 23.4MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on ECPIX-5 2022-03-08 15:34:19
2022-03-08 15:40:52 +01:00
39e4e211bb
targets/decklink_mini_4k: Add build/use instructions.
2022-03-08 14:14:18 +01:00
2df7fd573c
Update sipeed_tang_nano_9k.py
...
Add Gowin programmer support
2022-03-08 14:04:28 +08:00
4c9bc53a3c
add Win/powershell and WSL support
2022-03-08 13:24:56 +08:00
ec28ca8fa3
adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
...
This is a carrier board with a SoM mounted on it.
There is also an FMC connector that can accept another
AD-FMCOMMS8-EBZ to get two more ADRV9009 RFIC but support for
that is not added yet.
Note that the PCIe support requires :
- Change the .xci in the litepcie to use the right Quad
- Revert litex 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f so the
timing constrainst of litepcie apply correctly
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-03 22:17:09 +01:00
0f2e13fdf7
sqrl_fk33: Add HBM2 support (from https://github.com/enjoy-digital/fk33_hbm2_test ).
2022-03-03 17:34:48 +01:00
99a66274c8
xilinx_alveo_u280: Switch HBM2 to USPHBM2 now integrated in LiteX.
2022-03-03 16:11:48 +01:00
b80c7a7843
targets/sqrl_acorn: write_latency_calibration now disabled by default, no longer required.
2022-03-03 15:50:53 +01:00
db2d83ea29
antmicro_datacenter: use 100 MHz and add i2c master
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-01 13:00:36 +01:00
0b80890119
antmicro_datacenter: add 1 cycle of latency for RCD IC
2022-03-01 12:43:08 +01:00
9976b47f72
antmicro_datacenter: generate outputs for rowhammer-tester
2022-03-01 12:43:08 +01:00
5359fc5bfc
antmicro_datacenter: use A7DDRPHY
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2022-03-01 12:43:08 +01:00
2c4d31066f
digilent_arty_z7: Defaults to no_uart.
2022-03-01 11:15:30 +01:00
673676e3cb
digilent_arty_a7: Switch to VivadoProgrammer.
2022-03-01 10:48:22 +01:00
1320f3bd23
Merge pull request #357 from DaveBerkeley/colorlight_i9
...
Add ColorLight i9 v7.2
2022-03-01 10:07:55 +01:00
a19c03fa55
targets: Switch to generic/portable HyperRAM core from LiteX.
2022-03-01 09:10:19 +01:00
c9d009c735
Add ColorLight i9 v7.2
2022-02-28 14:08:49 +00:00
2311db18f8
add initial support for kröte fpga board
2022-02-25 14:22:19 +01:00
1623ba5942
targets/stlv7325: Reduce sys_clk_freq to 100MHz.
...
See https://github.com/enjoy-digital/litedram/issues/285 .
2022-02-25 09:04:07 +01:00
872113e1cc
stlv7325: Add SDCard support.
2022-02-24 18:02:43 +01:00
a08f346d90
stlv7325: Add Etherbone support (untested).
2022-02-24 17:43:53 +01:00
b1550f006a
stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer.
2022-02-24 17:17:08 +01:00
174d958ca7
Initial support for STLV7325 Kintex-7 board.
2022-02-23 18:28:55 +01:00
6661947d96
Merge pull request #354 from madscientist159/master
...
Add initial support for RCS Arctic Tern boards
2022-02-23 18:06:08 +01:00
1717af68ac
targets/sqrl_acorn/ddr3: Disable write_latency_calibration.
...
Introduce some memtest failures on some boards.
2022-02-23 10:38:43 +01:00
ae4b3c0938
Add initial support for RCS Arctic Tern boards
2022-02-21 20:04:51 -06:00
85397818d9
add Xilinx ZCU216 support
2022-02-21 19:14:13 +01:00
7d84e6e863
efinix_titanium_ti60_t225: Add SPI/Native SDCard support.
...
Both modes working with 8559b88ad8
2022-02-21 10:35:06 +01:00
df36cdbcc9
siglent_sds1104xe: Switch back to native DRAM width (now possible with Nax).
2022-02-18 11:47:08 +01:00
d85f88f42a
siglent_sds1104xe: Reduce DRAM's width to 16-bit for now (to use NaxRiscv).
2022-02-16 17:59:40 +01:00
08a79fa3ac
lattice_ecp5_vip: Minor cleanups, fix CI.
2022-02-15 10:58:38 +01:00
30afe26669
Merge pull request #348 from hubmartin/ecp5-vip
...
Draft: Add Lattice ECP5 VIP board + HDMI output board support
2022-02-15 08:53:57 +01:00
896884dd21
Merge branch 'master' into axu2cga_software
2022-02-15 08:21:29 +01:00
Florent Kermarrec
Gwenhael Goavec-Merou
Icenowy Zheng
Chema
Franck Jullien
Lukas F. Hartmann
slagernate
Adam Zeloof
Joel Stanley
Leon Schuermann
inc
Machdyne
Charles-Henri Mousset
Robert Szczepanski
AEW2015
Brian Swetland
Hans Baier
minexo79
Jorge Castro-Godínez
Alex Petrov
Alex Petrov
Alessandro Comodi
John Simons
Matt Johnston
Yonggang Liu
Joseph Faye
Gabriel Somlo
curliph
Sylvain Munaut
Piotr Binkowski
Karol Gugala
Dave Berkeley
Andrew Gillham
Raptor Engineering Development Team
Ilia Sergachev