Joel Stanley
b57fc8702a
microwatt: Update IRQ signal in wrapper
2020-06-10 12:30:52 +09:30
Joel Stanley
68d2aa45fa
microwatt: Add icache flush
2020-06-10 12:30:49 +09:30
Joel Stanley
e6909e2978
microwatt: Implement boot helper
2020-06-10 11:23:22 +09:30
Gabriel Somlo
5575a921d0
liblitesdcard: maintain unix newline convention across all source files
2020-06-09 14:09:35 -04:00
Florent Kermarrec
fe9b42facf
bios/boot: use progress bar in copy_image_from_sdcard_to_ram.
2020-06-09 20:00:32 +02:00
Florent Kermarrec
21b9239dc0
libbase: add progress bar (from Barebox).
2020-06-09 20:00:05 +02:00
Florent Kermarrec
32ebbc7761
software/liblitesdcard: add retries when setting card to Idle.
2020-06-09 19:59:38 +02:00
Florent Kermarrec
04d0ba6187
software/liblitesdcard/sdcard: add FatFs disk functions.
2020-06-09 17:58:43 +02:00
Florent Kermarrec
e27ed657e9
software/liblitesdcard/spisdcard: rename #defines and allow external definition.
2020-06-09 13:50:28 +02:00
Florent Kermarrec
a9e8860e49
software/liblitesdcard: create fat directory for FatFs files.
2020-06-09 13:44:26 +02:00
Florent Kermarrec
f1aba7e45c
sofware/liblitesdcard: enable Long Filename (LFN).
2020-06-09 13:35:14 +02:00
Florent Kermarrec
fb282d1a72
software/libsdcard: rewrite/simplify SPISDCard/FatFs support and only keep SDCard ver2.00+ compatibility.
2020-06-09 12:50:56 +02:00
Gabriel Somlo
78e3f25157
liblitesdcard: convert all sources to unix style newlines (cosmetic)
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-06-06 13:24:29 -04:00
Florent Kermarrec
c1806eba11
software/liblitesdcard: remove unsused functions with FF_FS_READONLY.
2020-06-05 23:25:54 +02:00
Florent Kermarrec
f9b43c81cc
software/liblitesdcard: switch to FatFs for sdcardboot.
2020-06-05 21:20:19 +02:00
Florent Kermarrec
f972c8e45e
software/liblitesdcard: base it on FatFs generic example code + LiteX's SPIMaster specific functions.
2020-06-05 16:27:38 +02:00
Florent Kermarrec
5b908983a2
software/liblitesdcard: add FatFs files.
...
To avoid maintaining our own code and support all Fat filesystems, let's just use FatFs library.
2020-06-05 16:26:58 +02:00
Florent Kermarrec
7d141258be
software/liblitesdcard/spisdcard: simplify/rewrite for consistency with the others parts of the project.
...
- Improve code readability, remove un-needed or duplicate comments.
- Only use a spi_xfer function for both write/read.
- Set the SDCard to low clk freq before init and increase it when initialized.
2020-06-05 12:46:23 +02:00
Florent Kermarrec
860ac1e212
software/liblitesdcard: add copyrights to spisdcard/fat16.
2020-06-04 12:14:54 +02:00
Florent Kermarrec
0ec50881f0
software/liblitesdcard/sdcard: simplify readSector.
2020-06-04 11:55:25 +02:00
Florent Kermarrec
8c6f74d483
software/liblitesdcard: fat16 boot working with both SPI and SD modes.
2020-06-04 11:40:42 +02:00
Florent Kermarrec
bdaf6ff2dd
software/liblitesdcard: move fat16 code to separate file to avoid duplication.
2020-06-03 23:16:13 +02:00
Florent Kermarrec
4b3c5203ed
software/bios/libsdcard: add initial boot from sdcard with litescard, rename spisdcardboot command to sdcardboot.
2020-06-03 20:03:18 +02:00
Florent Kermarrec
b30e3353b5
soc/add_sdcard: use SDClockerS7 for 7-Series and SDClockerGen for others devices.
2020-06-03 18:37:08 +02:00
Jan Kowalewski
eceee7e4c4
litex/soc/software/liblitespi: fix names associated with PHY CSRs
2020-06-03 15:37:06 +02:00
Florent Kermarrec
997a17b933
soc/add_sdcard: add minimal SDClockerECP5 on ECP5.
2020-06-03 14:34:59 +02:00
Florent Kermarrec
9a026c09f9
soc/add_sdcard: remove limitation to 7-Series but only add clocker for it.
2020-06-03 13:47:39 +02:00
Florent Kermarrec
c311f98cfa
soc/add_sdcard: emulator clocking moved to litesdcard.
2020-06-03 13:43:44 +02:00
Florent Kermarrec
382f239e74
software/libsdcard: keep SDCARD_DEBUG enabled for now, fix typos.
2020-06-03 13:38:34 +02:00
Florent Kermarrec
20bbdaaf6b
soc/add_sdcard: remove Timer (unused).
2020-06-03 13:13:07 +02:00
Florent Kermarrec
ab447df922
software/liblitesdcard: review/simplify (code is over-complicated, revert part of the old code and write a minimal test for now).
2020-06-03 13:12:45 +02:00
Florent Kermarrec
ee4056cfec
software/liblitesdcard: remove sdtimer functions (unused).
...
sdtimer was used to evaluate performance but is no longer used.
2020-06-03 11:11:45 +02:00
Florent Kermarrec
55723f138b
software/liblitedram: revert sdrsw() in sdrlevel: this is still required for sdrlevel command.
2020-06-02 16:14:53 +02:00
enjoy-digital
ddcf68c062
Merge pull request #553 from ozbenh/sim-autoinit
...
sdram: Unconditionally switch to SW control before inits
2020-06-02 15:49:00 +02:00
Mateusz Holenko
f1e7d73e48
bios: boot: Boot linux on mor1kx with external device tree and rootfs
2020-06-02 14:57:48 +02:00
Tim Ansell
77139289f8
Merge pull request #552 from ozbenh/memspeed-long
...
sdram: Use unsigned long for memory test
2020-06-01 15:23:03 -07:00
Benjamin Herrenschmidt
6239eac130
sdram: Use unsigned long for memory test
...
This makes it twice as fast on 64-bit CPUs when using a 64-bit bus :-)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-02 08:08:42 +10:00
enjoy-digital
a116578c82
Merge pull request #550 from antmicro/jboc/spd-read
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bios/litedram: Add command to verify SPD contents with the one used during generation
2020-06-01 21:17:40 +02:00
Benjamin Herrenschmidt
4a6256a50d
sdram: Unconditionally switch to SW control before inits
...
This will allow the controller to default to HW control which means
the sim model can be used without specific initializations
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-01 23:44:09 +10:00
enjoy-digital
5cc7a98845
Merge pull request #547 from gsomlo/gls-fix-sdcard-status
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soc/software/litesdcard: update for response register back to 128 bits
2020-06-01 11:37:05 +02:00
Florent Kermarrec
395af900fd
interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify.
...
Improve efficiency for 64-bit CPU accessing only the 32-bit LSBs/MSBs.
2020-06-01 11:06:23 +02:00
Florent Kermarrec
511832a911
soc/interconnect/axi: generate wishbone.sel for reads.
2020-06-01 10:58:45 +02:00
Florent Kermarrec
4f82a36afd
soc/software: only keep 32-bit CSR alignment support.
...
64-bit support was added for 64-bit CPU because of limitation of the hardware
on CSR accesses. Now that the Wihhbone2CSR bus handles wishbone.sel, this is no
longer required.
2020-06-01 10:01:14 +02:00
Gabriel Somlo
28290efd00
soc/software/litesdcard: update for response register back to 128 bits
...
The additional (17th) byte returned via the response register was
ignored by software (bios and kernel), so LiteSDCard was updated
to only return the (original, useful) 128 bits.
This patch updates the LiteSDCard code in the LiteX bios to only
expect those 128 bits, and to do so in a manner that's portable
across CSR data widths and alignments.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-30 18:12:51 -04:00
Florent Kermarrec
759367752c
wishbone/wishbone2csr: use wishbone.sel on CSR write.
...
CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.
2020-05-30 15:22:02 +02:00
Florent Kermarrec
b1ec092e88
soc/software/litesdcard: use new send register to send command and remove CSR8_CMD_FIX.
2020-05-29 20:15:02 +02:00
Florent Kermarrec
55c7461e7b
bios/cmds/cmd_litesdcard: rewrite comments/descriptions.
2020-05-29 18:51:24 +02:00
Florent Kermarrec
6cb03963f3
bios/main: replace / with -.
2020-05-29 18:40:54 +02:00
enjoy-digital
5dd5f97b88
Merge pull request #545 from gsomlo/gls-fix-mmptr
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csr: fix simple accessor alignment
2020-05-29 18:32:30 +02:00
Gabriel Somlo
3e1b17d459
csr: fix simple accessor alignment
...
MMPTR should always follow CSR alignment, NOT CSR data width.
(the latter merely indicates how many bits within a MMPTR are
actually populated).
Fixup for commit #4a5072a.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-29 12:03:05 -04:00
Florent Kermarrec
6c1e2d8413
software/liblitesdcard: replace hexdump with dump_bytes already available in the BIOS.
2020-05-29 17:15:20 +02:00
Florent Kermarrec
9e068a7494
soc/add_sdcard: add with_emulator parameter to use SDCard emulator (from Google Project Vault) and integrate it in litex_sim.
2020-05-29 16:07:40 +02:00
Jędrzej Boczar
a433c837e0
bios/litedram: add option to verify SPD EEPROM memory contents
2020-05-29 15:14:54 +02:00
enjoy-digital
62d939e85f
Merge pull request #543 from antmicro/jboc/eeprom-sim
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litex/build/sim: add module for simulating SPD EEPROM
2020-05-28 16:46:34 +02:00
Florent Kermarrec
76cc112ecf
bios: add main bus and csr bus infos, use KiB/GiB.
2020-05-28 15:05:24 +02:00
Jędrzej Boczar
a0ce4ce56b
litex/build/sim: add module for simulating SPD EEPROM
2020-05-28 12:10:25 +02:00
Florent Kermarrec
02072deab1
integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically.
2020-05-27 23:47:07 +02:00
Florent Kermarrec
4b3afa75a7
integration/soc: add add_sdcard method with integration code from nexys4ddr.
...
Even if not cleaned up yet, having it there will avoid duplications in targets.
2020-05-27 23:18:15 +02:00
Benjamin Herrenschmidt
c78caeb998
csr: Fix definition(s) of CSR_BASE in generated headers
...
CSR_BASE is currently defined twice. Once in mem.h as the base
of the CSR region in the SoC address space, and once in csr.h
as the base address for all CSRs.
This fixes two issues with those definitions:
- The mem.h one is unconditional which prevents an external
redefinition (which is useful under some circumstances such as
when using an address decoder outside of LiteX with a standalone
core).
- The csr.h one is actually the origin of the first CSR region
rather than the origin of the CSR region in the SoC space. They
are usually the same ... unless you don't have CSR bank 0 in
which case the csr.h one becomes different. This causes conflicts
with the mem.h definition and breaks projects using a standalone
cores.
The first one is fixed by adding the #ifndef/#endif around the
definition of the memory regions, the second one by passing the
csr_base to use to get_csr_header()
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-27 21:48:00 +02:00
Benjamin Herrenschmidt
f8bb500a43
liblitedram/sdram: Add option to disable cdelay()
...
When running in sim, those delays can take a *long* time, which
isn't always necessary with the simulated litedram PHY.
This allows system.h to optionally set CONFIG_SIM_DISABLE_DELAYS
which causes cdelay to do nothing.
This is especially useful when using a verilated litedram inside
a bigger/slower simulated design as to not spend a huge amount
of time going through the initializations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-27 21:39:28 +02:00
Florent Kermarrec
6d72ef28a8
cpu/serv: add variants.
2020-05-27 20:00:10 +02:00
Florent Kermarrec
fd7ec50e43
soc/integration/export: add optional csr_base parameter.
2020-05-27 19:59:54 +02:00
enjoy-digital
25d2e7c92f
Merge pull request #542 from gsomlo/gls-sdcard-followup
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software/bios: fixup sdclk command
2020-05-27 19:04:18 +02:00
enjoy-digital
3fd6ecd86e
Merge pull request #541 from antmicro/jboc/spd-read
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Add support for I2C to read SPD EEPROM
2020-05-27 19:03:50 +02:00
Florent Kermarrec
ab80606036
soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.
2020-05-27 18:40:45 +02:00
Gabriel Somlo
6da98ca14d
software/bios: fixup sdclk command
2020-05-27 12:38:59 -04:00
Florent Kermarrec
0a3d649ad8
interconnect/wishbone: integrate Wishbone2CSR.
2020-05-27 18:15:05 +02:00
Florent Kermarrec
b5b88d27b5
interconnect/csr_bus: add separators.
2020-05-27 18:13:57 +02:00
Florent Kermarrec
86952a6e06
interconnect/wishbone: remove CSRBank (probably not used by anyone).
2020-05-27 18:04:08 +02:00
Florent Kermarrec
e404608cf4
interconnect/wishbone: add separators and move SDRAM/Cache.
2020-05-27 17:59:33 +02:00
Florent Kermarrec
1fddd0e3d3
interconnect/wishbone: simplify DownConverter.
2020-05-27 17:34:11 +02:00
Jędrzej Boczar
1172c10afb
bios: move I2C from liblitedram to libbase
2020-05-27 15:37:19 +02:00
Florent Kermarrec
e0d2682055
interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten).
...
We'll provide a better implementation if this is useful.
2020-05-27 15:27:33 +02:00
Jędrzej Boczar
472bf9ac71
bios/sdram: expose I2C functions
2020-05-27 11:56:59 +02:00
Florent Kermarrec
67cf67034c
cpus: remove common cpu variants/extensions definition and simplify variant check.
...
Having common cpu variants/extensions has no real additional value since we are supporting
very various CPUs where minimal/standard/full have different meanings. Checking against
common variants/extensions has also cause more issues recently when adding new CPUs than
the additional value it was supported to provide.
So let's just simplify things: a CPU provide the supported variants and we just check
against that.
2020-05-26 09:36:44 +02:00
Florent Kermarrec
062ff67e12
cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin.
2020-05-26 08:51:33 +02:00
Florent Kermarrec
78a9579e09
cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word.
2020-05-25 10:46:53 +02:00
enjoy-digital
370e46529d
Merge pull request #539 from dayjaby/pr-fix_uart_startbit
...
Fix UART startbit: 1 cycle later
2020-05-25 10:33:58 +02:00
David Jablonski
e853ad4b61
fix uart startbit: 1 cycle later
2020-05-24 16:12:07 +02:00
Florent Kermarrec
2fb52e66b1
integration/soc: remove TODO in header.
2020-05-23 18:54:04 +02:00
Florent Kermarrec
b65f18c357
cpu/cv32e40p: fix copyright year.
2020-05-23 18:53:03 +02:00
Florent Kermarrec
30f3517041
cpu/cv32e40p: add copyright and improve indentation.
2020-05-22 15:55:35 +02:00
enjoy-digital
4c4cd335de
Merge pull request #535 from antmicro/arty-cv32e40p
...
Add support for the CV32E40P RISC-V CPU
2020-05-22 13:44:10 +02:00
Mateusz Hołenko
9d16b0fc82
libbase: Include missing uart header
...
This fixes compilation on mor1kx.
2020-05-22 11:43:18 +02:00
Jędrzej Boczar
a42dc97401
bios/sdram: add BIOS command for reading SPD
2020-05-21 14:32:31 +02:00
Jędrzej Boczar
8fd3e74ec9
bios/sdram: add firmware for reading SPD EEPROM
2020-05-21 14:07:42 +02:00
Florent Kermarrec
a6cbbc9d69
integration/soc: set build_name to platform.name when not specified.
2020-05-21 09:05:45 +02:00
Florent Kermarrec
16417cb8f1
software/liblitespi: fix #endif location.
2020-05-20 23:20:45 +02:00
Pawel Sagan
ce49990084
Extend I2S capabilities
...
This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.
This required to rework the FSM.
2020-05-20 14:31:51 +02:00
Piotr Binkowski
2d6ee5aaf2
cores/cpu: add cv32e40p
2020-05-20 13:46:37 +02:00
Piotr Binkowski
ca8cb83424
software/bios/isr: add support for cv32e40p
2020-05-20 13:46:37 +02:00
Jan Kowalewski
ab41e27e4c
software/liblitespi/spiflash: fix dummy bits setup function name
2020-05-20 11:47:40 +02:00
Florent Kermarrec
80eca3000b
software/liblitespi/spiflash: review/simplify/update and test on arty.
2020-05-20 11:16:39 +02:00
Florent Kermarrec
e91c317139
software/bios: cleanup includes and specify the lib in the include.
...
This ease understanding from which lib the file is included and also allow
having simple filenames in the libs.
2020-05-20 09:55:19 +02:00
Florent Kermarrec
c3a03d0d99
software: create liblitespi and mode litespi code to it (with some parts commented out for now).
2020-05-20 09:32:45 +02:00
Jan Kowalewski
61238beeae
soc/software/bios: add autoconfiguration functionality for LiteSPI core
2020-05-20 09:16:07 +02:00
Gabriel Somlo
c5524dbf20
software/bios: fix link order to avoid undefined symbol errors
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-19 16:20:58 -04:00
Florent Kermarrec
de7e0ee9ff
integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed.
2020-05-19 16:01:57 +02:00
Florent Kermarrec
6f8f0d2346
litex_setup: add litehyperbus and remove hyperbus core/test.
2020-05-19 15:49:25 +02:00
Florent Kermarrec
109fd2674a
integration/builder: simplify default output_dir to "build/platform".
...
All SoC are now based on the same base class and naming was too complicated.
2020-05-19 13:59:56 +02:00
Florent Kermarrec
7192397ab4
software/libbase: remove linker-sdram (unused).
2020-05-18 23:35:48 +02:00
Florent Kermarrec
b4b84def3c
software/bios: mode spisdcard code to liblitesdcard.
2020-05-18 23:33:34 +02:00
Florent Kermarrec
21e2a34c3f
software/bios: rename commands to cmds and update with libs' names.
2020-05-18 23:26:51 +02:00
Florent Kermarrec
33f6ce7431
software/bios: move hw flags definitions to respective libs, remove hw/flags.h.
2020-05-18 23:09:31 +02:00
Florent Kermarrec
403355a8ed
software: create liblitescard and move sdcard init/test code to it.
2020-05-18 22:49:12 +02:00
Florent Kermarrec
920d0ee536
software: create liblitedram and move sdram init/test code to it.
2020-05-18 22:42:23 +02:00
Florent Kermarrec
c95084e5c6
bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash.
2020-05-18 22:24:24 +02:00
Florent Kermarrec
573a881529
software/bios/commands: rename cmd_mdio to cmd_liteeth.
2020-05-18 22:16:20 +02:00
Florent Kermarrec
ff8d9e61bf
software/bios: move mdio to libliteeth.
2020-05-18 21:09:41 +02:00
Florent Kermarrec
70a67ce7ed
software/bios: rename libnet to libliteeth and move all ethernet files to it.
2020-05-18 21:04:54 +02:00
Florent Kermarrec
56b8723b72
software/bios: rename cmd_mem_access to cmd_mem.
2020-05-18 19:59:28 +02:00
Florent Kermarrec
a02077d547
cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build.
2020-05-18 17:30:42 +02:00
Florent Kermarrec
b5352f403c
cpu/microwatt: update microwatt_wraper.vhdl
2020-05-18 16:38:08 +02:00
Florent Kermarrec
be25500e91
uptime: rework and integrate it in Timer to ease software support.
2020-05-17 11:05:14 +02:00
Florent Kermarrec
d6549ff8f1
bios: add uptime command and rewrite cmd_bios comments.
2020-05-16 10:02:31 +02:00
Florent Kermarrec
fc0e55be32
soc: improve uptime comments.
2020-05-16 10:01:39 +02:00
enjoy-digital
840679add6
Merge pull request #526 from rprinz08/master
...
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 16:03:37 +02:00
Florent Kermarrec
82364de57f
soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled.
2020-05-15 15:00:04 +02:00
rprinz08
3f649077b1
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 12:07:52 +02:00
Florent Kermarrec
3391398a5f
bios/sdram: always show bitslip on two digits to keep scan aligned.
2020-05-14 15:20:52 +02:00
Benjamin Herrenschmidt
1e35b0e705
csr: Rework accessors
...
Have all the new compound accessors be written in terms of the simple
ones and fix how CSR_ACCCESORS_DEFINED can be used to override the
simple ones but keep the definitions of the other ones around.
This *should* also also fix incorrect multiple accesses done
by 64-bit CPUs to 32-bit CSR busses, and make the accessors not
depend on CONFIG_CSR_ALIGNMENT being the same as sizeof(unsigned long)*8
In addition, the generated csr.h now will include system.h
always when with_access_functions is True. This guarantees that the
higher level accessors are defined. The extern prototypes for the
simple accessors when CSR_ACCCESORS_DEFINED are removed and system.h
is responsible for providing them. It is also added to hw/common.h
This allows system.h to set CSR_ACCCESORS_DEFINED when necessary, in
which case it's responsible for both declaring and defining the simple
accessors. That way, it can make them inline rather than forcing them
to be extern which at least on microwatt saves spaces.
One can continue to use -DCSR_ACCCESORS_DEFINED but in that case a system.h
will have to be provided with at least the extern definitions.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 21:38:19 +10:00
enjoy-digital
a51c7a7bac
Merge pull request #518 from enjoy-digital/csr_base
...
export: add define of CSR_BASE if not already defined and use it for …
2020-05-14 08:02:37 +02:00
Florent Kermarrec
51742be2bb
integration/soc: review/simplify interconnect and add logger.info.
2020-05-13 18:29:12 +02:00
Benjamin Herrenschmidt
1ed6869110
soc: Revive generation of a PointToPoint interconnect
...
When there's only one master, one slave, and that slave is at 0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 00:06:53 +10:00
Florent Kermarrec
748ef1add3
export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses.
...
This will allow more flexibility when integrating standalone cores.
2020-05-13 15:56:20 +02:00
Florent Kermarrec
9d1443c1a8
cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that.
2020-05-13 09:31:20 +02:00
Florent Kermarrec
5ea3bae036
bios/boot: review/fix #503 .
...
- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
2020-05-13 08:44:17 +02:00
enjoy-digital
bf7857f553
Merge pull request #503 from rprinz08/master
...
BIOS boot firmware from SPI with address offset
2020-05-13 08:36:43 +02:00
Dave Marples
d2d82dacf2
Bios linker edits to prevent inappropriate optimisation
2020-05-12 23:32:49 +01:00
rprinz08
1f55fcf449
fixed bug in BIOS spi flash "fw" command
2020-05-12 16:58:42 +02:00
rprinz08
f062c0c44b
removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram
2020-05-12 16:57:21 +02:00
Florent Kermarrec
3fb99b7d33
cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
2020-05-12 16:51:47 +02:00
enjoy-digital
2a5a7536b8
Merge pull request #478 from antmicro/extended_spi_flash
...
Extended SPI flash support
2020-05-12 16:42:01 +02:00
Florent Kermarrec
3a6dd95d6f
integration/soc: review/simplify changes for standalone cores.
...
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
2020-05-12 16:18:26 +02:00
enjoy-digital
0d5eb13359
Merge pull request #511 from ozbenh/standalone-cores
...
Improve standalone cores
2020-05-12 14:55:44 +02:00
Florent Kermarrec
873d95e517
interconnect/wishbonebridge: refresh/simplify.
...
This should also improve Wishbone timings.
Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash
With the following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))
errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))
# # #
wb.close()
2020-05-12 13:40:28 +02:00
Benjamin Herrenschmidt
f628ff6b47
WB2CSR: Use CSR address_width for the wishbone bus
...
Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:37:36 +10:00
Benjamin Herrenschmidt
520c17e96d
soc_core: Add option to override CSR base
...
When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.
However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.
This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:35:12 +10:00
Benjamin Herrenschmidt
ecbd40284a
soc: Don't update CSR alignment when there is no CPU
...
The alignment specified by the standalone core config should
be honored.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:31:23 +10:00
Benjamin Herrenschmidt
f28f247130
soc: Don't create a wishbone slave to LiteDRAM with no CPU
...
When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:30:19 +10:00
Benjamin Herrenschmidt
dcc881db92
soc: Don't create a share intercon with only one master and one slave
...
This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 20:58:19 +10:00
enjoy-digital
c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex
...
Update README and core.py for Blackparrot and change vivado command for systemverilog
2020-05-12 11:41:25 +02:00
Kamil Rakoczy
0db3506997
Update Litex bios to handle updated litesdcard.
2020-05-12 10:07:16 +02:00
sadullah
aed1d514ab
Update README.md and core.py for BlackParrot
2020-05-12 03:06:38 -04:00
sadullah
5e4a436089
Vivado Command Update for Systemverilog
...
Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
enjoy-digital
3ce9010083
Merge pull request #505 from DurandA/patch-3
...
Enable 1x mode on SPI flash
2020-05-11 22:53:31 +02:00
Florent Kermarrec
e2176cefc2
soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.
2020-05-11 22:39:17 +02:00
Arnaud Durand
2c40967b5a
Enable 1x mode on SPI flash
2020-05-11 22:12:40 +02:00
enjoy-digital
13db89ebd2
Merge branch 'master' into rdimm_bside_init
2020-05-11 09:42:35 +02:00
enjoy-digital
c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-11 08:58:20 +02:00
Florent Kermarrec
59d88a880c
integration/soc/add_adapter: rename is_master to direction.
2020-05-11 08:47:50 +02:00
Ilia Sergachev
e4fa4bbcf7
integration/soc: fix add_adapter for slaves
2020-05-10 11:32:34 +02:00
Benjamin Herrenschmidt
2d70220b80
bios: Fix warning on 64-bit
...
This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00
rprinz08
ea232fc53a
BIOS boot firmware from SPI with address offset
2020-05-09 19:20:32 +02:00
Florent Kermarrec
fbbbdf03b5
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
2020-05-08 22:13:47 +02:00
Florent Kermarrec
05869beb72
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
2020-05-08 13:18:12 +02:00
Florent Kermarrec
90c485fcc8
integration/soc: add clock_domain parameter to add_etherbone.
...
To allow using a sys_clk < 125MHz with a 1Gbps link.
2020-05-08 13:16:26 +02:00
Florent Kermarrec
f1a50a2138
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
2020-05-08 11:54:51 +02:00
Florent Kermarrec
79ee135f56
bios/sdram: fix lfsr typo.
2020-05-07 12:11:59 +02:00
Dave Marples
2a37b97d9f
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
2020-05-07 09:36:41 +01:00
Dave Marples
967e38bb57
Small fixups to address compiler warnings etc.
2020-05-07 09:26:46 +01:00
Florent Kermarrec
84841e1d58
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
2020-05-07 08:21:57 +02:00
Benjamin Herrenschmidt
99c5b0fca1
bios/sdram: Use an LFSR to speed up pseudo-random number generation
...
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:56:10 +02:00
Florent Kermarrec
95b57899cd
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
2020-05-05 16:27:21 +02:00
Florent Kermarrec
9bef218ad6
cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).
...
Tested on Arty A7:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 4 2020 17:15:13
BIOS CRC passed (0adc4193)
Migen git sha1: 5b5e4fd
LiteX git sha1: 6f24d46d
2020-05-04 17:30:50 +02:00
Gabriel Somlo
edfed4f068
software/*/Makefile: no need to copy .S files from CPU directory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-04 09:16:52 -04:00
shuffle2
ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL
...
FREQUENCY_PIN_CLKI should be given in mhz
2020-05-04 01:10:09 -07:00
Florent Kermarrec
2112703181
cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.
...
It seems to be what most distros cross-comiplers are using.
2020-05-04 08:51:38 +02:00
Florent Kermarrec
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
Florent Kermarrec
45377d9faa
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
2020-05-03 21:29:54 +02:00
Florent Kermarrec
7c69a6dbba
bios/cmd_mdio.c: fix missing <base/mdio.h> import.
2020-05-03 10:54:35 +02:00
Florent Kermarrec
b02053357c
cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
2020-05-02 20:07:52 +02:00
Florent Kermarrec
97e534d0b6
cpus: add nop instruction and use it to simplify the BIOS.
2020-05-02 12:52:25 +02:00
Florent Kermarrec
4efc783534
cpus: add human_name attribute and use it to simplify the BIOS.
2020-05-02 11:52:58 +02:00
Florent Kermarrec
d81f171c8a
software/libbase/system.c: remove unused includes.
2020-05-02 11:27:22 +02:00
enjoy-digital
999b93af0a
Merge branch 'master' into blackparrot_litex
2020-05-02 11:16:33 +02:00
enjoy-digital
705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl
...
Terminal: add history and auto completion
2020-05-02 10:45:12 +02:00
Sadullah Canakci
0c770e0683
Update README.md
2020-05-02 02:51:41 -04:00
sadullah
19bb1b9b8c
update to comply with python-data layout
2020-05-01 23:44:20 -04:00
sadullah
3eb9efd64f
BP fpga recent version
2020-05-01 16:27:30 -04:00
sadullah
bf864d335b
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
2020-05-01 16:27:27 -04:00
sadullah
cf01ea65f3
rebased, minor changes in core.py
2020-05-01 16:25:01 -04:00
sadullah
b7b9a1f0fb
Linux works, LiteDRAM works (need cleaning, temporary push)
2020-05-01 16:24:58 -04:00
Sadullah Canakci
74140587c8
Create GETTING STARTED
...
Rename GETTING STARTED to GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
2020-05-01 16:20:35 -04:00
enjoy-digital
a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters
...
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
2020-05-01 21:17:38 +02:00
Florent Kermarrec
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
Gabriel Somlo
c8e3bba4b7
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-01 09:49:16 -04:00
Florent Kermarrec
3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
Franck Jullien
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
Franck Jullien
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
Franck Jullien
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
Franck Jullien
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
Franck Jullien
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
Florent Kermarrec
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
Florent Kermarrec
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
Florent Kermarrec
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
...
As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
Florent Kermarrec
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
Florent Kermarrec
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
David Shah
64b505156e
Add RDIMM side-B inversion support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
Ilya Epifanov
83f4dcb2c6
Added imac config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
Jakub Cebulski
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
Florent Kermarrec
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
enjoy-digital
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
...
Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
Florent Kermarrec
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
...
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
Florent Kermarrec
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
enjoy-digital
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
Florent Kermarrec
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
enjoy-digital
c5ef9c7356
Merge pull request #473 from fjullien/memusage
...
bios: print memory usage
2020-04-27 18:24:43 +02:00
Franck Jullien
3892d7a90a
bios: print memory usage
...
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
enjoy-digital
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
...
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
Florent Kermarrec
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
Florent Kermarrec
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
Florent Kermarrec
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
Florent Kermarrec
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
Florent Kermarrec
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
Florent Kermarrec
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
Florent Kermarrec
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
...
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
Florent Kermarrec
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
...
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
enjoy-digital
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
...
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
Jakub Cebulski
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
Jędrzej Boczar
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
Florent Kermarrec
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
Florent Kermarrec
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
Florent Kermarrec
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
Florent Kermarrec
c0f3710d66
bios/sdram: update/simplify with new exported LiteDRAM parameters.
2020-04-16 10:42:01 +02:00
Florent Kermarrec
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
...
Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
Mateusz Holenko
77a05b78e8
soc_core: Fix region type generation
...
Include information about being a linker region.
2020-04-14 21:45:32 +02:00
Florent Kermarrec
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
Florent Kermarrec
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
...
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
Tim 'mithro' Ansell
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
83b2581331
Fix the libcompiler_rt path.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
1c1c5bcbda
Remove submodules.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
Florent Kermarrec
79913e8614
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:49:45 +02:00
David Sawatzke
d69b4443b3
Add riscv64-none-elf triple
2020-04-09 05:36:10 +02:00
Florent Kermarrec
14bf8b8190
soc/cores/clock: add Max10PLL.
2020-04-08 08:54:12 +02:00
Florent Kermarrec
2470ef5096
soc/cores/clock: add Cyclone10LPPLL.
2020-04-08 08:33:57 +02:00
Florent Kermarrec
f8d6d0fda8
soc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 08:25:46 +02:00
Florent Kermarrec
970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
Florent Kermarrec
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
Florent Kermarrec
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
Florent Kermarrec
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
Florent Kermarrec
a67ab41835
interconnect/csr: add reset_less parameter.
...
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
Florent Kermarrec
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
Florent Kermarrec
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
Florent Kermarrec
a35df4f7d1
stream: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
Florent Kermarrec
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
Florent Kermarrec
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
...
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
Florent Kermarrec
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
