Dolu1990
|
6598e82920
|
wishbone => word address, not byte address
|
2018-04-19 11:22:06 +02:00 |
|
Dolu1990
|
455607b6b4
|
Fix dBus IO access
|
2018-04-18 14:11:59 +02:00 |
|
Dolu1990
|
6e59ddcc73
|
Cached wishbone demo is passing regression tests
|
2018-04-18 13:51:33 +02:00 |
|
Dolu1990
|
b37fc3fcc8
|
Add VexRiscv Wishbone demo for sim (generation ok)
|
2018-04-18 12:54:20 +02:00 |
|
Dolu1990
|
a66efcb35b
|
Add wishbone support for i$ / d$ (not tested)
|
2018-04-17 23:56:44 +02:00 |
|
Dolu1990
|
4440047fb6
|
ICache compressed is working
|
2018-04-16 10:34:18 +02:00 |
|
Dolu1990
|
76352b44fa
|
wip
|
2018-04-13 12:51:27 +02:00 |
|
Dolu1990
|
19d5d1ecf1
|
wip
|
2018-04-09 09:18:08 +02:00 |
|
Dolu1990
|
4dd2997ad5
|
wip
|
2018-04-09 09:12:30 +02:00 |
|
Dolu1990
|
e00c0750eb
|
wip
|
2018-04-03 18:37:05 +02:00 |
|
Dolu1990
|
d9f2e03753
|
statuc prediction is fully funcitonnal
|
2018-04-02 17:43:58 +02:00 |
|
Dolu1990
|
76ca852478
|
Static prediction is fully functionnal
|
2018-04-02 17:43:06 +02:00 |
|
Dolu1990
|
0919308a8f
|
IBusSimplePlugin add relaxedPcCalculation
|
2018-03-23 22:49:32 +01:00 |
|
Dolu1990
|
c48c7170e8
|
Added many pipelining option into IBusSimplePlugin
|
2018-03-23 19:07:03 +01:00 |
|
Dolu1990
|
351ad10925
|
RVC Add dhrystone regressions (PASS)
|
2018-03-21 23:36:57 +01:00 |
|
Dolu1990
|
0c7c2a1fba
|
IBusPlugin add support of bus error when using compressed instruction
|
2018-03-21 22:34:54 +01:00 |
|
Dolu1990
|
31a464ffdc
|
VexRiscv now pass Riscv-test compressed stuff
|
2018-03-21 20:50:07 +01:00 |
|
Dolu1990
|
af638e7bde
|
RV32IC is passing some of the compressed Riscv-test tests
|
2018-03-21 20:30:09 +01:00 |
|
Dolu1990
|
f872d599e2
|
Add decodePcGen
|
2018-03-20 18:34:36 +01:00 |
|
Dolu1990
|
1fb138de1f
|
IBusSimplePlugin fully functional Need to restore branch prediction
|
2018-03-20 00:01:28 +01:00 |
|
Dolu1990
|
ac74fb9ce8
|
iBusSimplePlugin done, DebugPlugin need minor rework
|
2018-03-18 13:21:21 +01:00 |
|
Dolu1990
|
64022557bf
|
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl
|
2018-03-15 18:56:25 +01:00 |
|
Dolu1990
|
63c1b738ff
|
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings
|
2018-03-14 00:56:23 +01:00 |
|
Dolu1990
|
d9b7426cde
|
undo InOutWrapper from Murax
|
2018-03-14 00:47:23 +01:00 |
|
Dolu1990
|
91031f8d75
|
DivPlugin is now based MulDivIterativePlugin (Smaller)
|
2018-03-10 13:31:35 +01:00 |
|
Dolu1990
|
e437a1d44e
|
Add division support in the MulDivInterativePlugin
|
2018-03-09 22:41:47 +01:00 |
|
Dolu1990
|
36438bd306
|
iterative mul improvments
|
2018-03-09 20:00:50 +01:00 |
|
Dolu1990
|
674ab2c594
|
experimental iterative mul/div combo
|
2018-03-09 19:07:26 +01:00 |
|
Dolu1990
|
5228a53293
|
MuraxSim improve simulation Speed
|
2018-03-06 12:20:39 +01:00 |
|
Dolu1990
|
9b2cd7b234
|
MuraxSim add switch
|
2018-03-06 12:17:15 +01:00 |
|
Dolu1990
|
53970dd284
|
SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
|
2018-03-05 14:34:59 +01:00 |
|
Dolu1990
|
ccad64def5
|
Pipeline CSR isWrite
|
2018-02-26 10:19:33 +01:00 |
|
Dolu1990
|
2b6185b063
|
Decoding logic : Add primes duplication removal
|
2018-02-25 08:57:31 +01:00 |
|
Dolu1990
|
2b6f43cef8
|
Fix Murax memory mapping range
|
2018-02-25 08:57:31 +01:00 |
|
Dolu1990
|
5260ad5c35
|
Decoding lib cleaning
|
2018-02-25 08:57:31 +01:00 |
|
Dolu1990
|
137b1ee32c
|
Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values
|
2018-02-22 22:36:13 +01:00 |
|
Dolu1990
|
d957934949
|
Fix ICache exception priority over miss reload
|
2018-02-19 22:44:46 +01:00 |
|
Dolu1990
|
d0e963559a
|
Update readme with the new ICache implementation
|
2018-02-18 23:48:11 +01:00 |
|
Dolu1990
|
93110d3b95
|
Add jump priority managment in PcPlugins
|
2018-02-16 14:27:20 +01:00 |
|
Dolu1990
|
506e0e3f60
|
New faster/smaller/multi way instruction cache design.
Single or dual stage
|
2018-02-16 02:21:08 +01:00 |
|
Dolu1990
|
3853e0313b
|
SynthesisBench cleaning/experiments
|
2018-02-11 14:53:42 +01:00 |
|
Dolu1990
|
0e6ae682b1
|
Add architecture section describing plugins in the readme
|
2018-02-09 00:44:27 +01:00 |
|
Dolu1990
|
57ebfee2e6
|
Add more axi bridges
|
2018-02-08 21:39:22 +01:00 |
|
Dolu1990
|
3ee111e100
|
Update readme (gcc stuff)
|
2018-02-05 16:34:10 +01:00 |
|
Dolu1990
|
d4b05ea365
|
Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
|
2018-02-05 16:16:27 +01:00 |
|
Dolu1990
|
4729e46763
|
Add DummyFencePlugin
|
2018-02-03 12:28:53 +01:00 |
|
Dolu1990
|
f13dba847c
|
Add custom csr gpio example
|
2018-02-02 11:14:55 +01:00 |
|
Dolu1990
|
b7d8ed8a81
|
Add onWrite/onRead/isWriting/isReading on the CsrPlugin
|
2018-02-01 21:28:28 +01:00 |
|
Dolu1990
|
4ee2482cbf
|
Fix custom_csr regression against random ibus stall
|
2018-01-31 18:33:21 +01:00 |
|
Dolu1990
|
d2e5755df4
|
revert removed code by mistake
|
2018-01-31 18:29:30 +01:00 |
|
Dolu1990
|
30b05eaf96
|
Add CsrInterface to allow custom CSR addition
Add CustomCsrDemoPlugin as a show case
|
2018-01-31 18:13:42 +01:00 |
|
Dolu1990
|
bdbf6ecf17
|
BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
|
2018-01-29 14:52:31 +01:00 |
|
Dolu1990
|
0d318ab6b9
|
Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
Add longer timeouts in the regressions tests
|
2018-01-29 13:17:11 +01:00 |
|
Dolu1990
|
307c0b6bfa
|
Now mret and ebreak are only allowed in CSR machine mode
|
2018-01-28 16:34:55 +01:00 |
|
Dolu1990
|
93da5d29bc
|
Fix dhrystone referance log
|
2018-01-28 16:34:55 +01:00 |
|
Dolu1990
|
26732942e5
|
Update DMIPS/Mhz
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
|
2018-01-25 01:11:57 +01:00 |
|
Dolu1990
|
3b3bbd48b9
|
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
|
2018-01-20 18:29:33 +01:00 |
|
Dolu1990
|
6a521a8d13
|
Better MuraxSim gui
Add MuraxSim in the readme
|
2018-01-09 08:59:17 +01:00 |
|
Dolu1990
|
9a89573942
|
SpinalHDL 1.1.2
Add Murax setup with Mul Div Barriel
|
2018-01-06 22:09:42 +01:00 |
|
Dolu1990
|
43d3ffd685
|
CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
|
2018-01-04 17:37:23 +01:00 |
|
Dolu1990
|
2b7465e5df
|
Add more atomic tests (PASS)
|
2018-01-04 16:16:22 +01:00 |
|
Dolu1990
|
611f2f487f
|
Fix DataCache atomic integration into DBusCachedPlugin
Atomic is passing basic tests
|
2018-01-04 15:24:00 +01:00 |
|
Dolu1990
|
4637e6cb48
|
Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode.
add Atomic test flow
|
2018-01-04 14:43:30 +01:00 |
|
Dolu1990
|
468dd3841e
|
Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer
|
2018-01-04 13:16:40 +01:00 |
|
Dolu1990
|
4ed19f2cc5
|
SpinalHDL 1.1.1
|
2017-12-30 03:36:57 +01:00 |
|
Dolu1990
|
0d39e38906
|
SpinalHDL 1.1.0
|
2017-12-28 13:49:39 +01:00 |
|
Dolu1990
|
3c0588eb4b
|
remove MuraxSim fixed path
|
2017-12-19 22:33:46 +01:00 |
|
Dolu1990
|
7f2b2181c1
|
SpinalHDL 1.0.3
|
2017-12-19 21:21:16 +01:00 |
|
Dolu1990
|
37849b7a66
|
Spinal 1.0.2 sim update
|
2017-12-19 00:40:52 +01:00 |
|
Dolu1990
|
ebda7526b5
|
MuraxSim 1.0.0
|
2017-12-17 17:57:09 +01:00 |
|
Dolu1990
|
dda5372a6c
|
Fix typo
|
2017-12-14 01:05:06 +01:00 |
|
Dolu1990
|
d6e0761065
|
Fix led gui refresh rate
|
2017-12-14 01:04:31 +01:00 |
|
Dolu1990
|
2259c9cb0f
|
Add SpinalHDL sim (1.0.0)
|
2017-12-14 00:57:12 +01:00 |
|
Dolu1990
|
e1b86ea511
|
SpinalHDL 0.11.4 update
|
2017-12-01 11:19:23 +01:00 |
|
Dolu1990
|
586d3ed286
|
Update formal VexRiscv to halt on missaligned dbus
|
2017-11-26 15:30:48 +01:00 |
|
Dolu1990
|
4de0aac469
|
Merge branch 'formal'
|
2017-11-24 14:03:25 +01:00 |
|
Dolu1990
|
b7f4f09814
|
Update verilator makefiles to support the last SpinalHDL changes (process merges)
|
2017-11-21 23:56:46 +01:00 |
|
Dolu1990
|
9b9bbaa4ad
|
Add missing full config for the iBus
|
2017-11-21 00:09:02 +01:00 |
|
Dolu1990
|
ce6fd6d0aa
|
Add VexRiscvAxi4 demo
|
2017-11-20 23:57:37 +01:00 |
|
Dolu1990
|
7c19288648
|
Update Synthesis bench
Update some synthesis results
|
2017-11-17 20:10:46 +01:00 |
Tony Kao
|
290dbc106e
|
Fixes GPIO width mismatch
Adds explicit type to apbDecoder.slave to suppress IDE errors
|
2017-11-16 15:02:13 -05:00 |
|
Dolu1990
|
6c3fed3505
|
SpinalHDL 0.11.1
|
2017-11-15 16:44:42 +01:00 |
|
Dolu1990
|
be3d301eaf
|
Merge remote-tracking branch 'origin/spinalhdl_reworkDev'
|
2017-11-12 13:08:05 +01:00 |
|
Dolu1990
|
838c13d68b
|
spinal.core.internals literals import
|
2017-11-10 13:14:30 +01:00 |
|
Dolu1990
|
3060296b94
|
unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch
|
2017-11-10 11:33:04 +01:00 |
|
Dolu1990
|
c3a7f4e58c
|
CSR unsetRegIfNoAssignement fix
BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
|
2017-11-10 00:59:31 +01:00 |
|
Dolu1990
|
d6777ae8ec
|
usetRegIfNoAssign upgrade
|
2017-11-09 20:10:56 +01:00 |
|
Dolu1990
|
a72c7fd0d1
|
Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala
|
2017-11-07 22:19:33 +01:00 |
|
Dolu1990
|
714d44d248
|
Add fixed bug into the FormalPlugin comments
|
2017-11-07 13:54:07 +01:00 |
|
Dolu1990
|
200a73bea0
|
Fix FormalPlugin to pass liveness again.
|
2017-11-06 23:04:33 +01:00 |
|
Dolu1990
|
8098a03a9b
|
with no bus stall, pass all tests except uniqueness
|
2017-11-06 20:26:45 +01:00 |
|
Dolu1990
|
e2a432eb5e
|
add HaltOnExceptionPlugin
wip
|
2017-11-05 20:13:27 +01:00 |
|
Dolu1990
|
276f7895e7
|
Add FormalPlugin
Add FormalSimple CPU configuration
|
2017-11-04 00:55:32 +01:00 |
|
Dolu1990
|
ba42f71813
|
pass VexRiscv regressions
|
2017-10-30 14:29:25 +01:00 |
Ubuntu
|
008a5b7309
|
updated main.cpp
added missing using namespace std
|
2017-10-17 22:09:08 +00:00 |
|
Dolu1990
|
2bf7ca24f2
|
Add VexRiscvAvalonWithIntegratedJtag
|
2017-10-16 11:52:17 +02:00 |
Dolu1990
|
aa859aae6b
|
Update framework.h
Add missing using namespace std;
|
2017-10-05 10:08:09 +02:00 |
|
Dolu1990
|
09ba7c28da
|
Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)
|
2017-08-27 15:21:44 +02:00 |
|
Dolu1990
|
8168c9bf3a
|
Update simd_add makefile
|
2017-08-27 14:49:36 +02:00 |
|
Charles Papon
|
2c6889e688
|
Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU
Murax add dhrystone config
|
2017-08-10 22:48:00 +02:00 |