d5b1a8f565
Add PMP test to regression suite
2020-12-01 18:38:06 +01:00
45ff78d068
VexRiscvSmpClusterGen.dBusCmdMasterPipe option added
2020-12-01 13:51:10 +01:00
c5023ad973
Add PMP regression test
2020-12-01 09:10:24 +01:00
2d0ebf1ef5
Flush pipeline after PMP CSR writes
2020-11-25 15:38:34 +01:00
e0ae46e794
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
...
# Conflicts:
# src/main/scala/vexriscv/plugin/CsrPlugin.scala
2020-11-18 14:43:24 +01:00
832218dbec
DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context
2020-11-16 12:38:29 +01:00
ba523c627a
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
2020-11-16 12:37:48 +01:00
c1b0869c21
AesPlugin is now little endian
2020-11-12 15:07:27 +01:00
1b2a2ebaca
DBusCachedPlugin miss decoded aquire fix
2020-11-12 15:07:07 +01:00
05e725174c
AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal)
2020-11-02 17:14:52 +01:00
9abe19317d
RegFilePlugin.x0Init do less assumption on other plugin behaviour
2020-11-02 17:01:17 +01:00
97fe279f7b
Enable PMP register lock
2020-10-29 13:37:21 +01:00
dc9246715d
Do not allow jtag ebreak outside machine mode
2020-10-28 13:00:16 +01:00
4209dc2792
Fix CsrPlugin privilege crossing
2020-10-28 13:00:15 +01:00
576e21d75d
Do not allow jtag ebreak outside machine mode
2020-10-28 12:58:24 +01:00
abebeaea1f
Fix CsrPlugin privilege crossing
2020-10-28 12:57:20 +01:00
fc2c8a7c37
Initial commit of PMP plugin
2020-10-27 09:38:58 +01:00
fe342c347c
CfuBusParameter has now a few default values
2020-10-23 11:06:24 +02:00
6c8e97f825
Update big endian instruction encoding
...
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.
Update the big endian instruction pipe to reflect the newer requirement.
2020-10-20 18:05:31 +02:00
4ece59385d
DataCache split redo / refilling execute stage halt
2020-10-19 18:12:20 +02:00
ec55187033
improve LightShifterPlugin arbitration halt timings
2020-10-09 11:37:48 +02:00
bbaa0520c0
Fix UserInterruptPlugin interrupt enable
2020-10-09 10:45:23 +02:00
72f85ef6c0
Merge remote-tracking branch 'origin/dev' into dev-asid
2020-10-04 19:53:29 +08:00
65e6f6054b
Add ASID field to SATP
...
ASID field is missing from the SATP which causes compatibility
issues with Xous.
While this patch resolves the Xous issue, it has not been tested
on Linux.
2020-10-04 15:34:58 +08:00
98de02051e
Merge pull request #135 from zeldin/bigendian
...
Add support for big endian byte ordering
2020-10-01 16:43:00 +02:00
3f5e771a5c
dbus mmu access improvement
2020-09-17 22:06:29 +02:00
de820daf74
add earlyBranch option to Smp config
2020-09-13 18:33:06 +02:00
49488d19af
pipeline data cache unaligned access check
2020-09-07 12:01:11 +02:00
8e466dd13c
Add support for RV32E in RegFilePlugin
...
The RV32E extension removes registers x16-x31 from the ISA. This
is useful when compiling with -mem2reg to save on BRAMs. On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.
Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
2020-09-06 17:05:31 +02:00
4c3cad97d3
fix CfuPlugin generation
2020-09-04 10:36:12 +02:00
c489143442
Add support for big endian byte ordering
2020-08-30 15:17:09 +02:00
7dcaa0c390
VexRiscvSmpCluster now avoid useless decoder for plic/clint
2020-08-13 11:26:11 +02:00
69d5ba239a
Smp config now initialise regfile using logic
2020-07-28 16:15:17 +02:00
cc423cbe49
Litex cluster add DMA sel feature
2020-07-21 19:42:27 +02:00
15bda15bc9
Litex cluster can now set cache layout
2020-07-21 19:35:56 +02:00
9f62f37538
improve LitexCluster area for single core configuration
2020-07-21 15:45:02 +02:00
da666ade49
Add VexRiscvLitexSmpClusterCmdGen
2020-07-21 15:07:32 +02:00
fe5401f835
BmbGenerators refractoring (bus -> ctrl)
2020-07-16 13:04:25 +02:00
da73317912
Cleanup BmbGenerators
2020-07-15 20:51:46 +02:00
5f0aec7570
BmbInterconnectGenerator refractoring
2020-07-15 17:03:05 +02:00
d0a572de98
Add openroad config
2020-07-08 01:37:10 +02:00
32f778613f
DBusCachedPlugin now support asyncTagMemory
2020-07-08 01:36:58 +02:00
60ee7e2b4c
Better VexRiscvSmpCluster config
2020-07-08 01:36:40 +02:00
51070d0e69
Fix MmuPlugin when used in multi stage config
2020-07-05 13:17:39 +02:00
06584518da
Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck
2020-07-05 13:17:07 +02:00
a404078117
Few fixes
2020-07-05 13:16:39 +02:00
c51e25f8c4
Litex SoC add coherent DMA master
2020-07-05 13:15:44 +02:00
32539dfe6d
Got VexRiscvSmpLitexCluster refractoring to work
2020-06-30 22:29:33 +02:00
0da94ac66f
Bring back smp cluster parameters
2020-06-29 15:49:01 +02:00
062509deee
Update Bmb brides and comment out SmpCluster for now
2020-06-29 11:44:10 +02:00
c12f9a378d
Fix inv regression
2020-06-20 13:18:46 +02:00
f0f2cf61da
D$ inv/ack are now fragment, which ease serialisation of wider invalidations
2020-06-19 15:57:56 +02:00
c18bc12cb2
Fix DebugPlugin.fromBmb
2020-06-19 15:57:21 +02:00
490c1f6b02
cleanup of old todo
2020-06-19 15:56:45 +02:00
b0cd88c462
SmpCluster now with proper jtag and plic
2020-06-12 16:18:41 +02:00
cb5597818d
Fix d$ generation crash
2020-06-07 11:29:07 +02:00
1f9fce6388
Fix d$ uncached writes exception handeling
2020-06-06 22:12:37 +02:00
760d2f74d0
Update litex cluster to implement utime
2020-06-05 13:31:24 +02:00
d6455817e7
smp cluster now have 2w*4KB of d$ , no more rdtime emulation
2020-06-05 10:43:03 +02:00
71760ea372
CsrPlugin now support utime csr to avoid emulation
2020-06-05 10:43:03 +02:00
3dafe8708b
Cfu update
2020-06-05 10:43:03 +02:00
0668046407
More smp cluster profiling
2020-06-05 10:40:51 +02:00
97c2dc270c
Fix typo
2020-06-04 10:11:30 +02:00
89c13bedbd
Fix litex smp cluster sim
2020-06-03 16:31:54 +02:00
73f88e47cb
Fix BmbToLitexDram coherency
2020-06-03 16:31:54 +02:00
db50f04653
Add litexMpCluster
2020-06-03 16:31:54 +02:00
08189ee907
DebugPlugin now support Bmb
2020-06-02 19:13:55 +02:00
2942d0652a
fix Briey verilator
2020-06-01 11:18:25 +02:00
5e5c730959
Add LitexSmpDevCluster with per cpu dedicated litedram ports
2020-05-29 10:56:55 +02:00
bc4a2c3747
Fix SmpCluster jtag
2020-05-27 14:19:37 +02:00
18cce053a3
Improve SingleInstructionLimiterPlugin to also include fetch stages
2020-05-27 14:19:17 +02:00
a64fd9cf3b
Add CsrPlugin external hartid
...
d$ rsp/sync now decrement pendings by signal amount
2020-05-20 13:49:10 +02:00
b901651ab5
Add default value of NONE to uinstret CSR.
2020-05-19 14:48:35 -07:00
c74b03b4de
Add uinstret support.
2020-05-19 13:40:46 -07:00
cf60989ae1
Litex smp cluster now blackboxify d$ data ram
2020-05-14 00:05:54 +02:00
42fef8bbcd
Smp cluster now use i$ reduceBankWidth
2020-05-12 23:59:38 +02:00
685c914227
Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width
2020-05-12 23:59:38 +02:00
0471c7ad76
Fix machineCsr test
2020-05-12 23:55:47 +02:00
cb44a474fc
more smp cluster profiling
2020-05-12 13:25:55 +02:00
63511b19a2
smp cluster add more profiling
2020-05-11 10:35:24 +02:00
b592b0bff8
Add regression TRACE_SPORADIC, LINUX_SOC_SMP
...
regression golden model now properly sync dut exceptions
2020-05-09 17:00:13 +02:00
0a159f06b2
update smp config
2020-05-07 22:50:36 +02:00
0e76cf9ac8
i$ now support multi cycle MMU
2020-05-07 22:50:25 +02:00
41ee8fd226
MmuPlugin now support multiple stages, D$ can now take advantage of that
2020-05-07 13:37:53 +02:00
8e025aeeaa
more litex smp cluster pipelining
2020-05-07 13:18:11 +02:00
fc0f3a2020
cleanup mmu interface
2020-05-06 18:05:20 +02:00
6323caf265
MMU now allow $ to match tag against tlb pyhsical values directly
...
D$ retiming
D$ directTlbHit feature added for better timings
2020-05-06 17:09:46 +02:00
ed4a89e4af
more pipelineing in Litex SMP cluster interconnect
2020-05-06 17:06:45 +02:00
8043feebd5
More VexRiscv smp cluster probes
2020-05-06 17:06:17 +02:00
09724e907b
play around with CSR synthesis impact on design size
2020-05-05 00:32:59 +02:00
c16f2ed787
Add probes in SmpCluster sim
2020-05-04 12:54:28 +02:00
b0f7f37ac8
D$ now support memDataWidth > 32
2020-05-04 12:54:16 +02:00
93b386e16e
litex smp cluster now use OO decoder
2020-05-02 23:44:58 +02:00
f0745eb0d9
update SMP line size to 64 bytes
2020-05-02 23:44:27 +02:00
09ac23b78f
Fix SMP fence lock when 4 stages CPU
2020-05-01 12:45:16 +02:00
f5f30615ba
Got litex SMP cluster to work on FPGA
2020-05-01 11:14:52 +02:00
dc0da9662a
Update SMP fence (final)
2020-05-01 11:14:11 +02:00
7c50fa6d55
SmpCluster now use i$ line of 64 bytes
2020-04-29 14:03:00 +02:00
9e9d28bfa6
d$ now implement consistancy hazard by using writeback redo
2020-04-29 14:02:41 +02:00
86e0cbc1f3
I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage
2020-04-29 13:59:43 +02:00
7b80e1fc30
Set SMP workspace to use i$ memDataWidth of 128 bits
2020-04-28 22:11:41 +02:00
eee9927baf
IBusCachedPlugin now support memory data width multiple of 32
2020-04-28 22:10:56 +02:00
03a0445775
Fix SMP for configuration without writeback stage.
...
Include SMP core into the single core tests regressions
2020-04-28 15:50:20 +02:00
4a49b23636
Fix regression
2020-04-28 14:38:27 +02:00
3ba509931c
Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
2020-04-27 17:38:06 +02:00
5fd0b220cd
CsrPlugin add openSbi config
2020-04-27 17:37:30 +02:00
0c59dd9ed3
SMP fence now ensure ordering for all kinds of memory transfers
2020-04-27 17:37:15 +02:00
3fb123a64a
fix withStall
2020-04-21 21:20:54 +02:00
3885e52bb7
Merge remote-tracking branch 'origin/dev' into smp
2020-04-21 17:21:48 +02:00
056bf63866
Add more consistancy tests
2020-04-21 16:03:03 +02:00
b389878d23
Add smp consistency check, fix VexRiscv invalidation read during write hazard logic
2020-04-21 12:18:10 +02:00
0e55caacab
deduplicae VexRiscv wishbone
2020-04-21 10:33:51 +02:00
b383b4b98b
Add commented usage of fromXilinxBscane2
2020-04-20 12:13:12 +02:00
8e8b64feaa
Got full linux / buildroot to boot in 4 cpu config
2020-04-19 19:49:26 +02:00
a1b6353d6b
workaround AMO LR/SC consistancy issue, but that need a proper fix
2020-04-19 19:48:57 +02:00
ad2d2e411a
Add tap less debug plugin bridges
2020-04-19 17:56:33 +02:00
af128ec9eb
revert to 4 cpu
2020-04-18 01:27:35 +02:00
4a49e6d91f
initialize the clint in sim
2020-04-18 01:26:31 +02:00
befecc7ed6
cleaning
2020-04-18 00:51:57 +02:00
8c0e534c6b
Add openSBI test, seem to work fine
2020-04-18 00:51:47 +02:00
d5a52caab8
fix smp test barrier
2020-04-16 17:27:27 +02:00
d88d04dbc4
More SMP tests (barrier via AMO and LRSC)
2020-04-16 15:23:25 +02:00
fd52f9ba50
Add smp.bin
2020-04-16 02:22:18 +02:00
73c21177e5
Add VexRiscvSmpCluster, seem to work on simple case
2020-04-16 01:30:03 +02:00
b9ceabf128
few fixes
2020-04-16 01:29:13 +02:00
46207abbc4
dataCache now implement invalidation sync
2020-04-16 01:28:38 +02:00
a00605b10c
fix Briey verilator
2020-04-13 13:01:12 +02:00
467a2bc488
refactor DBus invalidation, and add invalidation enable
2020-04-11 19:06:22 +02:00
abbfaf6bcf
regression : restore normal invalidation setup
2020-04-10 18:58:03 +02:00
4a9b8c1f72
improve invalidation read during write hazard logic
2020-04-10 14:44:28 +02:00
0ad0f5ed3f
Add d$ invalidation tests
...
fix d$ invalidation, linux OK
2020-04-10 14:28:16 +02:00
f71f360e32
Add SMP synthesis
2020-04-10 14:27:39 +02:00
296cb44bc4
Add hardware AMO support using LR/SC exclusive
2020-04-09 20:12:37 +02:00
1d0e180e1d
Add GenTwoStage config and UltraScale synthesis
2020-04-09 20:11:56 +02:00
861df664cf
clean some AMO stuff
2020-04-08 18:48:01 +02:00
6922f80a87
DataCache now implement fence operations
2020-04-08 18:12:13 +02:00
9e1817a280
fix DataCache for config without invalidation
2020-04-07 20:05:24 +02:00
0c8ea4a368
DataCache add invalidation feature
2020-04-07 19:18:20 +02:00
1ef099e308
Merge branch 'dev' into smp
2020-04-07 12:29:58 +02:00
f20eb4d541
Merge pull request #115 from antmicro/fix_emulator
...
emulator: Use external hw/common.h from LiteX
2020-04-07 12:29:40 +02:00
ddc59bc404
Fix DebugPlugin step by step
2020-04-07 12:27:52 +02:00
5aa0b86d96
Fix DebugPlugin step by step
2020-04-07 12:13:40 +02:00
a52b833727
fix weird regression testbench memory bug
2020-04-06 21:42:44 +02:00
a107e45116
fix non smp regression
2020-04-06 06:43:28 +02:00
ca72a421be
LrSc align software model to the hardware. Linux OK
2020-04-05 21:45:45 +02:00
2eec18de65
LrSc SMP, linux crash in userspace
2020-04-05 16:28:46 +02:00
f2ef8e95ab
Implement external LrSc
2020-04-05 11:38:57 +02:00
ff074459ad
Fix LrSc for configs without mmu
2020-04-04 22:54:35 +02:00
c9bbf0d12a
update LrSc reservation logic to match the spec
2020-04-04 21:21:35 +02:00
2dac7dae32
Fix BranchPlugin.jumpInterface priority to avoid conflicts with other instructions on DYNAMIC_TARGET missprediction
2020-03-28 14:36:06 +01:00
Samuel Lindemer
Dolu1990
Marcus Comstedt
bunnie
Tom Verbeure