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Author SHA1 Message Date
enjoy-digital
93c623251b
Merge pull request #122 from daveshah1/trellis_ulx3s 
Switch Trellis build to use LPF constraints; working on ULX3S
 2018-11-02 19:59:23 +01:00
Jean-François Nguyen
dcbe759b64 build/sim/verilator: don't use --threads when $(THREADS) is unset 2018-11-02 14:22:44 +01:00
Florent Kermarrec
6f38213acc boards/platforms/kc705: add user_sma_mgt_refclk 2018-11-01 10:52:01 +01:00
enjoy-digital
4cdd679908
Merge pull request #123 from cr1901/prv32-min 
PicoRV32 Enhancements
 2018-11-01 10:45:32 +01:00
William D. Jones
e56f71824d libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). 2018-11-01 05:02:04 -04:00
William D. Jones
f32121e0e1 cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. 2018-11-01 02:23:01 -04:00
William D. Jones
77389d27b5 libbase/crt0-picorv32: Ensure BSS is cleared on boot. 2018-11-01 02:18:03 -04:00
Florent Kermarrec
f7969b660a cores/clock: add with_reset parameter (default to True) 
In some cases we want to generate the reset externally.
 2018-10-31 16:23:23 +01:00
David Shah
0729b3a059 ulx3s: Connect SDRAM clock 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 13:29:35 +00:00
David Shah
8404434956 Fix Trellis build; ULX3S demo boots to BIOS 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 12:27:05 +00:00
David Shah
0c1d8d5993 trellis: Switch to using LPF for constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-31 11:43:39 +00:00
Florent Kermarrec
445c49400f boards/platforms/kcu105: add sfp_tx/rx definition 2018-10-31 10:48:48 +01:00
William D. Jones
f69bd877b9 cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). 2018-10-30 06:00:45 -04:00
William D. Jones
d05fe673a0 cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. 2018-10-30 06:00:45 -04:00
Florent Kermarrec
e9d4c882ba build/lattice/prjtrellis: fix default toolchain_path 2018-10-30 10:28:12 +01:00
Florent Kermarrec
468780c045 soc/cores/spi_flash: add endianness parameter 2018-10-30 10:19:21 +01:00
Florent Kermarrec
6f3131e259 soc/interconnect/stream_packet: use reverse_bytes from litex.gen 2018-10-30 10:16:55 +01:00
Florent Kermarrec
b796853893 gen: add common with reverse_bits/reverse_bytes functions 2018-10-30 10:15:29 +01:00
Florent Kermarrec
71fc34d7b6 boards/targets/ulx3s: reduce l2_size 2018-10-30 10:14:48 +01:00
Florent Kermarrec
75d073f394 build/lattice/prjtrellis: fix typo 2018-10-30 10:14:30 +01:00
Florent Kermarrec
6048a5291c build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts. 
nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
 2018-10-30 08:54:30 +01:00
Florent Kermarrec
2243f628f7 build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl 2018-10-30 08:47:12 +01:00
William D. Jones
f3111e1142
Update vivado.py 
Fix regression which caused Vivado to not be run at all.
 2018-10-29 23:43:32 -04:00
Florent Kermarrec
98fa899692 boards/targets: add ulx3s 2018-10-29 19:24:28 +01:00
Florent Kermarrec
7d779473f1 boards/platforms: add ulx3s 2018-10-29 19:23:59 +01:00
Florent Kermarrec
d9dcad33a4 build/lattice/prjtrellis: add inout support 2018-10-29 19:23:21 +01:00
Florent Kermarrec
091ad799b0 build/lattice/common: add tristate support 2018-10-29 19:22:04 +01:00
Florent Kermarrec
23acefb14e boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed 
simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
 2018-10-29 16:02:25 +01:00
Florent Kermarrec
1097f82283 build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis" 2018-10-29 15:58:54 +01:00
Florent Kermarrec
52917a710e boards/targets/simple: add gateware-toolchain parameter 2018-10-29 15:56:46 +01:00
Florent Kermarrec
d84083f642 boards/platforms/versaecp55g: use ftdi serial pins 2018-10-29 15:39:51 +01:00
Florent Kermarrec
c05b9ef2ad build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support 2018-10-29 13:26:29 +01:00
Florent Kermarrec
a8f819fec2 Merge branch 'master' of http://github.com/enjoy-digital/litex 2018-10-29 11:48:10 +01:00
Florent Kermarrec
4eb314a252 boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :) 2018-10-29 11:46:03 +01:00
Florent Kermarrec
27ec2a59e2 build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO 
PrjTrellis does not yet have constraint files support, constraints are set
with signal attributes and specific TRELLIS_IO instances are requested. This
iowrapper does this work for us automatically.

Remove this code and replace with a constraint file generation code when
PrjTrellis will have constraint file support.
 2018-10-29 11:44:31 +01:00
Florent Kermarrec
c506c9752c gen/fhdl/verilog: set direction to io signals 2018-10-29 11:41:04 +01:00
Tim 'mithro' Ansell
1cac079efa litex/build: Always run Vivado. 
When using Yosys for synthesis, still need Vivado for place and route.
 2018-10-29 02:04:44 -07:00
Florent Kermarrec
49dab3b448 build/lattice/prjtrellis: simplify code, remove some workarounds 2018-10-29 09:40:35 +01:00
Florent Kermarrec
a73d9d96b1 build/xilinx/vivado: fix merge issue 2018-10-29 08:26:13 +01:00
Florent Kermarrec
3e189379f9 boards/targets: add versa ecp55g prjtrellis target (experimental) 2018-10-28 19:34:17 +01:00
Florent Kermarrec
a69197d2db build/lattice: add initial prjtrellis support 2018-10-28 17:51:16 +01:00
Florent Kermarrec
397e3c7682 build/lattice/diamond: use bash on linux 2018-10-28 15:40:52 +01:00
Florent Kermarrec
d029cd243d build/lattice: improve special_overrides names (vendor_family) 2018-10-28 15:40:10 +01:00
enjoy-digital
b200ce9983
Merge branch 'master' into xilinx+yosys 2018-10-28 14:59:03 +01:00
Tim 'mithro' Ansell
ba0dd5728e uart: Enable buffering the FIFO. 
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
 2018-10-27 16:04:58 -07:00
Florent Kermarrec
e3935b481e build/sim/verilator: don't use THEADS parameters when threads=1 
Allow using old (non multi-threaded) version of Verilator
 2018-10-27 11:06:34 +02:00
Florent Kermarrec
a44181e716 soc_sdram: update litedram 2018-10-19 18:37:55 +02:00
Florent Kermarrec
ab6a530a24 bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode 2018-10-18 13:42:51 +02:00
Florent Kermarrec
b8be9545cc build/xilinx/vivado: enable xpm libraries 2018-10-18 09:25:34 +02:00
Florent Kermarrec
ab8cf3e345 soc/cores/clock: add margin parameter to create_clkout (default = 1%) 2018-10-16 14:57:37 +02:00
Florent Kermarrec
915c2f417a bios/sdram: improve write/read leveling 
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
 2018-10-10 10:42:56 +02:00
Florent Kermarrec
deffa60324 platforms/kc705: add ddram_dual_rank 2018-10-09 15:39:03 +02:00
Florent Kermarrec
10624c26da bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) 2018-10-09 10:06:51 +02:00
enjoy-digital
9f083e9bd3
Merge pull request #116 from stffrdhrn/sim-uart 
sim: serial: Send '\r\n' instead of just '\n'
 2018-10-09 07:32:31 +02:00
Stafford Horne
8877dba7e9 sim: serial: Send '\r\n' instead of just '\n' 
This fixes an issue when running with the HDMI2USB firmware which
expects \r\n to come from the UART.  Since the verilator adapter
is just sending \n commands cannot be executed.

Also, one minor whitespace cleanup. (could remove if needed)
 2018-10-09 11:18:11 +09:00
Florent Kermarrec
d187921500 cpu_interface: fix select_triple when only one specified 2018-10-08 17:01:04 +02:00
Florent Kermarrec
3b27d2ae89 soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains 2018-10-06 21:32:38 +02:00
Florent Kermarrec
168b07b9a2 soc_core: add csr range check 2018-10-06 20:55:16 +02:00
Tim 'mithro' Ansell
ace976242e build.xilinx: Convert attributes to something Yosys understands. 
Convert keep, dont_touch and async_reg to something Yosys understands.

Write out an EDIF file with the attributes so that Vivado can use them.
(Requires Yosys with commit
115ca57647)
 2018-10-05 12:48:30 -07:00
enjoy-digital
6febb6826c
Merge pull request #112 from cr1901/8k-b-evn 
build/platforms: Add ice40_hx8k_b_evn from Migen.
 2018-10-04 21:12:33 +02:00
Stafford Horne
ff6de429f0 Fix help for or1k builds 
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx.  Fix the message to properly represent what
needs to be passed to the commandline.
 2018-10-04 23:09:49 +09:00
Stafford Horne
dafdb8df72 Fix compiler warnings from GCC 8.1 
Fix these 2 warnings:

 litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
 [-Wstringop-truncation]
     strncpy(last_err, s, ERR_MAX_SIZE);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 In function 'set_last_error',

 litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  static char emerg_getc()
 2018-10-04 23:07:48 +09:00
Florent Kermarrec
2be5205463 build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) 2018-10-04 08:17:44 +02:00
Tim 'mithro' Ansell
78414c0588 xilinx/viviado: Allow yosys for synthesis. 2018-10-03 21:58:03 -07:00
Tim 'mithro' Ansell
d13ac3b3d5 cpu/mor1kx: Adding verilog include directory. 2018-10-03 21:57:24 -07:00
William D. Jones
9a44f08a3e build/platforms: Add ice40_hx8k_b_evn from Migen. 2018-10-03 20:53:33 -04:00
Tim 'mithro' Ansell
dc7cd75757 build.xilinx: Run phys_opt_design and generate timing report. 
Makes the flow more similar to migen.
 2018-10-03 16:02:43 -07:00
Florent Kermarrec
948527b0fe cores/cpu: revert vexriscv (it seems there is a regression in last version) 2018-10-02 12:30:11 +02:00
Florent Kermarrec
15bca4535f targets/sim: fix integrated_main_ram_size when with_sdram 2018-10-02 11:31:08 +02:00
Florent Kermarrec
6e327cda26 bios/sdram: rewrite write_leveling (simplify and improve robustness) 2018-10-01 15:38:19 +02:00
Florent Kermarrec
975be6686f platforms/genesys2: add eth clock timing constraint 2018-10-01 15:37:34 +02:00
Florent Kermarrec
934a5da559 soc/cores/clock: add expose_drp on S7PLL/S7MMCM 2018-09-28 13:02:10 +02:00
enjoy-digital
9097573e71
Merge pull request #109 from cr1901/xip-improve 
Improve XIP Support
 2018-09-25 15:32:04 +02:00
Florent Kermarrec
082b03016c targets: use new clock abstraction on all 7-series targets 2018-09-25 09:31:30 +02:00
Florent Kermarrec
74e74dc0e7 soc/cores/clock: different clkin_freq_range for pll and mmcm 2018-09-25 09:09:47 +02:00
Florent Kermarrec
91d8cc2d6a soc/cores/clock: different vco_freq_range for pll and mmcm 2018-09-25 09:04:38 +02:00
Florent Kermarrec
6cd954940c soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) 2018-09-25 08:36:18 +02:00
Florent Kermarrec
912ca3236b soc/cores/clock: create specific S7IDELAYCTRL module 2018-09-24 23:22:59 +02:00
Florent Kermarrec
baec87f530 soc/cores/clock: add S7MMCM support 2018-09-24 23:20:12 +02:00
Florent Kermarrec
ef40524924 soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) 2018-09-24 22:58:23 +02:00
Florent Kermarrec
5415b521be targets/arty: use new clock abstraction module (compile, untested on board) 2018-09-24 22:49:30 +02:00
Florent Kermarrec
63fc395006 soc/cores: init clock abstraction module 2018-09-24 22:49:01 +02:00
William D. Jones
0ff6d58605 Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). 2018-09-24 14:48:54 -04:00
William D. Jones
8106008184 integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. 2018-09-24 12:28:45 -04:00
William D. Jones
db90619067 integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). 2018-09-24 11:04:57 -04:00
Florent Kermarrec
70a32ed86f sim/verilator: add multithread support (default=1) 2018-09-24 12:43:29 +02:00
Florent Kermarrec
7f0d116d88 soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) 2018-09-24 10:59:32 +02:00
Florent Kermarrec
22febe9582 boards/targets: uniformize things between targets 2018-09-24 10:58:10 +02:00
Florent Kermarrec
01b025aafd soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication 2018-09-24 08:01:32 +02:00
Florent Kermarrec
b528a005a0 cores/cpu: add software informations to cpu and simplify cpu_interface 2018-09-24 07:51:41 +02:00
Florent Kermarrec
2d785cb0ac boards/plarforms: fix issues found while testing simple design on all platforms 2018-09-24 02:03:30 +02:00
Florent Kermarrec
c88029d330 soc_core: add uart-stub argument 2018-09-24 02:01:15 +02:00
Florent Kermarrec
e9ed737037 ease RemoteClient import 2018-09-23 10:23:00 +02:00
Sean Cross
6f25a0d8a1 csr: use external csr_readl()/csr_writel() if present 
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.

With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:55:09 +02:00
Sean Cross
9a252e367c csr: use readl()/writel() accessors for accessing mmio 
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-09-22 16:54:46 +02:00
William D. Jones
9d4da737ff libbase/crt0-lm32.S: Add provisions for loading .data from flash. 
:100644 100644 e0cd7153 34428845 M	litex/soc/software/libbase/crt0-lm32.S
 2018-09-21 10:23:14 -04:00
Florent Kermarrec
15e584d880 targets/sim: generate analyzer.csv 2018-09-20 12:20:48 +02:00
Florent Kermarrec
cde72603a1 targets/sim: generate csr.csv 2018-09-20 11:17:18 +02:00
Florent Kermarrec
f62df5023f targets/sim: add rom-init 2018-09-20 01:14:00 +02:00
Florent Kermarrec
1dbf591e78 targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) 2018-09-20 01:00:13 +02:00
Florent Kermarrec
9893c2460a integration/soc_core: add get_mem_data function to read memory content from file 2018-09-20 00:46:06 +02:00
Florent Kermarrec
a3eb2e403b soc/intergration/builder: fix when no sdram 2018-09-19 23:59:42 +02:00
Florent Kermarrec
934b08ede8 targets/sim: merge in a single class and ease configuration 2018-09-19 23:59:15 +02:00
Florent Kermarrec
bd42b18856 Merge branch 'master' of http://github.com/enjoy-digital/litex 2018-09-19 19:21:14 +02:00
Florent Kermarrec
3e77ae788f targets: replace MiniSoC with EthernetSoC 2018-09-19 19:19:50 +02:00
Florent Kermarrec
badd992469 targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) 2018-09-19 19:17:32 +02:00
enjoy-digital
537b0e9058
Merge pull request #101 from cr1901/icestorm-migen-pull 
Icestorm Improvements
 2018-09-18 08:19:09 +02:00
William D. Jones
5c83c88128 Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. 2018-09-17 21:17:24 -04:00
Florent Kermarrec
9c6f76f18c bios/sdram: mode sdhw() 2018-09-13 06:33:54 +02:00
Florent Kermarrec
a44bedd557 bios/sdram: add missing #ifdef 2018-09-13 06:30:37 +02:00
Florent Kermarrec
0e68daebf3 targets: self.pll_sys --> pll_sys 2018-09-13 05:31:35 +02:00
Florent Kermarrec
1468b9f3ba bios/sdram: show all read scans when failing. 2018-09-13 05:26:51 +02:00
Florent Kermarrec
07e4c183cd cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) 2018-09-12 06:02:23 +02:00
Florent Kermarrec
df3f003ecd soc_sdram: update with litedram 2018-09-09 02:13:00 +02:00
enjoy-digital
bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram 
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
 2018-09-08 03:55:23 +02:00
William D. Jones
bd70ba278b Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. 2018-09-07 21:49:24 -04:00
enjoy-digital
69716852f1
Merge pull request #100 from cr1901/tinyprog-fix 
lattice/programmer: Use --program-image option with tinyprog if addre…
 2018-09-08 03:48:04 +02:00
Florent Kermarrec
12a8944711 soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) 2018-09-07 11:51:17 +02:00
Florent Kermarrec
2b786065b1 targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen 2018-09-07 10:37:15 +02:00
William D. Jones
c812321a93 lattice/programmer: Use --program-image option with tinyprog if address is given. 2018-09-07 04:05:49 -04:00
Jean-François Nguyen
26963d62fa libnet/microudp: (WIP) fix endianness issues 2018-09-06 18:43:55 +02:00
Jean-François Nguyen
22c0131324 fix typo and unused include 2018-09-06 17:07:14 +02:00
Florent Kermarrec
fb24ac0ecc cpu/minerva: add workaround on import until code is released 2018-09-06 16:40:30 +02:00
Jean-François Nguyen
8f377307d8 add Minerva support 2018-09-05 22:33:04 +02:00
Florent Kermarrec
1944289e64 litex_server: update pcie and remove bar_size parameter 2018-09-05 13:01:51 +02:00
Tim Ansell
c5a2d6f3ec
Merge pull request #96 from cr1901/tinyfpga_bx 
build/platforms: Add TinyFPGA BX board and programmer.
 2018-09-03 20:49:33 -07:00
William D. Jones
2949262449 build/platforms: Add TinyFPGA BX board and programmer. 2018-09-03 23:39:40 -04:00
William D. Jones
ed507d618d Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. 2018-09-03 19:48:19 -04:00
William D. Jones
7af89efc70 lattice/icestorm: Add nextpnr pnr as alternate pnr tool. 2018-08-28 05:17:32 -04:00
Tim Ansell
ff908e404f
Merge pull request #92 from cr1901/l2-gate 
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
 2018-08-23 13:15:49 +10:00
William D. Jones
3146109af3 software/bios: Gate flush_l2_cache() if L2 Cache isn't present. 2018-08-22 23:03:08 -04:00
Florent Kermarrec
759e7d4dc3 bios/sdram: improve/simplify read window selection 
Compute a score for each window and select the best
 2018-08-22 23:15:32 +02:00
Florent Kermarrec
09776b77e6 sim: run as root only when needed (ethernet module present) 2018-08-22 15:20:28 +02:00
Florent Kermarrec
06e835a3f8 builder: change call to get_sdram_phy_c_header and also pass timing_settings 2018-08-22 14:28:37 +02:00
Florent Kermarrec
ee26f8c5ae soc_sdram: cosmetic 2018-08-22 13:40:22 +02:00
Florent Kermarrec
2db5424ae6 soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) 2018-08-22 13:28:23 +02:00
Florent Kermarrec
45e9a42c7e soc_core: add cpu_endianness 2018-08-21 19:10:22 +02:00
Florent Kermarrec
3877d0f111 builder: get_sdram_phy_header renamed to get_sdram_phy_c_header 2018-08-21 18:15:57 +02:00
Florent Kermarrec
c64e44ef3f soc_sdram: use new LiteDRAMWishbone2Native and port.data_width 2018-08-21 14:52:28 +02:00
Florent Kermarrec
2eeccc5054 vexriscv: update 2018-08-21 11:04:15 +02:00
Florent Kermarrec
eecc6f68ed soc/integration: move sdram_init to litedram 2018-08-20 15:36:51 +02:00
Florent Kermarrec
077f939169 Vexriscv: update csr-defs.h 2018-08-18 14:15:43 +02:00
Florent Kermarrec
4225c3b87c update Vexriscv 2018-08-18 14:14:00 +02:00
Florent Kermarrec
9547938527 bios/sdram: changes to ease manual read window selection 2018-08-18 13:45:22 +02:00
Florent Kermarrec
a760322fbd litex_server: allow multiple clients to connect to the same server 2018-08-17 16:09:08 +02:00
Florent Kermarrec
8a69a47e7b cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) 2018-08-17 08:32:32 +02:00
Florent Kermarrec
cb5b4ac468 bios/boot: flush all caches before running from ram 2018-08-16 19:47:43 +02:00
Florent Kermarrec
650ac18685 sim/verilator: catch ctrl-c on exit and revert default termios settings 2018-08-16 15:13:27 +02:00
Florent Kermarrec
0831ad5492 cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf 2018-08-16 10:04:09 +02:00
Florent Kermarrec
1610a7f3fb bios/sdram: fix read_level_scan result 2018-08-14 18:33:36 +02:00
Peter Gielda
3c7890cdd4
Fix generating csr.csv file 
Fix generating csr.csv file when no absolute path is given.
 2018-08-12 13:37:39 +02:00
Florent Kermarrec
9fa234da50 soc/intergration/cpu_interface: typo 2018-08-08 08:53:54 +02:00
Florent Kermarrec
22f645adc1 bios/main: use edata instead of erodata 2018-08-07 09:02:09 +02:00
Florent Kermarrec
580efecc8c picorv32: add reset signal 2018-08-07 08:59:34 +02:00
Florent Kermarrec
0429ee9f8f soc/software/bios: add reboot command 2018-08-06 12:23:50 +02:00
Florent Kermarrec
da75159814 soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers 2018-08-06 12:23:16 +02:00
Florent Kermarrec
8ba5625227 soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. 2018-08-06 12:21:18 +02:00
Florent Kermarrec
c0989f65dd soc/cores/cpu: add reset signal 2018-08-06 12:19:23 +02:00
Sean Cross
fb145daced tools: remove vexriscv_debug 
This program is no longer needed.

The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.

This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:25:33 +08:00
Sean Cross
f17b8324d4 vexriscv: reset wishbone bus on CPU reset 
If the CPU is resetting during a Wishbone transfer, assert the ERR line.

Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Sean Cross
c87ca4f1c3 vexriscv: put debug bus directly on wishbone bus 
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core.  Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.

Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Florent Kermarrec
8a311bf4a6 build/generic_platform: use list for sources instead of set 
Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
 2018-07-20 10:01:33 +02:00
Florent Kermarrec
df7e5dbcf6 bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup 2018-07-19 12:52:00 +02:00
Florent Kermarrec
1564b440eb soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 2018-07-19 12:51:16 +02:00
Florent Kermarrec
c314193cc9 boards/plarforms/genesys2: replace user_dip_sw with user_sw 2018-07-18 12:48:44 +02:00
Florent Kermarrec
10dd55fd88 boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter 2018-07-18 11:51:58 +02:00
Florent Kermarrec
85308672d3 software/bios/linker: revert data section since required by RISC-V compiler 2018-07-18 09:30:14 +02:00
enjoy-digital
55dd58b023
Merge pull request #80 from xobs/fix-vexriscv-csr-read 
vexriscv_debug: use csr read()/write() accessors
 2018-07-17 17:31:48 +02:00
Sean Cross
41a9e7d9ae vexriscv_debug: use csr read()/write() accessors 
CSR access widths can be different from register widths.  8-bit
registers are common.

The runtime-generated `read()` and `write()` functions handle this
mapping correctly.  When direct register accesses are handled, this
mapping is lost.

Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-17 18:03:58 +08:00
Florent Kermarrec
7ecdcaca4b soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) 2018-07-16 18:40:36 +02:00
Florent Kermarrec
a4caa8964a targets/nexys_video: remove read leveling constants (now automatic) 2018-07-16 09:44:15 +02:00
Florent Kermarrec
d825004173 targets/nexys4ddr: s7ddrphy now supports ddr2, working 2018-07-16 09:43:09 +02:00
Florent Kermarrec
4f1274e6a6 bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) 2018-07-16 09:42:09 +02:00
Florent Kermarrec
7dbd85a842 soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) 2018-07-10 22:32:51 +02:00
Florent Kermarrec
ef1c778446 soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) 2018-07-10 13:29:32 +02:00
Florent Kermarrec
f9104b201a bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) 2018-07-06 19:22:33 +02:00
Florent Kermarrec
c84e189d6a bios/sdram: fix compilation with no write leveling 2018-07-06 16:22:49 +02:00
Sean Cross
be8eb5ff84 vexriscv: debug: fix reading DATA register 
The REFRESH register accepts an 8-bit address and determines which
register to refresh.  Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.

A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.

Replace this check with an explicit check for 0x00.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 18:22:32 +08:00
Sean Cross
6bc9265c2b setup: add vexriscv_debug to list of entrypoints 
Add the vexriscv_debug program to the list of scripts created when
installing this module.  This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 16:22:11 +08:00
Sean Cross
45a649be9b tools: vexriscv_debug: add debug bridge 
Add a bridge that uses litex_server to go from openocd to wishbone.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-06 16:08:06 +08:00
Florent Kermarrec
c821a0feab cores/cpu/vexriscv: create variants: None and "debug", some cleanup 2018-07-05 17:31:23 +02:00
Florent Kermarrec
59fa71593d core/cpu/vexriscv/core: improve indentation 2018-07-05 16:51:40 +02:00
enjoy-digital
6068f6ce9c
Merge pull request #77 from xobs/debug-vexriscv-enjoy 
Enable support for vexriscv debugging
 2018-07-05 16:46:24 +02:00
Florent Kermarrec
11e8491547 platforms/arty_s7: keep up to date with Migen 2018-07-05 12:02:14 +02:00
Sean Cross
32d5a751db soc_core: uart: add a reset line to the UART 
Enable resetting the UART by adding a ResetInserter to the UART.

The UART must be reset when resetting the softcore.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:29 +08:00
Sean Cross
1ef127e06d soc: integration: use the new cpu_debugging flag for vexriscv 
Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:29 +08:00
Sean Cross
e7c762c8c3 soc: vexriscv: add cpu debug support 
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter.  With this enabled, a simple Wishbone interface is provided.

The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.

The debug register at address 4 is used to inject opcodes into the
core, and read back the result.

A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:28 +08:00
Sean Cross
2024542a3c vexriscv: verilog: pull debug-enabled verilog 
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v.  This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.

Sync the litex repo with the upstream version to take advantage of debug
support.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-05 17:25:27 +08:00
Florent Kermarrec
d35dc5cdea platforms/arty: merge with Migen 2018-07-05 11:18:49 +02:00
Florent Kermarrec
fa0215660b platforms/kc705: keep up to date with Migen 2018-07-05 10:43:26 +02:00
Florent Kermarrec
b9f3b49c63 platforms/de0nano: keep up to date with Migen 2018-07-05 10:42:45 +02:00
Florent Kermarrec
df99cc66e8 bios/sdram: also check for last read of scan to choose optimal window 2018-07-02 14:12:27 +02:00
Florent Kermarrec
8ce7fcb237 bios/main: add cpu frequency to banner 2018-07-02 13:47:18 +02:00
Florent Kermarrec
477d224921 bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. 2018-07-02 13:46:48 +02:00
Florent Kermarrec
9e737d3c57 soc/cores/code_8b10b: update (from misoc) 2018-06-29 14:24:44 +02:00
Florent Kermarrec
d58eb4ecb7 bios/sdram: use new phy, improve scan, allow disabling high skew 2018-06-28 18:43:48 +02:00
Florent Kermarrec
692cb14245 software/bios: fix picorv32 boot_helper 2018-06-28 11:42:43 +02:00
Florent Kermarrec
b5ee110e63 bios/sdram: add write/read leveling scans 2018-06-27 15:31:54 +02:00
Florent Kermarrec
34b2bd0c28 boards: add genesys2 (platform with clk/serial/dram/ethernet + target) 2018-06-27 11:27:05 +02:00
Florent Kermarrec
8edc659d7d soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) 2018-06-19 11:15:29 +02:00
Florent Kermarrec
2c13b701f5 soc/integration/cpu_interface: add shadow_base parameter 2018-06-18 18:01:47 +02:00
Sean Cross
7444992999 soc: bios: fix windows build 
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`.  This command does not exist on Windows, and is unnecessary.

Add a conditional guard to prevent this command from running on Windows.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-06-18 17:13:54 +08:00
Florent Kermarrec
18f86881d9 targets: change a7/k7ddrphy imports to s7ddrphy 2018-06-12 15:40:45 +02:00
Florent Kermarrec
3e723d152a soc/cores/cpu: add add_sources static method 
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
 2018-06-12 10:54:20 +02:00
bunnie
7353197e21 fix the vexriscv boot helper 2018-05-31 01:24:22 +08:00
Deano Calver
34a9303448 Fix for missing connectors for arty boards 2018-05-24 21:55:52 +03:00
Florent Kermarrec
e7d1683e34 litex_term: cleanup getkey and revert default settings on KeyboardInterrupt 2018-05-24 08:10:05 +02:00
Florent Kermarrec
6854c7f5fc soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) 2018-05-09 15:39:25 +02:00
Dolu1990
66229c8c05 add VexRiscv support (imported/adapted from misoc) 2018-05-09 15:03:37 +02:00
Florent Kermarrec
f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec
d149f386c9 allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) 2018-05-09 13:26:55 +02:00
Florent Kermarrec
c3652935d9 build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) 2018-05-01 12:02:54 +02:00
Florent Kermarrec
121eaba722 soc/intergration/soc_core: don't delete uart/timer0 interrupts 2018-05-01 00:46:26 +02:00
Florent Kermarrec
39ffa532b0 xilinx/programmer: fix programmer 2018-05-01 00:44:13 +02:00
Florent Kermarrec
c001b8eaf6 build/xilinx/vivado: add vivado ip support 2018-04-12 17:55:46 +02:00
Florent Kermarrec
43f8c230a7 soc_core: uncomment uart interrupt deletion 2018-04-12 17:23:46 +02:00
Florent Kermarrec
d7c7474670 gen/sim: fix import to use litex simulator instead of migen simulator 2018-04-04 15:40:53 +02:00
Florent Kermarrec
b7f7c8d159 build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC" 2018-03-12 09:33:05 +01:00
Florent Kermarrec
4324c6f666 bios/sdram: update kuddrphy initialization procedure 2018-03-08 13:54:30 +01:00
Florent Kermarrec
90dcd45f0b soc/software/main: go to new line at startup 2018-03-07 21:39:10 +01:00
Florent Kermarrec
6706b24167 software/bios/main: add missing space 2018-03-07 15:24:39 +01:00
Florent Kermarrec
2a50a8021a soc/integration/soc_core: improve error message for missing csrs 2018-03-05 09:59:06 +01:00
Tim 'mithro' Ansell
5ef34500f7 Improving error message when csr name is not found. 
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```

Now;
```
Traceback (most recent call last):
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
    return self.csr_map[name]
KeyError: 'ddrphy'

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  ...
  File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
    mapaddr = self.address_map(name, None)
  File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
    ) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.

Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py

Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
 2018-03-03 16:02:44 -08:00
enjoy-digital
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths 
xilinx/vivado: Provide a fallback mechanism for using the same root f…
 2018-03-03 08:29:18 +01:00
enjoy-digital
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial 
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
 2018-03-03 08:28:57 +01:00
William D. Jones
2b00b7eba4 xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. 2018-03-02 21:48:49 -05:00
Florent Kermarrec
fa6b256198 build/xilinx/platform: fix merge 2018-03-03 00:07:50 +01:00
William D. Jones
d40c57739c boards/arty_s7: Fix IOStandard on System Clock. 2018-03-02 13:35:43 -05:00
Florent Kermarrec
0332f73a7b build/xilinx/vivado: revert toolchain_path 2018-02-28 23:45:26 +01:00
Florent Kermarrec
2ff50a8882 build: fix merge 2018-02-28 23:10:24 +01:00
Florent Kermarrec
64e4e1ce84 build: merge with migen.build 27beffe7 2018-02-28 16:49:12 +01:00
Florent Kermarrec
0edfd9b901 boards/kcu105: regroup sfp tx and rx 2018-02-28 14:11:58 +01:00
William D. Jones
e71593d67e platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it 
optional via `add_extension`.
 2018-02-27 18:41:35 -05:00
Florent Kermarrec
1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec
43164b9a2c remove migen fork from litex 2018-02-23 13:37:26 +01:00
Sergiusz Bazanski
688f26cc32 Change AXI interface and tidy code 
Inspired by parts of https://github.com/peteut/migen-misc/
 2018-02-21 00:00:58 +00:00
Sergiusz Bazanski
512ed2b3d6 Preliminary AXI4Lite CSR bridge support 
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.

The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
 2018-02-20 21:27:51 +00:00
enjoy-digital
55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection 
Top module selection (for Verilator and Diamond)
 2018-02-19 12:27:25 +01:00
enjoy-digital
7b5bd4041a
Merge pull request #57 from rohitk-singh/master 
WIP - BIOS: Flashboot without main ram
 2018-02-10 21:37:38 +01:00
Florent Kermarrec
c14502807e board/targets/nexys4ddr: use MT47H64M16 2018-02-06 19:17:54 +01:00
Florent Kermarrec
95ebba428c boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 2018-02-06 19:08:46 +01:00
Florent Kermarrec
ee4fa597b4 boards: add nexys4ddr 2018-02-06 14:43:20 +01:00
enjoy-digital
2ecd1b0666
Merge pull request #61 from PaulSchulz/master 
platform/arty.py: Move Pmod definitions to 'connectors' section.
 2018-01-26 01:58:37 +01:00
William D. Jones
4607e5323f boards/platforms: Add Arty S7 Board. 2018-01-25 18:36:32 -05:00
Paul Schulz
0ac35300c4 Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream 2018-01-24 13:32:42 +10:30
Florent Kermarrec
4f2725809e software/common: revert PYTHON to python3 (since breaking things) 2018-01-23 10:39:13 +01:00
Florent Kermarrec
4e168221d8 bios: fix riscv processor print 2018-01-23 10:33:05 +01:00
Florent Kermarrec
d448874879 sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation) 2018-01-23 10:28:16 +01:00
Paul Schulz
3ac28ed6f7 platform/arty.py: Move Pmod definitions to 'connectors' section. 2018-01-23 16:11:25 +10:30
Sergiusz Bazanski
ef511e7edc Specify top-level module in Lattice Diemond build script. 
When building multi-source files the toolchain gets confused as to which
module is top-level. This ensures that the build_name of the design is
selected.
 2018-01-23 01:17:04 +00:00