Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity
2180 commits 9 branches 14 tags 12 MiB
Commit graph

944 commits

Author SHA1 Message Date
Sergey Anufrienko
ce951589d1 improve terasic_de2_115 target support 2023-10-23 21:15:00 +03:00
enjoy-digital
41351a845a
Merge pull request #526 from Chandler-Kluser/master 
Added QMTECH RP2040 Daughterboard
 2023-10-23 11:23:44 +02:00
Gwenhael Goavec-Merou
5f694166ce platforms/sipeed_tang_primer_25k: swap UART TX & RX, fix TX pin (J1:20 -> J1:21) 2023-10-19 06:26:10 +02:00
Gwenhael Goavec-Merou
9ae224a2a7 sipeed_tang_primer_25k: new board 2023-10-17 07:45:40 +02:00
rniwase
842819d832 platforms/xilinx_zcu102: Add pin definitions for DDR4 SDRAM and FMC connectors. 2023-10-13 23:53:10 +09:00
Florent Kermarrec
371234b369 platforms/analog_pocket: Add Video Scaler pins definitions and output_term/current strength on SDRAM pins. 
From https://github.com/tpwrules/pocket_linux.
 2023-10-09 10:12:38 +02:00
Florent Kermarrec
149ed9630c platforms/ocp_tap_timecard: Add with_multiboot parameter to enable/disable multiboot images generation. 
Generating multiboot images is not very fast, disabling it for quick P&R iterations can be useful.
 2023-10-03 19:03:42 +02:00
Gwenhael Goavec-Merou
aa853d5a48 platforms/efinix_trion_t20_bga256_dev_kit: CON4 cleanup 2023-10-02 19:19:50 +02:00
Gwenhael Goavec-Merou
bc6f6d869e platforms/efinix_trion_t20_bga256_dev_kit: CON3 (LVDS RX) / CON4 (LVDS TX) 2023-10-02 18:51:53 +02:00
Liana Koleva
6f0cd56109
update to match zcu102 constraint spec 2023-09-28 11:11:21 +02:00
Florent Kermarrec
928c1a2539 platforms/sipeed_tang_mega_138k: Fix default_clk_name/period. 2023-09-26 21:07:21 +02:00
enjoy-digital
29018a8382
Merge pull request #523 from Icenowy/tangmega138k 
[RFC] sipeed_tang_mega_138k: new board
 2023-09-26 19:12:44 +02:00
Liana Koleva
5f8ac853b1
Resolve High Density bank IOStandard error 
This resolves the following error during `build` on Vivado 2023.1:
```ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 47 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
clk125_p```
 2023-09-25 12:50:30 +02:00
Florent Kermarrec
1fb317840f platforms/ocp_tap_timecard: Add clk10 and som_led. 2023-09-22 08:33:04 +02:00
Florent Kermarrec
c14d66cb6b analog_pocket: Add Serial (to fix CI) and add to board list. 2023-09-21 10:11:55 +02:00
Florent Kermarrec
3df677cfeb Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART. 
$ ./analog_pocket.py --uart-name=jtag_uart --build --load
$ litex_term jtag --jtag-config=openocd_usb_blaster.cfg

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 21 2023 08:53:57
 BIOS CRC passed (1e2b3f44)

 LiteX git sha1: 7d738737

--=============== SoC ==================--
CPU:		VexRiscv @ 50MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB
L2:		8.0KiB
SDRAM:		64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM:	64.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 15.6MiB/s
   Read speed: 22.1MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2023-09-21 09:19:57 +02:00
Florent Kermarrec
a0b7811c54 platforms/ti60_f225: Add n parameter to rgmii_ethernet_qse_ios to allow having multiple adapters. 2023-09-11 10:45:28 +02:00
Chandler Klüser
c26f76e8cb Fixed misplacement of platform file 2023-09-03 15:49:38 -03:00
Chandler Klüser
632bab937e
Update qmtech_artix7_fgg676.py 2023-09-01 05:03:44 -03:00
Chandler Klüser
d8b006568a
Update qmtech_artix7_fgg676.py 2023-09-01 04:53:07 -03:00
Florent Kermarrec
b92c96b3a4 colorlight_i9plus: Cosmetic cleanups. 2023-08-30 17:22:11 +02:00
enjoy-digital
3471617878
Merge pull request #502 from chmousset/add_colorlight_i9plus 
[init] added colorlight i9+ based on XC7A50 FPGA
 2023-08-30 16:54:26 +02:00
enjoy-digital
4862d0667c
Merge pull request #515 from josuah/crosslink_nx_openocd 
Allow use of OpenOCD for the Crosslink-NX
 2023-08-28 16:35:20 +02:00
Florent Kermarrec
5799c35247 platforms/gsd_orangecrab: Set alt point to DFUProg. 2023-08-28 16:28:04 +02:00
Icenowy Zheng
ebfb9b8e01 sipeed_tang_mega_138k: new board 
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-08-15 16:33:13 +08:00
Josuah Demangeon
8172a304b3 platforms/crosslink_nx_evn: allow use of OpenOCD 2023-08-08 23:25:41 +02:00
enjoy-digital
3903cdee92
Merge pull request #517 from bayi/master 
Digilent CMOD A7 ISSIRAM fix
 2023-08-08 19:29:32 +02:00
Bayi
a6b025f7f3
Fix Digilent Cmod A7 ISSIRAM reading 2023-08-05 19:56:15 +02:00
Josuah Demangeon
5412d0e0e9 platforms/crosslink_nx_evn: allow use of UARTBone 
This goes along a small resistor jumper modification and firmware flashing like
it is for the ECP5 board. A warning message is added as the default serial might
be affected (--serial serial by default). The FTDI modification software used
for the ECP5 seems to be requried and matching.

This can be tested this way:
targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load
litex_server --uart --uart-port /dev/ttyUSB1
litex_cli --regs
 2023-08-04 20:47:32 +02:00
Florent Kermarrec
efc15a91a9 global: Use new WaitTimer integrated cast to int. 2023-08-01 14:56:35 +02:00
Florent Kermarrec
ace789653f platforms/ti60_f225: Add connector numbering to ease review/schematic comparison. 2023-07-21 09:08:22 +02:00
Florent Kermarrec
72a951081a xu8_pe3: Fix clk_p/n on pcie_x8. 2023-07-13 18:10:46 +02:00
Florent Kermarrec
18a3909a9c global: Switch to litex.gen.genlib.misc. 2023-07-06 22:11:45 +02:00
Mark1626
e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu 2023-06-27 21:35:55 +05:30
Mark1626
061a768495
Add Alchitry Cu board 2023-06-16 21:36:57 +05:30
Florent Kermarrec
c49a50a934 platform/gsd_butterstick: Add mssing USB comment. 2023-06-16 09:10:47 +02:00
Florent Kermarrec
28ecb1e9f3 enclustra_mercury_xu8_pe3: Fix pcie_x8 and add GTH banks for pcie_x4/x8. 2023-06-15 17:57:38 +02:00
Florent Kermarrec
06e8829eb4 platforms/gsd_butterstick: Add default programmer to avoid breaking older designs. 2023-06-14 16:40:35 +02:00
Florent Kermarrec
96175a9986 sitlinv_stlv7325_v2: Add default value to vccio. 2023-06-07 15:00:49 +02:00
Hans Baier
765ee1a3ce sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V 2023-06-07 10:12:55 +07:00
Gabriel Somlo
b01abce7d5 platform/stlv7325-v2: update VCCIO to fix --with-pcie generation 2023-06-01 16:45:33 -04:00
enjoy-digital
7fc8ca9816
Merge pull request #506 from sensille/rv901t-spiflash 
Add spiflash definition to linsn_rv901t board
 2023-05-30 22:36:14 +02:00
Florent Kermarrec
8a263c18f2 sitlinv_stlv7325: Rename to v1 and update VCCIO to fix --with-pcie generation. 2023-05-30 10:39:20 +02:00
Arne Jansen
4a05e56058 Add spiflash definition to linsn_rv901t board 2023-05-27 16:20:32 +02:00
Chen
2ae2dfa6a3
Add vcu128 target (#497) 
Add initial VCU128 support.
 2023-05-25 22:25:44 +02:00
Florent Kermarrec
9362e589ac Add initial Enclustra XU8/PE3 platform definition with Clk/I2C/PCIe/DDR4 and FMC connector definition. 2023-05-25 10:01:19 +02:00
Hans Baier
550bc0eee5 add QMTech XC7K325T board, add seven segment display to daughterboard 2023-05-08 11:51:51 +07:00
Hans Baier
187080228c add qmtech_xc7l325t 2023-05-08 05:17:35 +07:00
Florent Kermarrec
d33cf1a74c mnt_rkx7: Cosmetic cleanups. 2023-05-05 09:48:06 +02:00
enjoy-digital
6144966d24
Merge pull request #501 from mntmn/master 
mnt_rkx7: RGB and USB fix, add HDMI terminal
 2023-05-05 09:37:40 +02:00
Charles-Henri Mousset
31c680abf8
[enh] added option for uartbone 2023-04-30 09:42:31 +02:00
Charles-Henri Mousset
874532871f
[enh] taking advantage of pins directly connected 2023-04-30 09:24:49 +02:00
Charles-Henri Mousset
1202c387bf
[init] added colorlight i5a-907 support 2023-04-30 09:24:46 +02:00
Charles-Henri Mousset
322cc5d45b
[init] added colorlight i9+ based on XC7A50 FPGA 2023-04-29 18:36:35 +02:00
Gabriel Somlo
1185ff51f1 Initial support for STLV7325 (v2) Kintex-7 board. 
This is the 2nd (2023) version of the board sold through
https://www.aliexpress.us/item/3256801088848039.html

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2023-04-28 10:24:21 -04:00
Lukas F. Hartmann
a9e3e3c050 Merge branch 'master' of https://github.com/litex-hub/litex-boards 2023-04-25 20:29:11 +02:00
Lukas F. Hartmann
d160a5ad5d mnt_rkx7: swap RGB red/blue channels 2023-04-25 20:28:16 +02:00
594rk
03913e2e15
Update terasic_de10nano.py 
Corrected pin number
 2023-04-23 22:28:00 -05:00
enjoy-digital
b8cb2eaa47
Merge pull request #493 from hansfbaier/deca-ddr3 
make DDR3 memory work on the DECA with the UniPHY
 2023-04-11 15:27:02 +02:00
Hans Baier
60ac45e80c make DDR3 memory work on the DECA with the UniPHY 2023-04-11 19:59:49 +07:00
Hans Baier
e120b77ef0 enclustra kx2/st1: fix connectors 2023-04-11 10:58:52 +07:00
Hans Baier
c7077880b9 copyright notices on enclustra 2023-04-11 10:29:52 +07:00
Hans Baier
ed947d1b55 enclustra: add baseboard ST1 2023-04-11 10:29:44 +07:00
Hans Baier
be8ee26b2c enclustra_mercury_kx2: Add ST1 baseboard, part 1 2023-04-11 05:39:11 +07:00
Hans Baier
58679262ad enclustra kx2: add connectors 2023-04-10 14:06:42 +07:00
enjoy-digital
a8eb0b20c1
Merge pull request #491 from hansfbaier/stlv7325-hdmi 
STL7325: Add Video, and connectors (FMC, BTB, 2.54mm)
 2023-04-07 09:06:55 +02:00
Hans Baier
52ca60c2ac stlv7325: fix HDMI io standard 2023-04-07 09:50:04 +07:00
Hans Baier
2f13decc49 stlv7325: make VCCIO configurable 2023-04-07 09:27:03 +07:00
Hans Baier
abd639ba9e stlv7325: add 2.54mm headers 2023-04-07 08:21:17 +07:00
Hans Baier
3f85e4ae62 stlv7325: add BTB connectors 2023-04-07 08:09:27 +07:00
Hans Baier
b3e44324d1 sitlinv_stlv7325: add FMC connector 2023-04-07 07:56:27 +07:00
Hans Baier
5067a2683f sitlinv_stlv7325: add video HDMI, enable compressed bitstream 2023-04-07 07:31:42 +07:00
Hans Baier
43ce24dcb3 add QMTech 5CEFA5 Cyclone V board support 2023-04-06 18:27:51 +07:00
Florent Kermarrec
ae3d5d599b sqrl_fk33: Remove es1 workaround now that recent version of Vivado support it non-es devices. 2023-04-04 18:11:38 +02:00
enjoy-digital
e11d40a249
Merge pull request #487 from ICE-V-Wireless/master 
Add PMOD registrations to ICE-V Wireless
 2023-04-02 11:44:02 +02:00
Michael Welling
5de47baa44 Add PMOD registrations to ICE-V Wireless 
Signed-off-by: Michael Welling <mwelling@ieee.org>
 2023-04-02 03:31:55 -05:00
Hans Baier
f564f80826 terasic_deca: hdmi i2s uses 1.8V, not 3.3V 2023-04-01 08:14:09 +07:00
Hans Baier
74c8569a5c DDR3 RAM works on 1.5V, not 1.35V 2023-03-27 15:17:42 +07:00
Hans Baier
40c8e62b09 use bistream compression on those large devices 2023-03-21 09:25:56 +07:00
Hans Baier
0125ae4271 Add support for QMTech Artix7 200T FBG484 board 2023-03-20 08:21:36 +07:00
Hans Baier
98ddb97f5e Support QMTech XC7A75T, XC7A100T core boards 2023-03-20 07:57:58 +07:00
Icenowy Zheng
6b8a5d35c0 sipeed_tang_nano_20k: support copackaged SDRAM 
The copackaged SDRAM of GW2AR-18 QN88 package is 8MB size, 32bit DQ
width.

Add support for it.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-03-13 17:11:06 +08:00
Icenowy Zheng
291c43b898 sipeed_tang_nano_20k: new board 
This board uses Gowin GW2AR series chip (which is GW2A with integrated
RAM).

Support for the integrated SDRAM on Tang Nano 20K is still TODO.

Note: currently when the SD card is enabled, block 0 could be correctly
read but block 1 will fail.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-03-13 16:45:25 +08:00
Marco
28a1aefc21
Update sipeed_tang_nano_9k.py 
add pin info for _connectors
 2023-03-09 17:57:39 +01:00
Florent Kermarrec
1df46d1571 platforms/sipeed_tang_nano_9k: Review SPI RGB LCD addition. 2023-03-06 09:03:12 +01:00
Marco
8d35591f47
Update sipeed_tang_nano_9k.py 
add SPI-Interface for the 1.14inch LCD
 2023-03-04 15:25:59 +01:00
Florent Kermarrec
943cf2636f platforms/sipeed_tang_primer_20k: Add checkme on leds IOstandard. 2023-03-02 12:14:04 +01:00
Florent Kermarrec
9e73ba53ea platforms/sipeed_tang_primer_20k: Update hdmi pins to official dock version and fix compilation. 
Test:
./sipeed_tang_primer_20k.py --cpu-type=serv --with-video-terminal --build --load

Working.
 2023-03-02 11:39:41 +01:00
Florent Kermarrec
47659835b0 platforms: Switch US/USP platforms to XilinxUS/USPPlatform. 
We were still using Xilinx7SeriesPlatform.
 2023-03-01 09:37:55 +01:00
Florent Kermarrec
8a6f0bd94f opalkelly_xem8320: Review and update to recent LiteX changes. 2023-03-01 09:16:51 +01:00
AEW2015
e20391d366 Basic SoC for Opal Kelly XEM8320 2023-02-28 13:19:12 -07:00
inc
33cfe59614 add pullups for kopflos ethernet 2023-02-22 08:00:58 +01:00
inc
bd20b31a5c add support for machdyne kopflos board 2023-02-21 11:18:22 +01:00
Michael Welling
b1df2c0f85 Add initial support for the ICE-V wireless 
Signed-off-by: Michael Welling <mwelling@ieee.org>
 2023-02-19 00:00:07 -06:00
Florent Kermarrec
7b716e4899 antmicro_sdi_mipi_video_converter: Cleanup/Update to new LiteX conventions. 2023-02-16 09:02:14 +01:00
enjoy-digital
fe2be83feb
Merge pull request #473 from antmicro/crosslink-nx-zephyr 
Add support for SDI-MIPI Video Converter
 2023-02-16 08:49:04 +01:00
Florent Kermarrec
857166e455 xilinx_alveo_u200: Add missing copyrights. 2023-02-16 08:45:34 +01:00
enjoy-digital
adf8b8c5df
Merge pull request #472 from vietthanh85/xilinx_alveo_u200 
Add support for Xilinx Alveo U200
 2023-02-16 08:42:21 +01:00
Antoni Pokusinski
31d718749a Add copyrights 2023-02-15 12:37:33 +01:00
Antoni Pokusinski
70f2fd6368 Fix format 2023-02-15 12:37:33 +01:00
Antoni Pokusinski
0c774a906d Add clk12 to platform 2023-02-15 12:37:33 +01:00
Tomasz Michalak
223a69cf91 Add platform and target files for Antmicro's sdi mipi video converter board 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2023-02-15 12:37:33 +01:00
Do Viet Thanh
ec7a5c4c0b Correct DDR4 IO Banks of Xilinx Alveo U200 2023-02-14 06:40:12 +07:00
Florent Kermarrec
fdffeb8474 radiona_ulx4m_ld_v2: Do a first review/cleanup path. 2023-02-13 16:11:32 +01:00
Goran Mahovlic
99db2ae60d
Delete ulx4m_ld_v2.py 2023-02-13 11:48:51 +01:00
Goran Mahovlic
57c9cff39e
Update radiona_ulx4m_ld_v2.py 2023-02-13 11:45:48 +01:00
Goran Mahovlic
9320ae8b74
Fixing platform file 2023-02-13 11:44:59 +01:00
Goran Mahovlic
a3815efccb
Adding radiona ULX4M-LD-V2 2023-02-11 16:57:34 +01:00
MV
a354f04143 avoid undefined clocks by moving the derive*-statements to start of the additional constraints list 2023-02-09 15:58:41 +01:00
Florent Kermarrec
b9874685a5 gadgetfactory_papilio_pro: Cosmetic cleanups. 2023-01-17 15:43:12 +01:00
enjoy-digital
ec4d203eb6
Merge pull request #471 from Acathla-fr/papilio 
Target/Platform Papilio Pro added (with Arcade MegaWing)
 2023-01-17 11:21:27 +01:00
enjoy-digital
801008f5ad
Merge pull request #469 from hansfbaier/hpcstore-rename 
HPC FPGA Store on AliExpress renamed itself to SITLINV
 2023-01-17 11:20:19 +01:00
Do Viet Thanh
3b36e576ba Add support for Xilinx Alveo U200 2023-01-17 06:44:21 +07:00
Fabien
05ef1ee09e Target/Platform Papilio Pro added (with Arcade MegaWing) 2023-01-16 13:41:24 +01:00
Florent Kermarrec
55fcb4cd47 xilinx_alveo_u2x0: Improve indentation on DRAMs. 2023-01-16 09:34:59 +01:00
Florent Kermarrec
be77f82720 platforms/xilinx_alveo_u250: Fix dram numbering. 2023-01-16 09:31:23 +01:00
Florent Kermarrec
e02f64a7db platforms/gsd_butterstick: Fix copyright. 2023-01-16 08:41:10 +01:00
Greg Davill
59a897e2dd
gsd_butterstick: Add missing pin defs 2023-01-16 17:32:39 +10:30
Hans Baier
c0773ed9b9 HPC FPGA Store on AliExpress renamed itself to SITLINV 2023-01-16 11:31:35 +07:00
Florent Kermarrec
36a4100c8b ocp_timecard: Add DDR3 SDRAM support. 2023-01-13 12:41:34 +01:00
Florent Kermarrec
1e35d78512 ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers. 2023-01-13 10:08:44 +01:00
Florent Kermarrec
fc7154a632 ocp_tap_timecard: Add Leds/I2C/PMOD/GPS/SMAs IOs. 2023-01-13 09:14:05 +01:00
Florent Kermarrec
a0fd3e7536 Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested). 2023-01-12 18:50:23 +01:00
enjoy-digital
563ccbd8cf
Merge pull request #464 from machdyne/master 
initial support for machdyne konfekt and noir
 2023-01-01 16:12:51 +01:00
enjoy-digital
5de6865cbe
Merge pull request #463 from stone3311/master 
terasic_deca: add SPI SD card support
 2023-01-01 16:10:30 +01:00
inc
f0dc9a6874 initial support for machdyne konfekt and noir 2022-12-30 17:00:35 +01:00
stone3311
6cfb56bb07 terasic_deca: add SPI SD card support 2022-12-28 02:13:06 +01:00
jiv4ik
57845d1ca4
Correct pinout and IOStandard 
Correct connector pinout
Correct pinout for ETH
LED IOStandard set to LVCMOS33
BTN[0] IOStandard set to LVCMOS33
Changes are made based on Tang_primer_20K_3690 and Tang_Primer_20K-Dock_3709 schemes.
 2022-12-22 18:30:36 +03:00
Gwenhael Goavec-Merou
a92fdffb35 platforms/digilent_zybo_z7: reorder _io_x & _connectors_x, init cleanup 2022-12-12 22:17:39 +01:00
JoyBed
d28894a4b3
Reintroduce original Zybo + HDMI addition (#461) 
* Reintroduce original Zybo support

* Reintroduce original zybo, add HDMI + fixes for Z7
 2022-12-12 22:05:47 +01:00
enjoy-digital
c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config 
Arty z7 tcl config
 2022-12-08 08:31:22 +01:00
Guilherme Salustiano
25c40ddda7 add gpio to board 2022-12-05 21:38:56 -03:00
Gwenhael Goavec-Merou
e71e3ab3ec platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration 2022-12-03 16:54:39 +01:00
Guilherme Salustiano
d0d90e9eef
Merge branch 'litex-hub:master' into master 2022-11-29 15:25:41 -03:00
mkuhn99
926ed21f0b fixed review remarks; added zynq7000 as a submodule for using the ps as a slave 2022-11-23 17:20:25 +01:00
Guilherme Salustiano
570ea11744
fix(plataform.basys_3): V_sync is pin R19 
Based in https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#LL129C34-L129C37
 2022-11-23 09:16:50 -03:00
mkuhn99
6f7716adbb added config for ps7; introduced different variants for the zybo-board; fixed pins 2022-11-18 11:15:54 +01:00
Florent Kermarrec
6e10df234f platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau). 2022-11-14 10:21:37 +01:00
Icenowy Zheng
3d8106f84d stlv7325: fix Ethernet IO voltages 
The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.

Fix this in the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng
4ba5793822 sitlinv_stlv7325: remove unexistent COL/CRS pins 
The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.

Remove these pins from the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Gwenhael Goavec-Merou
24cd983b8c platforms/alinx_axu2cga: adding missing psu_config at platform level 2022-11-06 21:52:00 +01:00
Gwenhael Goavec-Merou
9960f38d95 targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser 2022-11-06 11:27:47 +01:00
Icenowy Zheng
d7184fb043 stlv7325, a_e115fb: use the proper vendor name Sitlinv 
The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.

Use this vendor name instead of where it's bought.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-10-30 10:51:13 +08:00
enjoy-digital
6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name 
platforms/nexys4*: Update part name
 2022-10-27 12:11:07 +02:00
Chema
125569b2cb add FPGAWars Alhambra II 2022-10-25 21:12:02 +02:00
enjoy-digital
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283 
Add ISX iM1283 board
 2022-10-22 15:56:43 +02:00
Shawn Anastasio
d4b2461b5a platforms/nexys4*: Update part name 
Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
 2022-10-21 14:15:27 -05:00
Florent Kermarrec
377cda05a3 ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity. 
Will need to be investigated more.
 2022-10-20 18:21:52 +02:00
Icenowy Zheng
745ebbbfa1 Add ISX iM1283 board 
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.

This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-10-14 22:50:43 +08:00
Florent Kermarrec
23c6acd013 platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks. 
Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.

Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+   table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
 2022-10-14 10:22:54 +02:00