a9cbc48eb2
PcManagerPlugin is can now handle an external reset vector signal
2018-04-24 23:11:11 +02:00
978eb9b6b2
DBusCachedPlugin add CSR info
2018-04-22 11:46:01 +02:00
74f2a4194a
Add ExternalInterruptArrayPlugin
2018-04-20 17:56:21 +02:00
6598e82920
wishbone => word address, not byte address
2018-04-19 11:22:06 +02:00
455607b6b4
Fix dBus IO access
2018-04-18 14:11:59 +02:00
6e59ddcc73
Cached wishbone demo is passing regression tests
2018-04-18 13:51:33 +02:00
b37fc3fcc8
Add VexRiscv Wishbone demo for sim (generation ok)
2018-04-18 12:54:20 +02:00
a66efcb35b
Add wishbone support for i$ / d$ (not tested)
2018-04-17 23:56:44 +02:00
4440047fb6
ICache compressed is working
2018-04-16 10:34:18 +02:00
76352b44fa
wip
2018-04-13 12:51:27 +02:00
19d5d1ecf1
wip
2018-04-09 09:18:08 +02:00
4dd2997ad5
wip
2018-04-09 09:12:30 +02:00
e00c0750eb
wip
2018-04-03 18:37:05 +02:00
d9f2e03753
statuc prediction is fully funcitonnal
2018-04-02 17:43:58 +02:00
76ca852478
Static prediction is fully functionnal
2018-04-02 17:43:06 +02:00
0919308a8f
IBusSimplePlugin add relaxedPcCalculation
2018-03-23 22:49:32 +01:00
c48c7170e8
Added many pipelining option into IBusSimplePlugin
2018-03-23 19:07:03 +01:00
0c7c2a1fba
IBusPlugin add support of bus error when using compressed instruction
2018-03-21 22:34:54 +01:00
31a464ffdc
VexRiscv now pass Riscv-test compressed stuff
2018-03-21 20:50:07 +01:00
af638e7bde
RV32IC is passing some of the compressed Riscv-test tests
2018-03-21 20:30:09 +01:00
f872d599e2
Add decodePcGen
2018-03-20 18:34:36 +01:00
1fb138de1f
IBusSimplePlugin fully functional Need to restore branch prediction
2018-03-20 00:01:28 +01:00
ac74fb9ce8
iBusSimplePlugin done, DebugPlugin need minor rework
2018-03-18 13:21:21 +01:00
64022557bf
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl
2018-03-15 18:56:25 +01:00
63c1b738ff
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings
2018-03-14 00:56:23 +01:00
d9b7426cde
undo InOutWrapper from Murax
2018-03-14 00:47:23 +01:00
91031f8d75
DivPlugin is now based MulDivIterativePlugin (Smaller)
2018-03-10 13:31:35 +01:00
e437a1d44e
Add division support in the MulDivInterativePlugin
2018-03-09 22:41:47 +01:00
36438bd306
iterative mul improvments
2018-03-09 20:00:50 +01:00
674ab2c594
experimental iterative mul/div combo
2018-03-09 19:07:26 +01:00
53970dd284
SpinalHDL 1.1.4
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Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
2018-03-05 14:34:59 +01:00
ccad64def5
Pipeline CSR isWrite
2018-02-26 10:19:33 +01:00
2b6185b063
Decoding logic : Add primes duplication removal
2018-02-25 08:57:31 +01:00
2b6f43cef8
Fix Murax memory mapping range
2018-02-25 08:57:31 +01:00
5260ad5c35
Decoding lib cleaning
2018-02-25 08:57:31 +01:00
d957934949
Fix ICache exception priority over miss reload
2018-02-19 22:44:46 +01:00
d0e963559a
Update readme with the new ICache implementation
2018-02-18 23:48:11 +01:00
93110d3b95
Add jump priority managment in PcPlugins
2018-02-16 14:27:20 +01:00
506e0e3f60
New faster/smaller/multi way instruction cache design.
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Single or dual stage
2018-02-16 02:21:08 +01:00
3853e0313b
SynthesisBench cleaning/experiments
2018-02-11 14:53:42 +01:00
0e6ae682b1
Add architecture section describing plugins in the readme
2018-02-09 00:44:27 +01:00
57ebfee2e6
Add more axi bridges
2018-02-08 21:39:22 +01:00
d4b05ea365
Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
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Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
2018-02-05 16:16:27 +01:00
4729e46763
Add DummyFencePlugin
2018-02-03 12:28:53 +01:00
f13dba847c
Add custom csr gpio example
2018-02-02 11:14:55 +01:00
b7d8ed8a81
Add onWrite/onRead/isWriting/isReading on the CsrPlugin
2018-02-01 21:28:28 +01:00
d2e5755df4
revert removed code by mistake
2018-01-31 18:29:30 +01:00
30b05eaf96
Add CsrInterface to allow custom CSR addition
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Add CustomCsrDemoPlugin as a show case
2018-01-31 18:13:42 +01:00
bdbf6ecf17
BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
2018-01-29 14:52:31 +01:00
0d318ab6b9
Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
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Add longer timeouts in the regressions tests
2018-01-29 13:17:11 +01:00
307c0b6bfa
Now mret and ebreak are only allowed in CSR machine mode
2018-01-28 16:34:55 +01:00
26732942e5
Update DMIPS/Mhz
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Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
2018-01-25 01:11:57 +01:00
3b3bbd48b9
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
2018-01-20 18:29:33 +01:00
9a89573942
SpinalHDL 1.1.2
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Add Murax setup with Mul Div Barriel
2018-01-06 22:09:42 +01:00
43d3ffd685
CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
2018-01-04 17:37:23 +01:00
611f2f487f
Fix DataCache atomic integration into DBusCachedPlugin
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Atomic is passing basic tests
2018-01-04 15:24:00 +01:00
4637e6cb48
Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode.
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add Atomic test flow
2018-01-04 14:43:30 +01:00
468dd3841e
Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer
2018-01-04 13:16:40 +01:00
ebda7526b5
MuraxSim 1.0.0
2017-12-17 17:57:09 +01:00
e1b86ea511
SpinalHDL 0.11.4 update
2017-12-01 11:19:23 +01:00
586d3ed286
Update formal VexRiscv to halt on missaligned dbus
2017-11-26 15:30:48 +01:00
4de0aac469
Merge branch 'formal'
2017-11-24 14:03:25 +01:00
b7f4f09814
Update verilator makefiles to support the last SpinalHDL changes (process merges)
2017-11-21 23:56:46 +01:00
9b9bbaa4ad
Add missing full config for the iBus
2017-11-21 00:09:02 +01:00
ce6fd6d0aa
Add VexRiscvAxi4 demo
2017-11-20 23:57:37 +01:00
7c19288648
Update Synthesis bench
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Update some synthesis results
2017-11-17 20:10:46 +01:00
290dbc106e
Fixes GPIO width mismatch
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Adds explicit type to apbDecoder.slave to suppress IDE errors
2017-11-16 15:02:13 -05:00
6c3fed3505
SpinalHDL 0.11.1
2017-11-15 16:44:42 +01:00
be3d301eaf
Merge remote-tracking branch 'origin/spinalhdl_reworkDev'
2017-11-12 13:08:05 +01:00
838c13d68b
spinal.core.internals literals import
2017-11-10 13:14:30 +01:00
3060296b94
unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch
2017-11-10 11:33:04 +01:00
c3a7f4e58c
CSR unsetRegIfNoAssignement fix
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BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
2017-11-10 00:59:31 +01:00
d6777ae8ec
usetRegIfNoAssign upgrade
2017-11-09 20:10:56 +01:00
a72c7fd0d1
Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala
2017-11-07 22:19:33 +01:00
714d44d248
Add fixed bug into the FormalPlugin comments
2017-11-07 13:54:07 +01:00
200a73bea0
Fix FormalPlugin to pass liveness again.
2017-11-06 23:04:33 +01:00
8098a03a9b
with no bus stall, pass all tests except uniqueness
2017-11-06 20:26:45 +01:00
e2a432eb5e
add HaltOnExceptionPlugin
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wip
2017-11-05 20:13:27 +01:00
276f7895e7
Add FormalPlugin
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Add FormalSimple CPU configuration
2017-11-04 00:55:32 +01:00
ba42f71813
pass VexRiscv regressions
2017-10-30 14:29:25 +01:00
2bf7ca24f2
Add VexRiscvAvalonWithIntegratedJtag
2017-10-16 11:52:17 +02:00
09ba7c28da
Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)
2017-08-27 15:21:44 +02:00
8168c9bf3a
Update simd_add makefile
2017-08-27 14:49:36 +02:00
2c6889e688
Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU
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Murax add dhrystone config
2017-08-10 22:48:00 +02:00
aa477b2b1c
DebugPlugin now prevent the CPU catching exception when debug instruction are pushed
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Fix DataCache locking when loading mem read rsp transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
2017-08-10 20:56:54 +02:00
1653548140
Better readme about custum instruction testing
2017-08-08 18:36:23 +02:00
54b06e6438
Add SIMD_ADD regression and config (show case)
2017-08-08 18:19:02 +02:00
3307d6c3b5
Briey move CPU and UART generics from to toplevel to the toplevel configuration object
2017-08-06 15:42:37 +02:00
671aa5050e
Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)
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Add MuraxConfig.fast
2017-08-04 14:55:54 +02:00
ac59eebb8d
Add Murax configuration which integrate a boot programme :
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Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
2017-08-03 21:58:23 +02:00
58981c0e8e
Add Murax fast in synthesis bench
2017-08-01 21:14:09 +02:00
0c9a39d3ce
Connect the UART interruption to the CPU
2017-07-31 17:20:47 +02:00
c16a53c388
Refractoring of some arbitration signals
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Add UART into Murax
2017-07-31 13:34:25 +02:00
8708d2482f
Add more information about dependencies
2017-07-30 11:37:22 +02:00
de33128e01
Add Murax 0.55 DMIPS/Mhz
2017-07-30 02:42:14 +02:00
e8aa828744
PcPlugin change fastPcCalculation into relaxedPcCalculation
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relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
2017-07-29 21:36:30 +02:00
3b66d986a8
Fix cpu sending instruction memory request while being halted by the DebugPlugin
2017-07-29 18:20:22 +02:00
43253f61c1
Update Murax info
2017-07-29 02:52:57 +02:00
fa887d3830
Add pipelining option (hit 60 Mhz)
2017-07-29 02:52:03 +02:00
3bdf020c67
Add interrupts and timer to Murax
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8KB ram is the default now
2017-07-29 01:59:17 +02:00
Dolu1990
Tony Kao
Charles Papon