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Author SHA1 Message Date
Florent Kermarrec
5a9afee234 fhdl/specials/memory: use $readmemh to initialize memories 2015-03-18 15:27:01 +01:00
Florent Kermarrec
c0fb0ef600 fhdl/verilog: change the way we initialize reg: reg name = init_value; 
This allows simplifications (init in _printsync and _printinit no longer needed)
 2015-03-18 15:05:26 +01:00
Florent Kermarrec
ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" 
This probably breaks simulation with Icarus Verilog (and others simulators?)
 2015-03-18 14:59:22 +01:00
Florent Kermarrec
2fc2f8a6c0 migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb) 2015-03-18 14:41:43 +01:00
Sebastien Bourdeauducq
bdc47b205a Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)" 
This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e453.
 2015-03-18 12:08:25 +01:00
Florent Kermarrec
89fefef3f8 genlib/io: add optional external rst to CRG 2015-03-17 16:22:22 +01:00
Florent Kermarrec
b7d7fe1a4c fhdl/special: add optional synthesis directive (needed by Synplify Pro) 2015-03-17 14:59:05 +01:00
Florent Kermarrec
9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code 
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
 2015-03-17 00:40:26 +01:00
Florent Kermarrec
e946f6e453 fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) 2015-03-16 23:47:07 +01:00
Florent Kermarrec
69ce6dd48c migen/genlib/io: add DDRInput and DDROutput 2015-03-16 22:47:13 +01:00
Sebastien Bourdeauducq
beeaefccea move pytholite to separate repos 2015-03-14 22:48:03 +01:00
Sebastien Bourdeauducq
c824379878 fhdl/visit: fix TransformModule 2015-03-14 17:45:11 +01:00
Sebastien Bourdeauducq
6a979a8023 mibuild: sanitize default clock management 2015-03-14 00:10:08 +01:00
Florent Kermarrec
ff266bc2ee migen/genlib/io: add DifferentialOutput and Xilinx implementation 2015-03-12 19:30:57 +01:00
Florent Kermarrec
bf28664cb4 genlib/io.py: fix copy/paste error (thanks rjo) 2015-03-12 18:49:49 +01:00
Florent Kermarrec
c8ba8cde8e migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild 2015-03-12 18:38:53 +01:00
Florent Kermarrec
8e09a86e4f genlib/misc: add increment parameter to Counter 2015-03-09 20:20:25 +01:00
Florent Kermarrec
ebcea3c000 fhdl/module: use r.append() in _collect_submodules 2015-03-09 19:45:02 +01:00
Florent Kermarrec
ee1091f491 fhdl/module: avoid flushing self._submodules and create do_exit. 2015-03-09 17:17:21 +01:00
Sebastien Bourdeauducq
7b00141a0c genlib/cordic: fix typos 2015-03-06 00:47:23 +01:00
Florent Kermarrec
06f3c46e35 genlib/misc: fix missing *args in Counter 2015-03-04 23:49:15 +01:00
Florent Kermarrec
7d68ecbd86 move dma_lasmi to MiSoC 2015-03-02 08:23:02 +01:00
Florent Kermarrec
58290f3c43 lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks) 2015-03-01 22:04:20 +01:00
Florent Kermarrec
8f81ae6826 genlib/misc: add FlipFlop, Counter, Timeout 2015-03-01 16:33:46 +01:00
Florent Kermarrec
e82531cdf8 move dfi/lasmibus/wishbone2lasmi to MiSoC sdram 2015-02-27 16:54:22 +01:00
Florent Kermarrec
225a2d4704 report cachesize in wishbone2lasmi 2015-02-27 14:12:13 +01:00
Florent Kermarrec
452c60e0c3 endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations) 2015-02-14 03:10:56 -08:00
Florent Kermarrec
319465445d actorlib/structuring: fix eop generation in Pack 2015-02-14 03:07:18 -08:00
Florent Kermarrec
c7eba8f4c4 remove crc since each crc is specific. It's probably better to adapt code for each case. 2015-02-14 03:01:12 -08:00
Florent Kermarrec
7471b2a152 genlib/crc: use OrderedDict 2015-01-23 00:23:41 +08:00
Florent Kermarrec
2175a79c03 fhdl/std: add FinalizeError import 2015-01-23 00:23:41 +08:00
Florent Kermarrec
037ea05b1e crc: modify CRCChecker to remove CRC and clean up 2014-12-21 17:24:52 +08:00
Sebastien Bourdeauducq
ae770c0f8c bank: support direct mapping of CSRs on Wishbone 2014-11-30 22:28:39 +08:00
Yann Sionneau
ee928a8973 Wishbone DownConverter: Fix sel signal 2014-11-26 19:33:12 +08:00
Sebastien Bourdeauducq
4542de2c11 genlib/fsm: add NextValue to replace reg/reg_next/ce pattern 2014-11-25 17:16:21 +08:00
Sebastien Bourdeauducq
5801e5746b fhdl/tools: do not attempt to rename sync clock domain if it does not exist 2014-11-21 14:51:05 -08:00
Sebastien Bourdeauducq
eb47f458dd flow: endpoint description structure with packetized parameter 2014-11-20 22:31:56 -08:00
Sebastien Bourdeauducq
f5fc4b365f actorlib/fifo: add buffered parameter 2014-11-20 18:46:54 -08:00
Jannis Harder
f847faf004 actorlib/fifo: fix no-op assignment due to .payload omission 2014-11-14 21:25:19 +01:00
Guy Hutchison
9f2f8d279d add hamming-code gen/check lib 2014-11-06 18:19:59 -08:00
Sebastien Bourdeauducq
ccc9a0d334 test/test_size: fix slice comparison 2014-11-03 12:08:43 +08:00
Sebastien Bourdeauducq
dcedc4e6a5 actorlib/structuring/Pipeline: make 'busy' a signal 2014-11-01 21:48:02 +08:00
Florent Kermarrec
33c3a927c2 actorlib/structuring: add Pipeline 
Pipeline enables easy cascading of dataflow modules.
DataFlowGraph can eventually use it to implement the
add_pipeline method to avoid duplicating things.
 2014-11-01 21:47:00 +08:00
Florent Kermarrec
8db549a23d actorlib/structuring: add Converter 
Converter enables easy conversions of data width on dataflows.
It handles the 3 possibles cases:
- downconverter
- upconverter
- direct connection when data width are identical.
 2014-11-01 21:43:52 +08:00
Sebastien Bourdeauducq
a7e4907724 Merge branch 'master' of github.com:m-labs/migen 2014-11-01 21:33:35 +08:00
Florent Kermarrec
bd1d456f5d flow/actor, actorlib/structuring: add packet support 2014-11-01 21:22:46 +08:00
Florent Kermarrec
4d1b6da42f bus/csr: add configurable address_width (needed more than 32 modules with CSR) 2014-11-01 21:22:11 +08:00
Florent Kermarrec
fcf2f7517c crc: generate error asynchronously to avoid stalling the flow and simplify 2014-11-01 21:21:46 +08:00
Sebastien Bourdeauducq
a4782899f6 fhdl/verilog: fix tristate to instance connection 2014-10-29 18:18:17 +08:00
Yann Sionneau
286092b62e Raise exception when not using correct boolean operators 2014-10-27 19:40:22 +08:00
Florent Kermarrec
86abb253c8 flow/actor/Endpoint: clean up __getattr__ 2014-10-22 09:35:30 +08:00
Florent Kermarrec
37031e3a2f DMAWriteController: fix Demultiplexer layout 2014-10-20 23:58:16 +08:00
Florent Kermarrec
07c33279c2 use new direct access on endpoints 2014-10-20 23:12:16 +08:00
Florent Kermarrec
ff688fb2f9 _Endpoint: allow direct access of payload elements 2014-10-20 23:09:56 +08:00
Florent Kermarrec
dbaeaf7833 remove trailing whitespaces 2014-10-17 17:08:46 +08:00
Florent Kermarrec
22507b117c bank: add re to CSRStorage 
being able to know when a register is updated is useful in many cases and avoid having to handle another register for that.
re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order.
 2014-10-16 17:43:41 +08:00
Sebastien Bourdeauducq
15f67b30d0 genlib/fsm: make first fsm.act() the reset state, even when using after_*/before_* methods before fsm.act 2014-09-29 19:38:58 +08:00
Florent Kermarrec
e03091e7e2 add generic CRCEngine, CRC32, CRCInserter and CRCChecker 
CRCEngine implements a generic and optimized CRC LFSR. It will enable generation of CRC generators and checkers.
CRC32 is an implementation of IEEE 802.3 CRC using the CRCEngine.
CRC32Inserter and CRC32Checker have been tested on an ethernet MAC.
 2014-09-26 11:42:10 +08:00
Florent Kermarrec
a03570ccca flow/actor: fix eop direction 2014-09-23 00:14:58 +08:00
Florent Kermarrec
66054af7bb flow/actor: add packetized parameter for Sink and Source 2014-09-22 23:45:28 +08:00
Florent Kermarrec
967b73bef3 actorlib/structuring: add reverse parameter to Unpack and Pack 2014-09-22 23:41:40 +08:00
Sebastien Bourdeauducq
6c9810532b genlib/fifo/SyncFIFOBuffered: replace not supported 2014-09-17 19:59:13 +08:00
Sebastien Bourdeauducq
4cacf97088 genlib/fifo: same 'level' semantics between SyncFIFOBuffered and FWFT SyncFIFO 2014-09-17 19:58:43 +08:00
Sebastien Bourdeauducq
264bc61e04 genlib/fifo: add replace command to sync FIFO 2014-09-10 21:19:15 +08:00
Sebastien Bourdeauducq
325ffdc6c6 actorlib/spi: remove unneeded import 2014-09-08 18:48:54 +08:00
Florent Kermarrec
c1e12c3346 actorlib/spi: remove EventManager from DMAController 2014-09-08 11:34:21 +08:00
Robert Jordens
0bac463780 sim/icarus: add vpi directory to module search path 
This allows running the iverilog simulations from the migen top directory
without having to install the .vpi anywhere.
 2014-09-07 16:49:12 +08:00
Robert Jordens
3d84a7a9de cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic 2014-09-07 16:49:12 +08:00
Robert Jordens
11f58862db test_cordic: stop spewing out numbers 2014-09-07 16:49:12 +08:00
Robert Jordens
4def6ec391 flow/network: replace NetworkX MultiDiGraph with simple implementation 2014-09-07 16:48:46 +08:00
Robert Jordens
683643266f cordic: vivado is bad at inferring compact adder/subtractor logic 2014-09-04 15:25:34 +08:00
Robert Jordens
bd232f3f61 fhdl.structure: do not permit clock domain names that start with numbers 2014-08-18 11:01:56 +08:00
Robert Jordens
ac2e961618 fhdl.structure: remove unused imports 2014-08-18 11:01:56 +08:00
Robert Jordens
6036fffef2 Signal.__getitem__: raise TypeError and IndexError when appropriate 2014-08-18 11:01:56 +08:00
Robert Jordens
b3d69913cd Signal.like: pass kwargs 2014-08-18 11:01:56 +08:00
Sebastien Bourdeauducq
60706e4b70 bus/dfi: add CKE and RESET_N 2014-08-09 10:56:08 +08:00
Sebastien Bourdeauducq
b124a98d92 genlib: add reset synchronizer 2014-08-06 19:38:37 +08:00
Sebastien Bourdeauducq
8baa957539 genlib/fifo: use synchronous memory read instead of additional register 
The latter causes problems with InsertReset
 2014-08-02 08:52:49 +08:00
Robert Jordens
44c6e524ba migen.fhdl.structure: add Signal.like(other) 
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
 2014-07-24 23:52:59 -06:00
Florent Kermarrec
9fcea6e64a migen/sim/generic: use kwargs to pass parameters to icarus.Runner 2014-07-24 10:17:54 -06:00
Robert Jordens
10d639d313 flow.plumbing: spelling 2014-07-19 14:29:51 -06:00
Robert Jordens
9266e10cae flow.plumbing: make argument order consistent 2014-07-19 14:29:50 -06:00
Sebastien Bourdeauducq
ff1d105c7e genlib/SyncFIFO: remove flush signal (use InsertReset instead) 2014-07-17 19:15:45 -06:00
Florent Kermarrec
ea0f4706f5 fsm: set reset_state as default state 2014-06-22 15:21:22 +02:00
Florent Kermarrec
4c426b36f3 fifo: add support for depth=2 2014-06-15 23:58:46 +02:00
Florent Kermarrec
70a2ee4368 migen/bank/description: add reset parameter to CSRStatus 2014-06-15 23:54:38 +02:00
Florent Kermarrec
9c1d95f6a4 wishbone2lasmi: fix wordbits computation 2014-05-01 13:32:18 +02:00
Sebastien Bourdeauducq
29ed3918cc fhdl: forbid zero-length signals 2014-04-18 15:01:50 +02:00
Florent Kermarrec
86f852a5f1 wishbone2lasmi: support lasmim data_width < wishbone data_width 2014-04-18 15:00:53 +02:00
Sebastien Bourdeauducq
a36a208dd1 sim: use (mandatory) ncycles when starting a simulation with no active functions 2014-04-13 15:16:27 +02:00
Robert Jordens
ce378f47d3 test/SyncFIFOCase: better test bench termination 2014-04-07 00:05:08 +02:00
Robert Jordens
ac1363565d genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered 2014-04-05 12:15:14 +02:00
Robert Jordens
9deddbdfbc test/test_cordic: fix for new Simulation API 2014-03-24 15:01:44 -07:00
Robert Jordens
7649028bdc test/support: fix default ncycles 2014-03-24 15:01:44 -07:00
Robert Jordens
0023b742e4 genlib/coding: gracefully handle flen(i) < 2 2014-03-19 18:12:27 -07:00
Robert Jordens
0836f2814a bus/csr: new simulation api 2014-03-19 18:12:27 -07:00
Robert Jordens
b03d9f4c14 genlib/fifo: add flush, expose level in SyncFIFO 
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.

Signed-off-by: Robert Jordens <jordens@gmail.com>
 2014-03-15 23:10:46 -07:00
Sebastien Bourdeauducq
2ab939e69d fix SimActor TB terminations 2014-01-28 00:03:56 +01:00
Sebastien Bourdeauducq
90f0dfad63 Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator 2014-01-27 23:58:46 +01:00
Sebastien Bourdeauducq
63c1d7e4b7 New simulation API 2014-01-26 22:19:43 +01:00
Sebastien Bourdeauducq
8f69d9b669 bank/eventmanager: add SharedIRQ 2014-01-06 22:13:06 +01:00
Robert Jordens
be1c8551d2 migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime) 2013-12-17 18:40:49 +01:00
Sebastien Bourdeauducq
a20688f777 fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems 2013-12-13 00:02:50 +01:00
Sebastien Bourdeauducq
adda930c68 fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs 2013-12-12 17:37:31 +01:00
Sebastien Bourdeauducq
adffec35f6 utils/misc: add gcd_multiple function to compute GCD or any number of integers 2013-12-12 17:36:50 +01:00
Sebastien Bourdeauducq
c13fe1bc63 specials/Memory: allow for more flexibility in memory port signals 2013-12-12 17:36:17 +01:00
Sebastien Bourdeauducq
135a4fea25 fhdl/verilog: fix representation of negative integers 
Give the explicit two's complement representation for the given bit width.

This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
 2013-12-11 22:26:10 +01:00
Robert Jordens
d6cb981c7a migen/test/test_signed: add a (currently failing) signed comparison testcase 2013-12-10 23:33:53 +01:00
Robert Jordens
487df5b174 migen/fhdl/bitcontainer: fix signed arrays (map is an iterator) 2013-12-10 23:32:12 +01:00
Robert Jordens
8d3d61ba98 fhdl.size: rename to bitcontainer 2013-12-03 22:51:52 +01:00
Robert Jordens
86ba9c8bbc migen.fhdl.size: verify fslice for negative values 2013-12-03 21:39:37 +01:00
Robert Jordens
c71eb5778f migen.fhdl.structure: have Cat() flat_iteration-ize its arguments 2013-12-03 21:36:33 +01:00
Robert Jordens
1bf133755e migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things 2013-12-03 21:36:33 +01:00
Robert Jordens
fe67210d77 migen.fhdl.size: add fiter(), fslice(), and freversed() 
do not overload __len__, __iter__, __reversed__ as not all valid
expressions (ints and bools) have them. furthermore len([]) is and
should be different from flen([]) (the later raises an error). keep
__getitem__ as an exception that proves the rule ;)
 2013-12-03 21:36:33 +01:00
Sebastien Bourdeauducq
ae6b78faeb genlib/divider: fix diff computation 2013-12-02 17:56:03 +01:00
Robert Jordens
dd24fdd356 genlib/sort: add bitonic, combinatorial sorter 
complete with with api documentation and unittests
 2013-12-02 12:56:36 +01:00
Robert Jordens
9762546c95 genlib/cordic: cleanup, documentation, unittests 2013-12-02 12:56:24 +01:00
Robert Jordens
e54fa6f5f4 migen/test: if SimCase is a TestCase, it's run in every module that imports it 2013-12-02 12:43:14 +01:00
Robert Jordens
4eef3b9399 migen/test/support: allow easy re-setUp of the testbench with different parameters 2013-12-02 12:42:59 +01:00
Sebastien Bourdeauducq
de830dc743 mibuild: use keyword arguments directly in build_cmdline 2013-12-01 17:56:07 +01:00
Robert Jördens
5b26fb10a9 genlib/coding: add docstrings, add it to api doc 2013-11-29 23:25:31 +01:00
Robert Jördens
5ccd1799f2 genlib/coding, test/test_coding: unittests 2013-11-29 23:25:03 +01:00
Sebastien Bourdeauducq
205908791a test/test_fifo: do not use relative import 
This way the test can simply be run with:
 python -m unittest test_fifo.py
 2013-11-29 23:18:03 +01:00
Robert Jördens
502a2871bc test/test_fifo, genlib/fifo: move test to unittest 2013-11-29 23:11:53 +01:00
Robert Jördens
cb5e0953aa migen/test: start unittests 2013-11-29 23:11:23 +01:00
Robert Jördens
55afab2276 sim: use Simulator as a contextmanager 
__del__ garbage collector callbacks are too delicate.  E.g. imported
modules can be garbage collected before the objects using them. Can't
use os.remove, socket.SHUT_RDWR...

* added a DeprecationWarning if a Simulator is garbage collected without
having its .close() called
* renamed all gc __del__ callbacks to close()
* implemented context manager hooks for Simulator. Use like

   with Simulator(TestBench()) as s:
       s.run()
 2013-11-29 23:05:15 +01:00
Sebastien Bourdeauducq
be9fea182d fhdl/structure: clarify usage restrictions of LHS Cat 2013-11-29 22:35:53 +01:00
Robert Jördens
73db4944f1 fhdl.structure: document the API 2013-11-29 22:31:55 +01:00
Robert Jördens
e469e5e539 genlib.fifo: fix docstring section syntax 2013-11-29 22:31:51 +01:00
Sebastien Bourdeauducq
e1b31ec455 genlib/fifo: clarify we behaviour when writable=0 2013-11-28 22:31:10 +01:00
Robert Jordens
6e9e0a60eb setup API documentation, start by documenting fifos 2013-11-28 22:14:20 +01:00
Sebastien Bourdeauducq
fa741f54fd specials/Instance: add PreformattedParam 2013-11-25 12:09:51 +01:00
Sebastien Bourdeauducq
29f7b94e37 bus/wishbone/sram: expose memory component 2013-11-24 23:43:14 +01:00
Sebastien Bourdeauducq
c5342c5b5c bus/wishbone: style 2013-11-24 23:42:54 +01:00
Sebastien Bourdeauducq
948d7e7332 lasmibus/Crossbar: more flexible master assignment 2013-11-23 17:51:22 +01:00
Robert Jordens
7e4024beb3 genlib/fsm: rename {entering,leaving} to after_{entering,leaving}, add before_{entering,leaving} 2013-11-21 23:30:24 +01:00
Sebastien Bourdeauducq
cdabf34bee flow/isd: update to new APIs 2013-11-20 17:45:09 +01:00
Florent Kermarrec
416c8af1e2 plumbing: use Record.connect in Multiplexer/ Demultiplexer 2013-11-04 21:22:05 +01:00
Florent Kermarrec
7e2859f43f util: add missing __init__.py 2013-11-04 21:22:02 +01:00
Sebastien Bourdeauducq
c3aad93753 actorlib/spi/DMAWriteController: make ack_when_inactive a keyword-only arg 2013-11-02 23:21:05 +01:00
Florent Kermarrec
e0e99ec385 actorlib/spi: add ack_when_inactive parameter to DMA Write Controller 
In some cases we don't want to stall the input pipeline when the DMA is inactive, setting ack_when_inactive to True will enable acknowledge of data when the DMA is inactive.
 2013-11-02 23:16:05 +01:00
Sebastien Bourdeauducq
b4a7d36fa5 flow/plumbing/muxdemux: use existing connect() method instead of new function 2013-11-02 23:15:03 +01:00
Sebastien Bourdeauducq
7170ae3a67 flow/actor: Record.connect no longer takes kwargs 2013-11-02 23:14:32 +01:00
Florent Kermarrec
84966af098 flow/plumbing: add Multiplexer and Demultiplexer 2013-11-02 23:09:47 +01:00
Sebastien Bourdeauducq
f658802ff8 replace use of __dict__ with dir()/xdir() 2013-11-02 16:03:47 +01:00
Sebastien Bourdeauducq
892c12bff5 flow: add AbstractActor busy signals 2013-10-25 18:50:14 +02:00
Sebastien Bourdeauducq
99c53ed9e8 Better record layout parameterization mechanism 2013-10-23 12:54:50 +02:00
Sebastien Bourdeauducq
98f79021cd Revert "genlib/record: support passing params in same object" 
This reverts commit 018afe57ef.
 2013-10-22 15:23:00 +02:00
Sebastien Bourdeauducq
b782db14fc Revert "genlib/fifo: support RecordP" 
This reverts commit c0d2b5a789.
 2013-10-22 15:22:40 +02:00
Sebastien Bourdeauducq
c0d2b5a789 genlib/fifo: support RecordP 2013-10-21 22:30:06 +02:00
Sebastien Bourdeauducq
018afe57ef genlib/record: support passing params in same object 2013-10-21 22:05:28 +02:00
Sebastien Bourdeauducq
4fb3e970b1 genlib/fsm: add entering/ongoing/leaving methods 2013-09-06 14:51:18 +02:00
Sebastien Bourdeauducq
91422788ef actorlib/fifo: do not duplicate safe write logic 2013-09-04 17:33:53 +02:00
Sebastien Bourdeauducq
523565be63 actorlib/spi/DMAController: use EventSourceProcess 2013-09-04 17:29:42 +02:00
Florent Kermarrec
b6eb97e49f actorlib/spi: add optional irq generation on DMAController 2013-09-04 17:27:57 +02:00
Sebastien Bourdeauducq
1209ec17f6 actorlib/fifo: rewrite 
* use classes for less code duplication
* the idea of decorator is to avoid passing common parameters (e.g. clock domain names) in module constructors, so remove those parameters
* style
 2013-09-04 17:22:50 +02:00
Florent Kermarrec
71b14ac873 actorlib: add fifo 2013-09-04 17:15:22 +02:00
Sebastien Bourdeauducq
dac10f5570 bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules 2013-08-26 20:33:34 +02:00
Sebastien Bourdeauducq
2cf6b6c768 wishbone/SRAM: fix non-32-bit bus 2013-08-26 20:32:59 +02:00
Florent Kermarrec
33ca4d778f wishbone2lasmi: configurable data width 2013-08-26 20:29:12 +02:00
Florent Kermarrec
628fa8ce9e wishbone : add DownConverter 2013-08-26 20:28:09 +02:00
Florent Kermarrec
a653a6144b wishbone2lasmi : add support for 32 bits lasmim data width 2013-08-20 18:49:46 +02:00
Florent Kermarrec
37930d70ac genlib/misc: improve genericity of split/displacer/chooser 2013-08-20 18:49:02 +02:00
Nina Engelhardt
6f9f08f6eb add ternary operator sel ? a : b 2013-08-12 13:15:56 +02:00
Nina Engelhardt
e12187aa80 add += operator to fragment 2013-08-12 13:15:05 +02:00
Sebastien Bourdeauducq
fdf022a04b fhdl: improve naming of related signals 2013-08-08 19:22:17 +02:00
Sebastien Bourdeauducq
2c580fff03 fhdl/namer: detect leaf nodes better 2013-08-08 12:22:58 +02:00
Sebastien Bourdeauducq
eb1417c5ed fhdl: move insert_resets to tools 2013-08-08 11:32:58 +02:00
Sebastien Bourdeauducq
305c6985bc fhdl: support for naming related signals 2013-08-08 11:32:37 +02:00
Sebastien Bourdeauducq
146a1b5d51 namer: add HUID suffix step 2013-08-08 00:15:18 +02:00
Sebastien Bourdeauducq
fd34b75fb4 namer: split by numbers 2013-08-07 23:22:40 +02:00
Sebastien Bourdeauducq
0e369318bb treeviz: support multiline labels 2013-08-07 21:46:03 +02:00
Sebastien Bourdeauducq
ceddd8afa4 treeviz: improve layout of unbalanced trees 2013-08-07 18:32:02 +02:00
Sebastien Bourdeauducq
7a243171bd fhdl/namer: new namer with explicit tree 2013-08-07 17:13:52 +02:00
Sebastien Bourdeauducq
cc5ff7a772 add tree visualizer 2013-08-07 15:52:35 +02:00
Nina Engelhardt
efa7dc9cf4 fhdl/edif: adjust for use with mibuild 2013-08-03 10:54:06 +02:00
Nina Engelhardt
7372c7a97c fhdl/edif: add support for inout signals 2013-08-03 10:51:24 +02:00
Sebastien Bourdeauducq
0e195da3c0 bank/csrgen: add get_offset function to pre-calculate register addresses 2013-08-02 23:05:54 +02:00
Sebastien Bourdeauducq
2a296aced7 bank/description/AutoCSR: prefix csr/mem only once 2013-08-02 23:05:21 +02:00
Nina Engelhardt
17002fb05e fhdl: add EDIF back-end 2013-07-31 22:47:43 +02:00
Sebastien Bourdeauducq
246b860a85 csr: new data width API 2013-07-28 16:33:36 +02:00
Sebastien Bourdeauducq
6ba0d4bd0d bus/wishbone: configurable data width 2013-07-27 22:25:07 +02:00
Sebastien Bourdeauducq
14ed5c1acc genlib/record: support abstract signal width 2013-07-27 22:18:06 +02:00
Sebastien Bourdeauducq
7e20320b9d pytholite/io: len -> flen 2013-07-27 15:38:48 +02:00
Sebastien Bourdeauducq
04ec60541c pythloite/ExprCompiler: attempt compile-time evaluation first 2013-07-27 15:38:29 +02:00
Sebastien Bourdeauducq
f62eff0309 bus/csr/Initiator: correct read latency 2013-07-27 15:37:47 +02:00
Sebastien Bourdeauducq
e05f520cdf actorlib/spi: remove unused function 2013-07-27 15:36:42 +02:00
Nina Engelhardt
61b8958953 fix synthesis translate on/off switch 2013-07-26 15:55:16 +02:00
Sebastien Bourdeauducq
9c7ad6b05b fhdl: RenameClockDomains decorator 2013-07-26 15:42:14 +02:00
Sebastien Bourdeauducq
cec8fc4ca4 fhdl/specials/Instance: fix item sorting 2013-07-26 14:00:29 +02:00
Robert Jordens
6e1195415e genlib/roundrobin: fix n==1 case (correctly) 2013-07-26 09:33:33 +02:00
Robert Jordens
b8ff2f2792 genlib/roundrobin.py: fix n==1 case 2013-07-26 00:41:08 +02:00
Sebastien Bourdeauducq
b96eb339af fhdl: compact Instance syntax 2013-07-25 20:34:19 +02:00
Sebastien Bourdeauducq
b7ed19c6c5 fhdl: do not export Fragment 2013-07-25 18:52:54 +02:00
Sebastien Bourdeauducq
b367932498 fhdl: introduce module decorators 2013-07-25 17:56:31 +02:00
Sebastien Bourdeauducq
cabae0c32b genlib: remove direct uses of Fragment 2013-07-24 19:25:14 +02:00
Robert Jördens
fe18397acc wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect) 2013-07-22 10:30:44 +02:00
Robert Jördens
5bc9a0b383 fsm.py: set reset_state 2013-07-22 10:30:40 +02:00
Sebastien Bourdeauducq
411e6ec114 fhdl/tools: do not export resort_statements 2013-07-17 16:50:09 +02:00
Sebastien Bourdeauducq
d5d2e64dc3 Revert "fhdl/tools/group_by_target: remove resort_statements" 
This reverts commit 939f01cee2.
 2013-07-17 16:49:26 +02:00