Commit Graph

905 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 1209ec17f6 actorlib/fifo: rewrite
* use classes for less code duplication
* the idea of decorator is to avoid passing common parameters (e.g. clock domain names) in module constructors, so remove those parameters
* style
2013-09-04 17:22:50 +02:00
Florent Kermarrec 71b14ac873 actorlib: add fifo 2013-09-04 17:15:22 +02:00
Sebastien Bourdeauducq dac10f5570 bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules 2013-08-26 20:33:34 +02:00
Sebastien Bourdeauducq 2cf6b6c768 wishbone/SRAM: fix non-32-bit bus 2013-08-26 20:32:59 +02:00
Florent Kermarrec 33ca4d778f wishbone2lasmi: configurable data width 2013-08-26 20:29:12 +02:00
Florent Kermarrec 628fa8ce9e wishbone : add DownConverter 2013-08-26 20:28:09 +02:00
Florent Kermarrec a653a6144b wishbone2lasmi : add support for 32 bits lasmim data width 2013-08-20 18:49:46 +02:00
Florent Kermarrec 37930d70ac genlib/misc: improve genericity of split/displacer/chooser 2013-08-20 18:49:02 +02:00
Nina Engelhardt 6f9f08f6eb add ternary operator sel ? a : b 2013-08-12 13:15:56 +02:00
Nina Engelhardt e12187aa80 add += operator to fragment 2013-08-12 13:15:05 +02:00
Sebastien Bourdeauducq fdf022a04b fhdl: improve naming of related signals 2013-08-08 19:22:17 +02:00
Sebastien Bourdeauducq 2c580fff03 fhdl/namer: detect leaf nodes better 2013-08-08 12:22:58 +02:00
Sebastien Bourdeauducq eb1417c5ed fhdl: move insert_resets to tools 2013-08-08 11:32:58 +02:00
Sebastien Bourdeauducq 305c6985bc fhdl: support for naming related signals 2013-08-08 11:32:37 +02:00
Sebastien Bourdeauducq 146a1b5d51 namer: add HUID suffix step 2013-08-08 00:15:18 +02:00
Sebastien Bourdeauducq fd34b75fb4 namer: split by numbers 2013-08-07 23:22:40 +02:00
Sebastien Bourdeauducq 0e369318bb treeviz: support multiline labels 2013-08-07 21:46:03 +02:00
Sebastien Bourdeauducq ceddd8afa4 treeviz: improve layout of unbalanced trees 2013-08-07 18:32:02 +02:00
Sebastien Bourdeauducq 7a243171bd fhdl/namer: new namer with explicit tree 2013-08-07 17:13:52 +02:00
Sebastien Bourdeauducq cc5ff7a772 add tree visualizer 2013-08-07 15:52:35 +02:00
Nina Engelhardt efa7dc9cf4 fhdl/edif: adjust for use with mibuild 2013-08-03 10:54:06 +02:00
Nina Engelhardt 7372c7a97c fhdl/edif: add support for inout signals 2013-08-03 10:51:24 +02:00
Sebastien Bourdeauducq 0e195da3c0 bank/csrgen: add get_offset function to pre-calculate register addresses 2013-08-02 23:05:54 +02:00
Sebastien Bourdeauducq 2a296aced7 bank/description/AutoCSR: prefix csr/mem only once 2013-08-02 23:05:21 +02:00
Nina Engelhardt 17002fb05e fhdl: add EDIF back-end 2013-07-31 22:47:43 +02:00
Sebastien Bourdeauducq 246b860a85 csr: new data width API 2013-07-28 16:33:36 +02:00
Sebastien Bourdeauducq 6ba0d4bd0d bus/wishbone: configurable data width 2013-07-27 22:25:07 +02:00
Sebastien Bourdeauducq 14ed5c1acc genlib/record: support abstract signal width 2013-07-27 22:18:06 +02:00
Sebastien Bourdeauducq 7e20320b9d pytholite/io: len -> flen 2013-07-27 15:38:48 +02:00
Sebastien Bourdeauducq 04ec60541c pythloite/ExprCompiler: attempt compile-time evaluation first 2013-07-27 15:38:29 +02:00
Sebastien Bourdeauducq f62eff0309 bus/csr/Initiator: correct read latency 2013-07-27 15:37:47 +02:00
Sebastien Bourdeauducq e05f520cdf actorlib/spi: remove unused function 2013-07-27 15:36:42 +02:00
Nina Engelhardt 61b8958953 fix synthesis translate on/off switch 2013-07-26 15:55:16 +02:00
Sebastien Bourdeauducq 9c7ad6b05b fhdl: RenameClockDomains decorator 2013-07-26 15:42:14 +02:00
Sebastien Bourdeauducq cec8fc4ca4 fhdl/specials/Instance: fix item sorting 2013-07-26 14:00:29 +02:00
Robert Jordens 6e1195415e genlib/roundrobin: fix n==1 case (correctly) 2013-07-26 09:33:33 +02:00
Robert Jordens b8ff2f2792 genlib/roundrobin.py: fix n==1 case 2013-07-26 00:41:08 +02:00
Sebastien Bourdeauducq b96eb339af fhdl: compact Instance syntax 2013-07-25 20:34:19 +02:00
Sebastien Bourdeauducq b7ed19c6c5 fhdl: do not export Fragment 2013-07-25 18:52:54 +02:00
Sebastien Bourdeauducq b367932498 fhdl: introduce module decorators 2013-07-25 17:56:31 +02:00
Sebastien Bourdeauducq cabae0c32b genlib: remove direct uses of Fragment 2013-07-24 19:25:14 +02:00
Robert Jördens fe18397acc wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect) 2013-07-22 10:30:44 +02:00
Robert Jördens 5bc9a0b383 fsm.py: set reset_state 2013-07-22 10:30:40 +02:00
Sebastien Bourdeauducq 411e6ec114 fhdl/tools: do not export resort_statements 2013-07-17 16:50:09 +02:00
Sebastien Bourdeauducq d5d2e64dc3 Revert "fhdl/tools/group_by_target: remove resort_statements"
This reverts commit 939f01cee2.
2013-07-17 16:49:26 +02:00
David Carne 9190568685 genlib/fifo/AsyncFIFO: fix data corruption bug 2013-07-17 12:10:39 +02:00
Sebastien Bourdeauducq 939f01cee2 fhdl/tools/group_by_target: remove resort_statements 2013-07-17 10:38:39 +02:00
David Carne 16ebe41028 fhdl/tools: BUGFIX: fix group_by_target grouping
group_by_target does not properly combine target groups if statements
are presented in the order:

 ({A}, statement1)
 ({B}, statement2)
 ({A, B}, statement3)

which returns groups:

 ({A, B}, [statement1, statement3])
 ({B}, [statement2])

This patch fixes group_by_target such that the resulting group is:

 ({A, B}, [statement1, statement2, statement3])
2013-07-17 10:14:39 +02:00
Sebastien Bourdeauducq 5b36f688ea Remove ASMI 2013-07-16 18:50:50 +02:00
David Carne faa8b7c49a fhdl/tools: clock domain merging for clock renaming 2013-07-16 18:17:44 +02:00
Sebastien Bourdeauducq b016a60b85 lasmibus: fix master locking 2013-07-15 21:45:07 +02:00
Sebastien Bourdeauducq 7083764b53 genlib/fifo: add test bench 2013-07-15 21:36:39 +02:00
Sebastien Bourdeauducq 65a0b12812 actorlib/spi/DMAController: export length/storage/trigger 2013-07-13 17:13:15 +02:00
Sebastien Bourdeauducq 6595b9a111 actorlib/spi/SingleGenerator: export CSRs 2013-07-13 17:12:51 +02:00
Sebastien Bourdeauducq c2d6f14087 flow/actor/PipelinedActor: clean up 2013-07-12 18:52:34 +02:00
Sebastien Bourdeauducq 6aa1e0c199 actorlib/spi/DMAWriteController: len -> flen 2013-07-11 19:22:56 +02:00
Florent Kermarrec f5ddd33e7e dfi: split phase description 2013-07-10 19:56:47 +02:00
Sebastien Bourdeauducq 43fe16ef73 bus/lasmibus: add separate req/data ack to target and initiator 2013-07-10 19:09:51 +02:00
Sebastien Bourdeauducq af6ef0a3b4 dma_lasmi/Writer: fix default FIFO depth 2013-07-07 20:01:55 +02:00
Sebastien Bourdeauducq fa8112c3f5 dma_lasmi/Reader: handle ack=1 when stb=0 2013-07-07 18:57:05 +02:00
Sebastien Bourdeauducq 7e6fbd31a4 lasmibus/crossbar: simplify master ack generation 2013-07-07 18:56:43 +02:00
Sebastien Bourdeauducq b68c00d36f pytholite: fix kwargs handling 2013-07-03 17:20:05 +02:00
Sebastien Bourdeauducq 0aa58f5dcf pytholite: support generator arguments 2013-07-03 16:35:07 +02:00
Sebastien Bourdeauducq 04efee7847 fhdl: mark variable as deprecated 2013-06-30 20:14:20 +02:00
Sebastien Bourdeauducq 71b89e4c46 fhdl/verilog: lower complex slices before reset insertion 2013-06-30 14:32:47 +02:00
Sebastien Bourdeauducq ded5e569eb fhdl/tools: separate complex slice lowerer from basic lowerer 2013-06-30 14:32:19 +02:00
Sebastien Bourdeauducq 9c59ea1e26 genlib/misc: remove bitreverse 2013-06-30 14:31:25 +02:00
Robert Jördens a255296171 support re-slicing and non-unit step size
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
2013-06-30 14:03:34 +02:00
Robert Jördens 9d241f8cd3 coding.py: rewrite If() to make verilog more readable 2013-06-30 11:39:47 +02:00
Sebastien Bourdeauducq b0d467d744 pytholite: use eval instead of literal_eval 2013-06-28 19:03:55 +02:00
Robert Jördens ecc4062071 genlib/coding.py: binary vs. one-hot, priority coding 2013-06-28 15:20:01 +02:00
Sebastien Bourdeauducq 48a5b86dcd genlib/cordic: cleanup 2013-06-26 22:46:04 +02:00
Sebastien Bourdeauducq 080afdc3f9 fhdl/verilog: fix signedness rules for comparison 2013-06-26 22:45:47 +02:00
Robert Jordens 0224ea01cb migen/genlib/cordic.py: generic cordic
* rotating or vectoring cordic modes
* circular, linear, or hyperbolic functions
* combinatorial, pipelined or iterative evaluation
* arbitrary width, stages and guard bits
* two or four quadrant mode for circular/rotate
2013-06-26 22:31:36 +02:00
Sebastien Bourdeauducq d0caa738bd FSM: new API 2013-06-25 22:17:39 +02:00
Sebastien Bourdeauducq b56cb3cefc fhdl/verilog: improve error reporting 2013-06-24 19:44:25 +02:00
Sebastien Bourdeauducq d6f7b4cee6 lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete) 2013-06-17 23:36:03 +02:00
Sebastien Bourdeauducq 5cd0019231 genlib/fifo: support records 2013-06-17 23:35:10 +02:00
Sebastien Bourdeauducq 6d6d232cad lasmibus/crossbar: better switching policy 2013-06-15 16:51:09 +02:00
Sebastien Bourdeauducq ac2cde0e87 asmibus: remove port sharing 2013-06-14 18:34:36 +02:00
Sebastien Bourdeauducq 0c52c08989 bus/asmibus: fix slot aging timer 2013-06-14 17:57:43 +02:00
Sebastien Bourdeauducq 1ec1fb9ebe bus/lasmibus/Crossbar: support cba_shift=0 2013-06-11 18:15:49 +02:00
Sebastien Bourdeauducq fe54c68762 lasmi: fix minor problems 2013-06-10 22:49:33 +02:00
Sebastien Bourdeauducq aea3b59432 genlib/fsm: fix handling of zero delayed_enter 2013-06-10 22:49:05 +02:00
Sebastien Bourdeauducq 3a284b9c1e actorlib: LASMI DMA (untested) 2013-06-10 22:29:39 +02:00
Sebastien Bourdeauducq 932bfa7e75 bus: Wishbone -> LASMI bridge (untested) 2013-06-10 18:52:07 +02:00
Sebastien Bourdeauducq f2e2397c9d bus/lasmibus: bugfixes 2013-06-09 23:36:32 +02:00
Sebastien Bourdeauducq a836cba790 bus/lasmibus: add target and initiator 2013-06-09 16:03:22 +02:00
Sebastien Bourdeauducq 35f9f2e9d7 bus/lasmi: interface definition and crossbar (untested) 2013-06-08 15:49:50 +02:00
Kenneth Ryerson 85813b3b58 csr/sram: fix reads on high addresses when word_bits != 0 2013-06-03 21:52:23 +02:00
Kenneth Ryerson e5e3492afe csr/sram: fix page_bits computation 2013-06-03 21:51:44 +02:00
Sebastien Bourdeauducq cebfe787db genlib/misc: fix import 2013-05-30 18:46:52 +02:00
Sebastien Bourdeauducq ebbd5ebcd2 bus/csr/SRAM: better handling of writes to memories larger than the CSR width 2013-05-30 18:45:04 +02:00
Sebastien Bourdeauducq f0b0942055 bitreverse: fhdl/tools -> genlib/misc 2013-05-30 18:44:37 +02:00
Sebastien Bourdeauducq bac62a32a9 Make memory ports part of specials
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq 70ffe86356 New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq 5208baada8 bus/wishbone/SRAM: support init and read_only 2013-05-19 20:53:54 +02:00
Sebastien Bourdeauducq 7ada0159fd bus/csr/SRAM: support init 2013-05-19 20:53:37 +02:00
Sebastien Bourdeauducq 792b8fed1b bus/asmi: port sharing support 2013-05-12 15:58:39 +02:00
Sebastien Bourdeauducq f202946717 fhdl/tools/_TargetLister: do not include array keys in targets 2013-05-11 17:28:41 +02:00
Sebastien Bourdeauducq 0ec6a7eb4e genlib/record: match_by_position -> connect_flat 2013-05-11 11:48:21 +02:00
Sebastien Bourdeauducq 955a9733c8 Revert "genlib/record/connect: add match_by_position"
This reverts commit df1ed32765.
2013-05-10 17:41:51 +02:00
Sebastien Bourdeauducq c82b53f1cd bank/description/AutoCSR: add autocsr_exclude 2013-05-08 20:58:57 +02:00
Sebastien Bourdeauducq 10212e85e7 dma_asmi: cleanup 2013-05-08 18:58:50 +02:00
Sebastien Bourdeauducq b9b6df6f29 bank/eventmanager: refactor, rename EventSourceLevel -> EventSourceProcess, add fully externally controlled event source 2013-05-08 18:12:26 +02:00
Sebastien Bourdeauducq 7a74dae461 actorlib/spi: add DMAWriteController 2013-05-04 17:38:54 +02:00
Sebastien Bourdeauducq fd089b146f actorlib/dma_asmi/OOOWriter: fix tag offset 2013-05-04 17:38:17 +02:00
Sebastien Bourdeauducq 12deaa91d8 flow/network/DataFlowGraph: add_buffered_connection 2013-05-02 13:25:30 +02:00
Sebastien Bourdeauducq b5b29f6d5d bank/description/CSRStorage: set reset property of storage for use in test benches 2013-05-02 11:49:23 +02:00
Sebastien Bourdeauducq 8ffa273719 flow/network: better determination of plumbing layout 2013-05-01 22:13:26 +02:00
Sebastien Bourdeauducq 471393d0f9 actorlib/dma_asmi: drive dat_wm 2013-05-01 21:52:26 +02:00
Sebastien Bourdeauducq c8810a016f actorlib/spi: add DMA read controller 2013-04-30 18:55:01 +02:00
Sebastien Bourdeauducq c70c71502e actorlib/spi/SingleGenerator: use CSR alignment bits 2013-04-30 18:54:47 +02:00
Sebastien Bourdeauducq dc0304a87b bank/description/CSRStorage: support alignment bits 2013-04-30 18:53:40 +02:00
Sebastien Bourdeauducq 51f1ace061 flow/network/CompositeActor: expose unconnected endpoints 2013-04-30 18:53:02 +02:00
Sebastien Bourdeauducq 4f13c5b74d flow/network/DataFlowGraph: add add_pipeline 2013-04-30 15:49:51 +02:00
Sebastien Bourdeauducq fb83794ef4 actorlib/spi/Collector: cleanup, new APIs 2013-04-28 18:32:46 +02:00
Sebastien Bourdeauducq 746e452838 actorlib/dma_asmi: support for writes 2013-04-28 18:06:36 +02:00
Sebastien Bourdeauducq e97edd7253 genlib/fifo: disable retiming on Gray counter outputs 2013-04-25 14:57:07 +02:00
Sebastien Bourdeauducq 156ef43ace genlib/cdc: add NoRetiming 2013-04-25 14:56:45 +02:00
Sebastien Bourdeauducq b862b070d6 fhdl/verilog: recursive Special lowering 2013-04-25 14:56:26 +02:00
Sebastien Bourdeauducq 67c3119249 genlib/fifo: add asynchronous FIFO 2013-04-25 13:30:37 +02:00
Sebastien Bourdeauducq fee228a09f fhdl/specials/memory: do not write address register for async reads 2013-04-25 13:30:05 +02:00
Sebastien Bourdeauducq 6c08cd67aa graycounter: expose binary output 2013-04-25 13:11:15 +02:00
Sebastien Bourdeauducq 0f9df2d732 genlib: add Gray counter 2013-04-24 19:13:36 +02:00
Florent Kermarrec f599fe4ade Support for resetless clock domains 2013-04-23 11:54:05 +02:00
Sebastien Bourdeauducq 8e11fcf1d0 bus/csr/SRAM: fix Module conversion errors 2013-04-14 13:55:04 +02:00
Sebastien Bourdeauducq ea63389823 fhdl: support len() on all values 2013-04-14 13:50:26 +02:00
Sebastien Bourdeauducq 75d33a0c05 fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec) 2013-04-11 18:55:49 +02:00
Sebastien Bourdeauducq 72ef4b9683 ioo+pytholite: use new Module API 2013-04-10 23:42:46 +02:00
Sebastien Bourdeauducq 4c9018ea17 fhdl/visit: add TransformModule 2013-04-10 23:42:14 +02:00
Sebastien Bourdeauducq 746acdacd1 ioo: move to genlib 2013-04-10 22:28:53 +02:00
Sebastien Bourdeauducq 1cc4c8ee9f uio: remove Trampoline (Python 3.3 provides generator delegation instead) 2013-04-10 22:15:28 +02:00
Sebastien Bourdeauducq 6ce856290a flow: match record fields by position 2013-04-10 21:33:56 +02:00
Sebastien Bourdeauducq df1ed32765 genlib/record/connect: add match_by_position 2013-04-10 21:33:45 +02:00
Sebastien Bourdeauducq 692794a21f flow: use Module and new Record APIs 2013-04-10 19:12:42 +02:00
Sebastien Bourdeauducq 20bdd424c8 flow: adapt to new Record API 2013-04-01 22:15:23 +02:00
Sebastien Bourdeauducq 29b468529f bus: replace simple bus module with new bidirectional Record 2013-04-01 21:54:21 +02:00
Sebastien Bourdeauducq 6a3c413717 New bidirectional-capable Record API 2013-04-01 21:53:33 +02:00
Sebastien Bourdeauducq c4f4143591 New CSR API 2013-03-30 17:28:41 +01:00
Sebastien Bourdeauducq 633e5e6747 fhdl/module/finalize: pass additional args to do_finalize 2013-03-30 11:29:46 +01:00
Sebastien Bourdeauducq 574becc1fc fhdl/specials: clean up clock domain handling 2013-03-26 11:58:34 +01:00
Sebastien Bourdeauducq 77a0f0a3bb actorlib/structuring/Cast: support inversion 2013-03-25 15:54:09 +01:00
Sebastien Bourdeauducq c4c4765a4e bank/csrgen/BankArray: retain name information 2013-03-25 14:44:15 +01:00
Sebastien Bourdeauducq 53edc3557e bank/description/Register: add get_size 2013-03-25 14:43:44 +01:00
Sebastien Bourdeauducq 3da98ea04d genlib/record: use getattr instead of __dict__ 2013-03-24 00:51:01 +01:00
Sebastien Bourdeauducq 1897b74f97 genlib/record: add eq 2013-03-24 00:50:33 +01:00
Sebastien Bourdeauducq 9d7c679b8c genlib/fifo: simple synchronous FIFO 2013-03-22 18:18:38 +01:00
Sebastien Bourdeauducq ca431fc7c2 fhdl/module: support clock domain remapping of submodules 2013-03-22 18:17:54 +01:00
Sebastien Bourdeauducq a94bf3b2c5 genlib/cdc/MultiReg: output clock domain defaults to sys 2013-03-21 10:40:02 +01:00
Sebastien Bourdeauducq 17f2b17654 fhdl/verilog: optionally disable clock domain creation 2013-03-18 18:45:19 +01:00
Sebastien Bourdeauducq 7a06e9457c Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
Sebastien Bourdeauducq dc55289323 fhdl/tools/_ArrayLowerer: complete support for arrays as targets 2013-03-18 14:38:01 +01:00
Sebastien Bourdeauducq e95d2f4779 fhdl/tools/value_bits_sign: support not 2013-03-18 09:52:43 +01:00
Sebastien Bourdeauducq b6fe3ace05 fhdl/structure: style fix 2013-03-17 15:33:38 +01:00
Sébastien Bourdeauducq 2a4cc3875c Merge pull request #6 from larsclausen/master
Minor improvements
2013-03-17 07:33:14 -07:00
Sebastien Bourdeauducq 2f522bdd9f genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains 2013-03-15 19:50:24 +01:00
Sebastien Bourdeauducq e2d156ef64 genlib/cdc/MultiReg: remove idomain 2013-03-15 19:49:24 +01:00
Sebastien Bourdeauducq 7b49fd9386 fhdl/specials: fix rename_clock_domain declarations 2013-03-15 19:47:01 +01:00
Sebastien Bourdeauducq 51bec340ab sim: remove PureSimulable (superseded by Module) 2013-03-15 19:41:30 +01:00
Sebastien Bourdeauducq dd0f3311cd structure: remove Fragment.call_sim 2013-03-15 19:15:48 +01:00
Sebastien Bourdeauducq 9b9bd77d00 sim: compatibility with new ClockDomain API 2013-03-15 19:15:28 +01:00
Sebastien Bourdeauducq bd8bbd9305 Make ClockDomains part of fragments 2013-03-15 18:17:33 +01:00
Sebastien Bourdeauducq 5adab17efa flow/actor/filter_endpoints: deterministic order 2013-03-14 12:20:18 +01:00
Sebastien Bourdeauducq fc883198ae bank/csrgen/BankArray: create banks in sorted order 2013-03-13 23:07:44 +01:00
Sebastien Bourdeauducq 52d13959f2 bank/description: modify reg/mem in-place 2013-03-13 19:46:34 +01:00
Lars-Peter Clausen dea4674922 Allow SimActors to produce/consume a constant stream of tokens
Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.

The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
Lars-Peter Clausen 72579a6129 Add support for negative slice indices
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].

Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
	reg.eq(Cat(Replicate(0, n), reg[-n:])

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
Sebastien Bourdeauducq 69dbf84e54 sim/generic: support implicit get_fragment 2013-03-12 16:54:01 +01:00
Sebastien Bourdeauducq ecfe1646ec fhdl/verilog: implicit get_fragment 2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq 4ada2ead05 fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq 04df076fba bank: automatic register naming 2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq 7e2581bf17 fhdl/tracer: recognize CALL_FUNCTION_VAR opcode 2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq 12158ceadf fhdl/tracer: recognize LOAD_DEREF opcode 2013-03-12 10:31:56 +01:00
Sebastien Bourdeauducq 3c75121783 fhdl/tracer: remove leading underscores from names 2013-03-11 22:21:58 +01:00
Sebastien Bourdeauducq 80970b203c bus/asmibus: use implicit finalization 2013-03-11 17:11:59 +01:00
Sebastien Bourdeauducq b042757187 Fix Register name conflict between Pytholite and Bank 2013-03-10 19:47:21 +01:00
Sebastien Bourdeauducq f93695f60e bank/eventmanager: use module and autoreg 2013-03-10 19:29:05 +01:00
Sebastien Bourdeauducq 174e8cb8d6 bus/asmibus: use fhdl.module API 2013-03-10 19:28:22 +01:00
Sebastien Bourdeauducq 17e0dfe120 fhdl/module: replace autofragment 2013-03-10 19:27:55 +01:00
Sebastien Bourdeauducq cddbc1157d bank/description/AutoReg: check that get_memories and get_registers are callable 2013-03-10 18:11:29 +01:00
Sebastien Bourdeauducq 68fe4c269c bank/csrgen: BankArray 2013-03-10 00:45:16 +01:00
Sebastien Bourdeauducq f1474420df bank/description: AutoReg 2013-03-10 00:43:16 +01:00
Sebastien Bourdeauducq d0676e2dd1 migen/fhdl/autofragment: factorize 2013-03-09 23:23:24 +01:00
Sebastien Bourdeauducq d0d2df3c4b fhdl/autofragment: remove legacy functions 2013-03-09 23:05:45 +01:00
Sebastien Bourdeauducq 72fb6fd6bd fhdl/tools/flat_iteration: generalize 2013-03-09 23:03:15 +01:00
Sebastien Bourdeauducq f53acb92e7 fhdl/autofragment: fix submodules 2013-03-09 21:15:38 +01:00
Sebastien Bourdeauducq 6da8eb906f fhdl/autofragment: empty build_fragment by default 2013-03-09 19:10:47 +01:00
Sebastien Bourdeauducq 2b8dc52c13 Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq b75fb7f97c csr/SRAM: support for writes with memory widths larger than bus words 2013-03-09 00:50:57 +01:00
Sebastien Bourdeauducq 6fa30053bf fhdl/verilog: tristate outputs are always wire 2013-03-06 11:30:52 +01:00
Sebastien Bourdeauducq 9b4ca987e0 bus/csr: support memories with larger word width than the bus (read only) 2013-03-03 19:27:13 +01:00
Sebastien Bourdeauducq bb5ee8d3bd fhdl/autofragment: bugfixes + add auto_attr 2013-03-03 17:53:06 +01:00
Sebastien Bourdeauducq cc8118d35c fhdl/autofragment: FModule 2013-03-02 23:30:54 +01:00
Sebastien Bourdeauducq d2491828a4 csr/SRAM: prefix page register with memory name 2013-03-01 12:06:12 +01:00
Sebastien Bourdeauducq c10622f5e2 fhdl/verilog: insert reset before listing signals 2013-02-27 18:10:04 +01:00
Sebastien Bourdeauducq d2cbc70190 bank/description: memprefix 2013-02-25 23:14:15 +01:00
Sebastien Bourdeauducq a81781f589 fhdl/specials: allow setting memory name 2013-02-25 23:14:03 +01:00
Sebastien Bourdeauducq 425de02f42 uio/ioo: fix specials 2013-02-25 23:13:38 +01:00
Sebastien Bourdeauducq 55ab01f928 fhdl/specials/Instance: _printintbool -> verilog_printexpr 2013-02-24 13:08:01 +01:00
Sebastien Bourdeauducq a878db1e3c genlib: clock domain crossing elements 2013-02-23 19:03:35 +01:00
Sebastien Bourdeauducq 7c4e6c35e5 fhdl/verilog: support special lowering and overrides 2013-02-23 19:03:16 +01:00
Sebastien Bourdeauducq f9acee4e68 corelogic -> genlib 2013-02-22 23:19:37 +01:00
Sebastien Bourdeauducq 38664d6e16 fhdl: inline synthesis directive support 2013-02-22 19:10:02 +01:00
Sebastien Bourdeauducq 49cfba50fa New 'specials' API 2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq 1b18194b1d fhdl: TSTriple 2013-02-19 17:26:02 +01:00
Sebastien Bourdeauducq dc93a231c6 fhdl: tristate support 2013-02-15 00:17:24 +01:00
Sebastien Bourdeauducq 63d399b6ad fhdl/autofragment: from_attributes 2013-02-11 18:34:01 +01:00
Sebastien Bourdeauducq 92b67df41c sim: default runner to Icarus Verilog 2013-02-09 17:04:53 +01:00
Sebastien Bourdeauducq bd6856ba7a flow/perftools: finish removing ActorNode 2013-02-09 17:03:48 +01:00
Sebastien Bourdeauducq 473fd20f8c fhdl/structure: store clock domain name 2013-01-24 13:49:49 +01:00
Sebastien Bourdeauducq 3201554f76 fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert() 2013-01-23 15:13:06 +01:00
Sebastien Bourdeauducq 314a6c7743 corelogic: complex arithmetic support 2013-01-05 14:18:36 +01:00
Sebastien Bourdeauducq badba89686 fhdl: support nested statement lists 2013-01-05 14:18:15 +01:00
Sebastien Bourdeauducq 47f5fc70e4 pytholite: fix bug with constant assignment to register 2012-12-19 16:21:57 +01:00
Sebastien Bourdeauducq 9c65402fda pytholite: prune unused registers 2012-12-19 16:03:05 +01:00
Sebastien Bourdeauducq 3fae6c8f03 Do not use super() 2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq b06fbdedd6 fhdl/tools: bitreverse 2012-12-14 23:56:16 +01:00
Sebastien Bourdeauducq 1f350adf14 actorlib/sim/SimActor: do not drive busy low when generator yields None 2012-12-14 23:56:03 +01:00
Sebastien Bourdeauducq a67f483f0f Token: support idle_wait 2012-12-14 19:16:22 +01:00
Sebastien Bourdeauducq 6f99241585 Move Token to migen.flow.transactions 2012-12-14 15:55:38 +01:00
Sebastien Bourdeauducq 28b4d99d31 replace some forgotten is_abstract() 2012-12-12 22:36:45 +01:00
Sebastien Bourdeauducq a7227d7d2b Remove ActorNode 2012-12-12 22:20:48 +01:00
Sebastien Bourdeauducq 8163ed4828 Merge branch 'master' of github.com:milkymist/migen 2012-12-06 20:57:30 +01:00
Sebastien Bourdeauducq 483b821342 fhdl/structure: do not create Signal in Instance when parameter is int 2012-12-06 20:56:46 +01:00
Sebastien Bourdeauducq 280a87ea69 elsewhere: do not create interface in default param 2012-12-06 17:34:48 +01:00
Sebastien Bourdeauducq 62187aa23d migen/bank: do not create interface in default param 2012-12-06 17:28:28 +01:00
Sebastien Bourdeauducq c3fdf42825 bus/csr: add SRAM 2012-12-06 17:16:17 +01:00
Sebastien Bourdeauducq e89c66bf14 bank/csrgen: interface -> bus 2012-12-06 17:15:34 +01:00
Sebastien Bourdeauducq 273d9d285b bank/description: define reset value of read signal 2012-12-05 16:40:44 +01:00
Sebastien Bourdeauducq 34ce934809 actorlib/sim: drive busy high until generator is finished 2012-12-05 16:40:12 +01:00
Sebastien Bourdeauducq 4bcb39699b bus/wishbone/sram: accept memories < 32 bits 2012-12-01 13:04:22 +01:00
Sebastien Bourdeauducq 523816982a bus/wishbone: add SRAM 2012-12-01 12:59:09 +01:00
Sebastien Bourdeauducq adb1565d7a pytholite: fix bit width of selection signal 2012-11-30 17:07:32 +01:00
Sebastien Bourdeauducq cfb23c442f pytholite: support signed registers 2012-11-30 17:07:12 +01:00
Sebastien Bourdeauducq 7093939309 corelogic/roundrobin: fix request width (again) 2012-11-29 23:47:51 +01:00
Sebastien Bourdeauducq 31c722f993 corelogic/roundrobin: fix request width 2012-11-29 23:47:08 +01:00
Sebastien Bourdeauducq 70e97e0456 Fix various errors from new bitwidth/signedness system conversion 2012-11-29 23:36:55 +01:00
Sebastien Bourdeauducq 261166d92b fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
2012-11-29 22:59:54 +01:00
Sebastien Bourdeauducq 55d143a454 fhdl/structure: add unary minus 2012-11-29 22:52:57 +01:00
Sebastien Bourdeauducq d8e478efee Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00
Sebastien Bourdeauducq 50ed73c937 New specification for width and signedness 2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq 6eebfce44a Refactor Case 2012-11-29 01:11:15 +01:00
Sebastien Bourdeauducq 070652cc39 pytholite/reg: use source id in dictionary 2012-11-29 00:09:35 +01:00
Sebastien Bourdeauducq fee22a4631 Remove Constant 2012-11-28 23:18:43 +01:00
Sebastien Bourdeauducq 59831e0485 fhdl/structure: improved bits_for function 2012-11-28 18:39:44 +01:00
Sebastien Bourdeauducq 11b1e53224 visit/NodeTransformer: copy most nodes 2012-11-28 17:50:55 +01:00
Sebastien Bourdeauducq a2bcbfdf8f fhdl/tools: use NodeTransformer to lower arrays 2012-11-28 17:46:15 +01:00
Sebastien Bourdeauducq 3bc15024ac fhdl/tools: use NodeVisitor 2012-11-26 21:40:23 +01:00
Sebastien Bourdeauducq e3a983d731 Remove unroll 2012-11-26 20:07:48 +01:00
Sebastien Bourdeauducq 1460f069f6 fhdl/structure: remove deprecated MemoryPort 2012-11-26 19:36:43 +01:00
Sebastien Bourdeauducq 5183774ec8 bus/wishbone2asmi: do not use MemoryPort 2012-11-26 19:14:59 +01:00
Sebastien Bourdeauducq fc85ca53ad actorlib/spi: do not use MemoryPort 2012-11-26 18:27:59 +01:00
Sebastien Bourdeauducq dac0d11e52 actorlib/sim: Dumper 2012-11-24 00:00:07 +01:00
Sebastien Bourdeauducq 27d87c9412 fhdl/structure: disable we_granularity when larger than width 2012-11-23 23:08:12 +01:00
Sebastien Bourdeauducq d2c61e6a90 sim/generic/multiread: do not return spurious items 2012-11-23 23:07:25 +01:00
Sebastien Bourdeauducq 74721b206f pytholite: fix import of _Slice 2012-11-23 21:20:18 +01:00
Sebastien Bourdeauducq 95122bb778 pytholite/io: support memory 2012-11-23 20:36:09 +01:00
Sebastien Bourdeauducq f42683b71e fhdl/structure/Memory: fix we width 2012-11-23 19:21:52 +01:00
Sebastien Bourdeauducq 0f6215a13a fhdl/structure: add Memory.get_port API 2012-11-23 19:17:49 +01:00
Sebastien Bourdeauducq 9d3e218863 fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs. 2012-11-23 18:38:03 +01:00
Sebastien Bourdeauducq 3971600917 fhdl/structure: use sets for memories and instance collections 2012-11-23 17:20:08 +01:00
Sebastien Bourdeauducq f3efd74dfd uio: support memories 2012-11-23 16:23:24 +01:00
Sebastien Bourdeauducq ab31b4d99c bus: memory initiator 2012-11-23 16:22:50 +01:00
Sebastien Bourdeauducq 0b7dd7bdce pytholite/io: fix Wishbone writes + support sel attribute 2012-11-23 13:40:46 +01:00
Sebastien Bourdeauducq 4c216d8f11 pytholite/io: support Wishbone reads 2012-11-23 13:09:55 +01:00
Sebastien Bourdeauducq 0b24a2ff36 pytholite/io: support Wishbone writes 2012-11-23 12:41:50 +01:00
Sebastien Bourdeauducq f098c5c695 pytholite/compiler: pass keyword arguments to gen_io 2012-11-23 12:40:57 +01:00
Sebastien Bourdeauducq 51e2e6ecd0 fhdl/verilog: remove empty cases 2012-11-18 16:32:51 +01:00
Sebastien Bourdeauducq 89643bc434 sim/ipc/Message: convert values 2012-11-17 23:19:40 +01:00
Sebastien Bourdeauducq e92af9de59 pytholite/transel: use python3-compatible comparison methods 2012-11-17 23:16:07 +01:00
Sebastien Bourdeauducq b6b4c5d70e uio/ioo: fix UnifiedIOSimulation 2012-11-17 22:25:42 +01:00
Sebastien Bourdeauducq 1cabcb3c3f uio: support generator trampolining in simulation 2012-11-17 19:59:22 +01:00
Sebastien Bourdeauducq be68ecfc72 uio: add simulation I/O object 2012-11-17 19:55:33 +01:00
Sebastien Bourdeauducq 7add4c6f3c uio: unified I/O object 2012-11-17 19:54:50 +01:00
Sebastien Bourdeauducq d10df1a8ab actorlib/sim: swap TokenExchanger parameters 2012-11-17 19:46:28 +01:00
Sebastien Bourdeauducq d4baac6c0f bus/csr: allow specifying existing interface 2012-11-17 19:44:25 +01:00
Sebastien Bourdeauducq 86090e1cbd bus/asmibus: swap port position to be consistent with wishbone API 2012-11-17 19:42:39 +01:00
Sebastien Bourdeauducq ece786d6aa bus/wishbone: allow specifying existing interface 2012-11-17 19:42:06 +01:00
Sebastien Bourdeauducq d0d4c48098 bus/transactions: add busname parameter 2012-11-17 19:36:08 +01:00
Sebastien Bourdeauducq 897a2e3f9c actorlib/sim: split TokenExchanger 2012-11-17 14:15:51 +01:00
Sebastien Bourdeauducq eb156af20c pytholite/io: support token pull 2012-11-16 23:48:41 +01:00
Sebastien Bourdeauducq dd9a102a78 pytholite/io: support token push 2012-11-16 19:24:45 +01:00
Sebastien Bourdeauducq bf5ce8dc20 pytholite: move expression and register handling to separate modules 2012-11-11 23:48:23 +01:00
Sebastien Bourdeauducq f59fd69e34 pytholite/compiler: recognize composite I/O pattern 2012-11-11 18:03:16 +01:00
Sebastien Bourdeauducq 0b5652bb79 pytholite/compiler: visit_assign_special 2012-11-11 15:52:06 +01:00
Sebastien Bourdeauducq 687d18a150 pytholite: move FSM management to separate module 2012-11-11 14:30:25 +01:00
Sebastien Bourdeauducq 409a5570e4 pytholite/compiler: refactor visit_block 2012-11-11 14:17:52 +01:00
Sebastien Bourdeauducq fb63698ef4 pytholite/compiler: clean up visit_statement 2012-11-10 23:30:14 +01:00
Sebastien Bourdeauducq 6ebd1e4503 pytholite: forward 'yield call' statements to io module 2012-11-10 22:59:14 +01:00
Sebastien Bourdeauducq 48acb1bcfd pytholite: introduce io module 2012-11-10 21:51:19 +01:00
Sebastien Bourdeauducq 6776f06a42 pytholite/compiler: support bitslice 2012-11-10 18:04:05 +01:00
Sebastien Bourdeauducq 37f113c3ea pytholite/compiler: support range(constants) in for loops 2012-11-10 15:26:13 +01:00
Sebastien Bourdeauducq 370bab1190 pytholite/compiler: cleanup print statements 2012-11-10 15:10:57 +01:00
Sebastien Bourdeauducq 39c7dc7d63 pytholite/compiler: support for loops (iterating on lists only) 2012-11-10 15:02:55 +01:00
Sebastien Bourdeauducq 93db3edd00 pytholite/compiler: support while loops 2012-11-10 14:37:33 +01:00
Sebastien Bourdeauducq a901ef46ab Revert "pytholite/compiler: SymbolStack"
This reverts commit f57da497b2.
2012-11-10 12:09:45 +01:00
Sebastien Bourdeauducq f57da497b2 pytholite/compiler: SymbolStack 2012-11-09 23:02:16 +01:00
Sebastien Bourdeauducq 5750c7c07e pytholite/compiler: improve naming of selection signals 2012-11-09 20:19:22 +01:00
Sebastien Bourdeauducq 4921a34616 pytholite/compiler: fix handling of constants 2012-11-09 20:17:57 +01:00
Sebastien Bourdeauducq 26cf1b8840 fhdl: make constants hashable 2012-11-09 20:17:43 +01:00
Sebastien Bourdeauducq c1b8492b61 pytholite/compiler: go to next state 2012-11-09 20:12:15 +01:00
Sebastien Bourdeauducq e1075a962c pytholite/compiler: support if statements 2012-11-09 19:37:52 +01:00
Sebastien Bourdeauducq 92ff5095da pytholite/compiler: support comparisons in expressions 2012-11-09 18:41:32 +01:00
Sebastien Bourdeauducq a645e0b24e pytholite/compiler: create FSM 2012-11-09 17:37:42 +01:00
Sebastien Bourdeauducq 7744655ef2 fhdl/visit: add missing self 2012-11-09 17:37:24 +01:00
Sebastien Bourdeauducq 13af0ce556 fhdl: visit module (untested) 2012-11-09 16:00:11 +01:00
Sebastien Bourdeauducq 9c182c47d1 pytholith: add register muxes 2012-11-08 21:49:20 +01:00
Sebastien Bourdeauducq 18758d87f6 pytholite: do not use ast.NodeVisitor 2012-11-06 13:52:19 +01:00
Sebastien Bourdeauducq 56d4cdeb48 fhdl/structure: make all values hashable 2012-11-06 13:51:51 +01:00
Sebastien Bourdeauducq 3042f047fe pytholite: visit AST and list registers 2012-10-31 15:59:12 +01:00
Sebastien Bourdeauducq b171b3b3c2 pytholite: transformable elements 2012-10-29 18:13:03 +01:00
Sebastien Bourdeauducq 31cdb02eff bank/description: regprefix 2012-10-15 21:21:59 +02:00
Sebastien Bourdeauducq 7a1a781f49 actorlib/spi: typo 2012-10-15 21:21:42 +02:00
Sebastien Bourdeauducq daee4fb58c transform/unroll_sync: autodetect in/out 2012-10-15 20:32:07 +02:00
Sebastien Bourdeauducq fecab5518b transform/unroll_sync: support generator function 2012-10-15 19:42:30 +02:00
Sebastien Bourdeauducq 9efc581bee transform/unroll: support empty dictionaries 2012-10-12 21:54:48 +02:00
Sebastien Bourdeauducq eacba52fba transform/unroll: support for variables 2012-10-12 19:54:03 +02:00
Sebastien Bourdeauducq e5fc9cc675 transform: unroll 2012-10-12 13:16:39 +02:00
Sebastien Bourdeauducq d329d40fe9 actorlib/spi: SingleGenerator 2012-10-09 21:11:15 +02:00
Sebastien Bourdeauducq c473718a12 actorlib/spi/collector: atomic update for write_count 2012-10-09 19:08:09 +02:00
Sebastien Bourdeauducq 85081793cf bank: remove RE signal for field registers 2012-10-09 19:07:53 +02:00
Sebastien Bourdeauducq e410973352 bank: support for atomic writes 2012-10-08 18:43:18 +02:00
Sebastien Bourdeauducq 24877f271b actorlib/spi: fix memory port we/wd 2012-10-04 20:10:24 +02:00
Sebastien Bourdeauducq 035870703f flow/actorlib: Simple Processor Interface (WIP) 2012-10-04 18:22:22 +02:00
Sebastien Bourdeauducq 8101b68965 fhdl: fix instance get_io 2012-09-28 18:02:03 +02:00
Sebastien Bourdeauducq c273866b08 fhdl: support expressions in instance ports 2012-09-22 20:51:10 +02:00
Sebastien Bourdeauducq 2fc9cae88a fhdl: support inverted clock ports in instances 2012-09-22 20:50:49 +02:00
Sebastien Bourdeauducq 2e14569b5c fhdl/verilog: sort clock domains by name 2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq 9a18a9df3f fhdl: list signals in execution order 2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq e16353a281 Multi-clock design support + new instance API 2012-09-10 23:45:02 +02:00
Sébastien Bourdeauducq 6490785b6c Merge pull request #3 from brandonhamilton/upstream
Optionally accept iverilog simulator options
2012-09-09 10:52:52 -07:00
Sebastien Bourdeauducq b45c9546eb fhdl/namer: better handling of indices 2012-09-09 19:33:55 +02:00
Sebastien Bourdeauducq 589251fffd fhdl/tracer: support BUILD_LIST opcode 2012-09-09 18:53:24 +02:00
Sebastien Bourdeauducq 910c350021 fhdl/namer: use execution order indices for variable names as well 2012-09-09 17:31:35 +02:00
Sebastien Bourdeauducq f3e3a3eec7 fhdl/namer: number objects according to execution order 2012-09-09 12:27:32 +02:00
Sebastien Bourdeauducq 51f9a2a963 fhdl/namer: simplify + more relevant names 2012-09-09 01:26:33 +02:00
Sebastien Bourdeauducq 4164fb4ac9 bus/csr: configurable data width 2012-08-26 21:19:34 +02:00
Sebastien Bourdeauducq 5bf19c155f sim: ensure clean IPC shutdown 2012-08-05 00:16:11 +02:00
Sebastien Bourdeauducq 47c341ecdf flow/isd: add freeze register 2012-08-04 23:39:52 +02:00
Sebastien Bourdeauducq 6de517f59c flow/network: remove print 2012-08-03 18:50:57 +02:00
Sebastien Bourdeauducq 25cb25a8ae flow/network: option to add debugger 2012-08-03 18:49:35 +02:00
Sebastien Bourdeauducq fd0e281dfc flow: in-system debugger module 2012-08-03 18:49:04 +02:00
Sebastien Bourdeauducq adacdadd58 flow/hooks/DFGHook: add iterator on hooks 2012-08-03 18:48:35 +02:00
Sebastien Bourdeauducq 37fe6d64c3 flow: EndpointHook -> EndpointSimHook 2012-08-03 12:58:41 +02:00
Sebastien Bourdeauducq 30f1e77c18 corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time 2012-07-13 20:21:04 +02:00
Sebastien Bourdeauducq 8de192dfbd x.bv.width -> len(x) 2012-07-13 18:32:54 +02:00
Sebastien Bourdeauducq 9cdc88eadf fhdl: len() for Constant 2012-07-13 18:16:50 +02:00
Sebastien Bourdeauducq 8c169a99df corelogic/misc: remove multimux 2012-07-13 18:05:57 +02:00
Sebastien Bourdeauducq 599ed8d470 fhdl: fix value_bv for operators 2012-07-13 17:40:49 +02:00