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VexRiscv
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409 Commits

Author SHA1 Message Date
Dolu1990 6bc5431fcd Add iBusCached regressions 2018-06-07 00:57:26 +02:00
Dolu1990 5e7dd02bf7 Fix relaxedPc/DYNAMIC_TARGET interaction 2018-06-06 18:30:30 +02:00
Dolu1990 dc968020c4 Fix relaxedBusCmdValid pendingCmd overflow 2018-06-06 15:20:37 +02:00
Dolu1990 7768f065e4 Add many cpu configs on regressions tests (some config are broken) 2018-06-06 02:23:07 +02:00
Dolu1990 8729530a8d Fix Dynamicfetch/!rvc config 2018-06-05 02:33:18 +02:00
Dolu1990 930563291c Allow RVC/dynamic_target/fetch bus latency > 1 all together 
Fix freeretos rvc regressions
 2018-06-05 02:21:05 +02:00
Dolu1990 702db29edd Fix dynamic prediction RVC allignement 2018-06-04 20:03:08 +02:00
Dolu1990 fc835f370e Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function 2018-06-04 19:45:15 +02:00
Tom Verbeure 52f1cdbca7 Fix some missing Barriel -> barriel fixes 2018-06-03 21:46:40 -07:00
Dolu1990 9f0387350b Add Freertos RVC binaries regression 2018-06-03 17:10:58 +02:00
Tom Verbeure e9bbbb3965 BarrielShifter -> BarrelShifter 2018-06-03 07:40:11 +00:00
Dolu1990 7375855e58 DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch) 2018-06-03 00:50:18 +02:00
Dolu1990 98b68093f4 dynamic_prediction + RVC => instruction fetch stopped midair 2018-05-28 21:28:39 +02:00
Dolu1990 863ac3f34d dynamic prediction now use history from first aligned word of the instruction instead of the last one. 2018-05-28 11:03:13 +02:00
Dolu1990 8a0c238bf3 dynamic prediction ok with rvc, todo dynamic_target with rvc 2018-05-28 10:59:22 +02:00
Tom Verbeure 0335543309 More Unrolls 2018-05-28 07:20:26 +00:00
Tom Verbeure 1613191779 Unrool -> Unroll 2018-05-28 07:18:13 +00:00
Dolu1990 7493e70265 Merge remote-tracking branch 'origin/master' into reworkFetcher 2018-05-28 09:02:30 +02:00
Dolu1990 5943ee727e Fill travis, DhrystoneBench is now a Unit test 2018-05-28 09:02:01 +02:00
Dolu1990 1752b5f184 Give name to inter stages registers 2018-05-27 23:39:49 +02:00
Dolu1990 5704f22739 wip 2018-05-27 23:33:57 +02:00
Dolu1990 346338f084 Better HexTools 2018-05-26 11:51:42 +02:00
Dolu1990 6142b04603 Move HexTools into Spinal 2018-05-26 11:43:16 +02:00
Dolu1990 c8677cca9b Better HexTools 2018-05-26 11:32:36 +02:00
Dolu1990 b0777bc646 Merge remote-tracking branch 'origin/master' into reworkFetcher 2018-05-24 14:05:35 +02:00
Dolu1990 6004dcc365 Fix typo 2018-05-24 14:04:50 +02:00
Dolu1990 9815763b7f Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
	src/test/cpp/regression/main.cpp
 2018-05-24 14:04:01 +02:00
Dolu1990 c4f33b30e2 Update SynthesisBench murax 2018-05-24 14:03:28 +02:00
Dolu1990 485f35a1b5 IBusCachedPlugin default is two cycle cache with single cycle ram. 2018-05-24 13:46:31 +02:00
Dolu1990 2f8ccc55b6 Fix branch plugin decode prediction exception by using the instruction decoder 2018-05-24 12:52:00 +02:00
Dolu1990 a53f8fdc35 Clean configs 2018-05-23 16:57:32 +02:00
Dolu1990 eb5bc4a791 Fix RVC decompressor (ALU immediats) 2018-05-22 17:23:20 +02:00
Dolu1990 ff760a0bf0 DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS) 2018-05-21 13:45:08 +02:00
Dolu1990 7ffbfab312 Reintroduce MMU feature (pass tests) 2018-05-16 20:32:12 +02:00
Dolu1990 c8cec59f1d Update IBusCachedPlugin parameters 2018-05-16 12:11:53 +02:00
Dolu1990 3b54ecf303 Restore two cycle instruction cache features 2018-05-15 23:03:33 +02:00
Dolu1990 4e7152ae5a IcestormFlow add ultraplus support 2018-05-14 20:18:53 +02:00
Dolu1990 df3d9ccb13 rework IBusSimplePlugin parameters 2018-05-14 10:31:40 +02:00
Dolu1990 c0271d382f More assertion (csrPlugin) 2018-05-14 10:13:44 +02:00
Dolu1990 9caa7163ae IBusSimplePlugin add relaxedBusCmdValid feature 2018-05-14 10:04:19 +02:00
Dolu1990 610bd01f3b remove rspStageGen 2018-05-14 09:21:28 +02:00
Dolu1990 7b37669a0f Add exception catch to iBusSimplePLugin (pass) 2018-05-09 18:43:48 +02:00
Dolu1990 acccbf40e2 RVC debug pass tets 2018-05-09 00:28:14 +02:00
Dolu1990 0056da1342 DebugPlugin work 2018-05-08 02:01:34 +02:00
Dolu1990 e65757e34c wip before moving the fetchHalt 2018-05-06 16:38:00 +02:00
Dolu1990 294293cb70 Reintroduce debug plugin (instruction injector need optimisations) 2018-05-05 23:05:32 +02:00
Dolu1990 a50fbf0d7a Fix IBusCachedPlugin Pass all dhrystone tests 2018-04-30 13:35:17 +02:00
Dolu1990 558af595a1 Add ice40 synthesis results 2018-04-26 13:14:37 +02:00
Dolu1990 bdcf3f6234 Add HexTools and add a Briey main which load the ram 2018-04-26 10:27:39 +02:00
Dolu1990 cfc324aa0f Allow csr mtvec to not have reset values 2018-04-24 23:33:48 +02:00
Dolu1990 a9cbc48eb2 PcManagerPlugin is can now handle an external reset vector signal 2018-04-24 23:11:11 +02:00
Dolu1990 978eb9b6b2 DBusCachedPlugin add CSR info 2018-04-22 11:46:01 +02:00
Dolu1990 74f2a4194a Add ExternalInterruptArrayPlugin 2018-04-20 17:56:21 +02:00
Dolu1990 6598e82920 wishbone => word address, not byte address 2018-04-19 11:22:06 +02:00
Dolu1990 455607b6b4 Fix dBus IO access 2018-04-18 14:11:59 +02:00
Dolu1990 6e59ddcc73 Cached wishbone demo is passing regression tests 2018-04-18 13:51:33 +02:00
Dolu1990 b37fc3fcc8 Add VexRiscv Wishbone demo for sim (generation ok) 2018-04-18 12:54:20 +02:00
Dolu1990 a66efcb35b Add wishbone support for i$ / d$ (not tested) 2018-04-17 23:56:44 +02:00
Dolu1990 4440047fb6 ICache compressed is working 2018-04-16 10:34:18 +02:00
Dolu1990 76352b44fa wip 2018-04-13 12:51:27 +02:00
Dolu1990 19d5d1ecf1 wip 2018-04-09 09:18:08 +02:00
Dolu1990 4dd2997ad5 wip 2018-04-09 09:12:30 +02:00
Dolu1990 e00c0750eb wip 2018-04-03 18:37:05 +02:00
Dolu1990 d9f2e03753 statuc prediction is fully funcitonnal 2018-04-02 17:43:58 +02:00
Dolu1990 76ca852478 Static prediction is fully functionnal 2018-04-02 17:43:06 +02:00
Dolu1990 0919308a8f IBusSimplePlugin add relaxedPcCalculation 2018-03-23 22:49:32 +01:00
Dolu1990 c48c7170e8 Added many pipelining option into IBusSimplePlugin 2018-03-23 19:07:03 +01:00
Dolu1990 351ad10925 RVC Add dhrystone regressions (PASS) 2018-03-21 23:36:57 +01:00
Dolu1990 0c7c2a1fba IBusPlugin add support of bus error when using compressed instruction 2018-03-21 22:34:54 +01:00
Dolu1990 31a464ffdc VexRiscv now pass Riscv-test compressed stuff 2018-03-21 20:50:07 +01:00
Dolu1990 af638e7bde RV32IC is passing some of the compressed Riscv-test tests 2018-03-21 20:30:09 +01:00
Dolu1990 f872d599e2 Add decodePcGen 2018-03-20 18:34:36 +01:00
Dolu1990 1fb138de1f IBusSimplePlugin fully functional Need to restore branch prediction 2018-03-20 00:01:28 +01:00
Dolu1990 ac74fb9ce8 iBusSimplePlugin done, DebugPlugin need minor rework 2018-03-18 13:21:21 +01:00
Dolu1990 64022557bf Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl 2018-03-15 18:56:25 +01:00
Dolu1990 63c1b738ff Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings 2018-03-14 00:56:23 +01:00
Dolu1990 d9b7426cde undo InOutWrapper from Murax 2018-03-14 00:47:23 +01:00
Dolu1990 91031f8d75 DivPlugin is now based MulDivIterativePlugin (Smaller) 2018-03-10 13:31:35 +01:00
Dolu1990 e437a1d44e Add division support in the MulDivInterativePlugin 2018-03-09 22:41:47 +01:00
Dolu1990 36438bd306 iterative mul improvments 2018-03-09 20:00:50 +01:00
Dolu1990 674ab2c594 experimental iterative mul/div combo 2018-03-09 19:07:26 +01:00
Dolu1990 5228a53293 MuraxSim improve simulation Speed 2018-03-06 12:20:39 +01:00
Dolu1990 9b2cd7b234 MuraxSim add switch 2018-03-06 12:17:15 +01:00
Dolu1990 53970dd284 SpinalHDL 1.1.4 
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
 2018-03-05 14:34:59 +01:00
Dolu1990 ccad64def5 Pipeline CSR isWrite 2018-02-26 10:19:33 +01:00
Dolu1990 2b6185b063 Decoding logic : Add primes duplication removal 2018-02-25 08:57:31 +01:00
Dolu1990 2b6f43cef8 Fix Murax memory mapping range 2018-02-25 08:57:31 +01:00
Dolu1990 5260ad5c35 Decoding lib cleaning 2018-02-25 08:57:31 +01:00
Dolu1990 137b1ee32c Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values 2018-02-22 22:36:13 +01:00
Dolu1990 d957934949 Fix ICache exception priority over miss reload 2018-02-19 22:44:46 +01:00
Dolu1990 d0e963559a Update readme with the new ICache implementation 2018-02-18 23:48:11 +01:00
Dolu1990 93110d3b95 Add jump priority managment in PcPlugins 2018-02-16 14:27:20 +01:00
Dolu1990 506e0e3f60 New faster/smaller/multi way instruction cache design. 
Single or dual stage
 2018-02-16 02:21:08 +01:00
Dolu1990 3853e0313b SynthesisBench cleaning/experiments 2018-02-11 14:53:42 +01:00
Dolu1990 0e6ae682b1 Add architecture section describing plugins in the readme 2018-02-09 00:44:27 +01:00
Dolu1990 57ebfee2e6 Add more axi bridges 2018-02-08 21:39:22 +01:00
Dolu1990 3ee111e100 Update readme (gcc stuff) 2018-02-05 16:34:10 +01:00
Dolu1990 d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location 
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
 2018-02-05 16:16:27 +01:00
Dolu1990 4729e46763 Add DummyFencePlugin 2018-02-03 12:28:53 +01:00
Dolu1990 f13dba847c Add custom csr gpio example 2018-02-02 11:14:55 +01:00
Dolu1990 b7d8ed8a81 Add onWrite/onRead/isWriting/isReading on the CsrPlugin 2018-02-01 21:28:28 +01:00
Dolu1990 4ee2482cbf Fix custom_csr regression against random ibus stall 2018-01-31 18:33:21 +01:00
Dolu1990 d2e5755df4 revert removed code by mistake 2018-01-31 18:29:30 +01:00
Dolu1990 30b05eaf96 Add CsrInterface to allow custom CSR addition 
Add CustomCsrDemoPlugin as a show case
 2018-01-31 18:13:42 +01:00
Dolu1990 bdbf6ecf17 BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions 2018-01-29 14:52:31 +01:00
Dolu1990 0d318ab6b9 Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) 
Add longer timeouts in the regressions tests
 2018-01-29 13:17:11 +01:00
Dolu1990 307c0b6bfa Now mret and ebreak are only allowed in CSR machine mode 2018-01-28 16:34:55 +01:00
Dolu1990 93da5d29bc Fix dhrystone referance log 2018-01-28 16:34:55 +01:00
Dolu1990 26732942e5 Update DMIPS/Mhz 
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
 2018-01-25 01:11:57 +01:00
Dolu1990 3b3bbd48b9 SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 18:29:33 +01:00
Dolu1990 6a521a8d13 Better MuraxSim gui 
Add MuraxSim in the readme
 2018-01-09 08:59:17 +01:00
Dolu1990 9a89573942 SpinalHDL 1.1.2 
Add Murax setup with Mul Div Barriel
 2018-01-06 22:09:42 +01:00
Dolu1990 43d3ffd685 CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure 2018-01-04 17:37:23 +01:00
Dolu1990 2b7465e5df Add more atomic tests (PASS) 2018-01-04 16:16:22 +01:00
Dolu1990 611f2f487f Fix DataCache atomic integration into DBusCachedPlugin 
Atomic is passing basic tests
 2018-01-04 15:24:00 +01:00
Dolu1990 4637e6cb48 Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. 
add Atomic test flow
 2018-01-04 14:43:30 +01:00
Dolu1990 468dd3841e Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer 2018-01-04 13:16:40 +01:00
Dolu1990 4ed19f2cc5 SpinalHDL 1.1.1 2017-12-30 03:36:57 +01:00
Dolu1990 0d39e38906 SpinalHDL 1.1.0 2017-12-28 13:49:39 +01:00
Dolu1990 3c0588eb4b remove MuraxSim fixed path 2017-12-19 22:33:46 +01:00
Dolu1990 7f2b2181c1 SpinalHDL 1.0.3 2017-12-19 21:21:16 +01:00
Dolu1990 37849b7a66 Spinal 1.0.2 sim update 2017-12-19 00:40:52 +01:00
Dolu1990 ebda7526b5 MuraxSim 1.0.0 2017-12-17 17:57:09 +01:00
Dolu1990 dda5372a6c Fix typo 2017-12-14 01:05:06 +01:00
Dolu1990 d6e0761065 Fix led gui refresh rate 2017-12-14 01:04:31 +01:00
Dolu1990 2259c9cb0f Add SpinalHDL sim (1.0.0) 2017-12-14 00:57:12 +01:00
Dolu1990 e1b86ea511 SpinalHDL 0.11.4 update 2017-12-01 11:19:23 +01:00
Dolu1990 586d3ed286 Update formal VexRiscv to halt on missaligned dbus 2017-11-26 15:30:48 +01:00
Dolu1990 4de0aac469 Merge branch 'formal' 2017-11-24 14:03:25 +01:00
Dolu1990 b7f4f09814 Update verilator makefiles to support the last SpinalHDL changes (process merges) 2017-11-21 23:56:46 +01:00
Dolu1990 9b9bbaa4ad Add missing full config for the iBus 2017-11-21 00:09:02 +01:00
Dolu1990 ce6fd6d0aa Add VexRiscvAxi4 demo 2017-11-20 23:57:37 +01:00
Dolu1990 7c19288648 Update Synthesis bench 
Update some synthesis results
 2017-11-17 20:10:46 +01:00
Tony Kao 290dbc106e Fixes GPIO width mismatch 
Adds explicit type to apbDecoder.slave to suppress IDE errors
 2017-11-16 15:02:13 -05:00
Dolu1990 6c3fed3505 SpinalHDL 0.11.1 2017-11-15 16:44:42 +01:00
Dolu1990 be3d301eaf Merge remote-tracking branch 'origin/spinalhdl_reworkDev' 2017-11-12 13:08:05 +01:00
Dolu1990 838c13d68b spinal.core.internals literals import 2017-11-10 13:14:30 +01:00
Dolu1990 3060296b94 unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch 2017-11-10 11:33:04 +01:00
Dolu1990 c3a7f4e58c CSR unsetRegIfNoAssignement fix 
BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
 2017-11-10 00:59:31 +01:00
Dolu1990 d6777ae8ec usetRegIfNoAssign upgrade 2017-11-09 20:10:56 +01:00
Dolu1990 a72c7fd0d1 Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala 2017-11-07 22:19:33 +01:00
Dolu1990 714d44d248 Add fixed bug into the FormalPlugin comments 2017-11-07 13:54:07 +01:00
Dolu1990 200a73bea0 Fix FormalPlugin to pass liveness again. 2017-11-06 23:04:33 +01:00
Dolu1990 8098a03a9b with no bus stall, pass all tests except uniqueness 2017-11-06 20:26:45 +01:00
Dolu1990 e2a432eb5e add HaltOnExceptionPlugin 
wip
 2017-11-05 20:13:27 +01:00
Dolu1990 276f7895e7 Add FormalPlugin 
Add FormalSimple CPU configuration
 2017-11-04 00:55:32 +01:00
Dolu1990 ba42f71813 pass VexRiscv regressions 2017-10-30 14:29:25 +01:00
Ubuntu 008a5b7309 updated main.cpp 
added missing using namespace std
 2017-10-17 22:09:08 +00:00
Dolu1990 2bf7ca24f2 Add VexRiscvAvalonWithIntegratedJtag 2017-10-16 11:52:17 +02:00
Dolu1990 aa859aae6b Update framework.h 
Add missing using namespace std;
 2017-10-05 10:08:09 +02:00