ba42f71813
pass VexRiscv regressions
2017-10-30 14:29:25 +01:00
008a5b7309
updated main.cpp
...
added missing using namespace std
2017-10-17 22:09:08 +00:00
2bf7ca24f2
Add VexRiscvAvalonWithIntegratedJtag
2017-10-16 11:52:17 +02:00
aa859aae6b
Update framework.h
...
Add missing using namespace std;
2017-10-05 10:08:09 +02:00
09ba7c28da
Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)
2017-08-27 15:21:44 +02:00
8168c9bf3a
Update simd_add makefile
2017-08-27 14:49:36 +02:00
2c6889e688
Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU
...
Murax add dhrystone config
2017-08-10 22:48:00 +02:00
aa477b2b1c
DebugPlugin now prevent the CPU catching exception when debug instruction are pushed
...
Fix DataCache locking when loading mem read rsp transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
2017-08-10 20:56:54 +02:00
1653548140
Better readme about custum instruction testing
2017-08-08 18:36:23 +02:00
54b06e6438
Add SIMD_ADD regression and config (show case)
2017-08-08 18:19:02 +02:00
3307d6c3b5
Briey move CPU and UART generics from to toplevel to the toplevel configuration object
2017-08-06 15:42:37 +02:00
671aa5050e
Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)
...
Add MuraxConfig.fast
2017-08-04 14:55:54 +02:00
ac59eebb8d
Add Murax configuration which integrate a boot programme :
...
Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
2017-08-03 21:58:23 +02:00
58981c0e8e
Add Murax fast in synthesis bench
2017-08-01 21:14:09 +02:00
f44b345132
Add console TX in the Murax verilator
2017-07-31 21:04:41 +02:00
0c9a39d3ce
Connect the UART interruption to the CPU
2017-07-31 17:20:47 +02:00
c16a53c388
Refractoring of some arbitration signals
...
Add UART into Murax
2017-07-31 13:34:25 +02:00
8708d2482f
Add more information about dependencies
2017-07-30 11:37:22 +02:00
de33128e01
Add Murax 0.55 DMIPS/Mhz
2017-07-30 02:42:14 +02:00
e8aa828744
PcPlugin change fastPcCalculation into relaxedPcCalculation
...
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
2017-07-29 21:36:30 +02:00
3b66d986a8
Fix cpu sending instruction memory request while being halted by the DebugPlugin
2017-07-29 18:20:22 +02:00
43253f61c1
Update Murax info
2017-07-29 02:52:57 +02:00
fa887d3830
Add pipelining option (hit 60 Mhz)
2017-07-29 02:52:03 +02:00
3bdf020c67
Add interrupts and timer to Murax
...
8KB ram is the default now
2017-07-29 01:59:17 +02:00
823ac353ff
Add Murax SoC (very light, work on ice40)
2017-07-28 21:25:49 +02:00
1450077b70
Add Murax SoC (wip)
2017-07-28 14:16:30 +02:00
493f7721cb
All FreeRTOS tests are now passing
2017-07-28 00:07:51 +02:00
800e9e79a5
freertos regression now include O0 and O3 for rv32i and rv32im
2017-07-27 01:23:50 +02:00
6b3e2dbe7d
Add FreeRTOS test regression (FREERTOS=yes)
...
Multithreaded regression
2017-07-26 23:38:59 +02:00
10d282b2ef
Add DBusSimple early injection feature (better DMIPS)
2017-07-26 23:36:25 +02:00
6d117f5c81
Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages)
...
freeRTOS pass
2017-07-23 22:58:26 +02:00
9fe4e1d54d
Package refractoring VexRiscv -> vexriscv Plugin -> plugin
2017-07-23 13:28:17 +02:00
4b5bf7d807
Briey Area down by 10% by spliting the memory system in two (System, Debug)
2017-07-23 01:11:33 +02:00
37c338ec98
Avalon add read response support.
...
Fix debug instruction injection and IBusSimplePlugin interraction
2017-07-21 20:39:54 +02:00
54f785b1a3
Add full avalon support (pass regression)
2017-07-21 17:40:45 +02:00
52f5020e64
Rename some regression commands
...
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
2017-07-21 14:32:49 +02:00
575a410786
Avalon regression (WIP)
2017-07-20 14:20:19 +02:00
570f0e1e3e
D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax
2017-07-20 14:20:19 +02:00
8643086fc0
Add Briey area and timings into readme
2017-07-19 18:34:16 +02:00
42e546ecd9
Add fullNoMmuNoCache config
2017-07-17 16:45:06 +02:00
fcec6cba86
revert test changes
2017-07-17 15:26:37 +02:00
617861ee6c
Add smallAndProductive
2017-07-17 15:25:56 +02:00
99c3397243
readme, better plugin example
2017-07-17 14:19:28 +02:00
84bba3adf0
REG1/REG2 refractoring RS1/RS2
...
Add CustomeInstruction example
2017-07-17 14:02:56 +02:00
708a8f66de
typo fixes
2017-07-17 14:01:35 +02:00
79c2972076
Update bench config with realistic embedded CSR
2017-07-16 14:34:42 +02:00
53300c4116
Add area and FMax in readme
...
Add Synthesis bench
2017-07-16 13:50:19 +02:00
37ea699c55
Add Synthesis bench
2017-07-16 03:29:50 +02:00
6930e76042
Remove mepc from smallest CSR config
...
Better readme
2017-07-16 00:44:23 +02:00
bc792a8655
Fix UartRx sim
2017-07-15 19:05:34 +02:00
74becb6633
Add VexRiscvAvalon QSysify
2017-07-15 09:41:39 +02:00
12d21a08e8
Add DebugPlugin avalon
2017-07-14 19:28:22 +02:00
d3dcfcec06
Add toAvalon bridge to cached bus
...
Add VexRiscvAvalon demo
2017-07-14 18:04:41 +02:00
f51f28164a
Fix info to flush data cache
...
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
2017-07-09 01:00:46 +02:00
8d34c04425
Fix CsrPlugin case issue
...
Better DBusSimplePlugin FMax with catch enables
SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
2017-06-27 19:37:46 +02:00
e9ab3d71d5
update readme
...
add uart.elf binary for testing
2017-06-26 14:44:52 +02:00
4d7455f9c3
add retiming to the dataCache waysHit
...
Add exception catches in the default briey configuration
2017-06-26 14:02:25 +02:00
e9e7cf9e7a
Add briey tracing
...
Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
2017-06-24 14:09:12 +02:00
edf1b4ed5a
Cleaning, better jtag perf
2017-06-18 16:10:27 +02:00
bc90331c49
Cleaning
2017-06-15 13:54:34 +02:00
88a2c4a603
Cleaning/Add documentation
2017-06-15 13:44:21 +02:00
835dd4ad50
Add CSR
2017-06-15 11:16:11 +02:00
f8678698fc
Briey improve AXI FMax
...
Faster debugginPlugin regression
2017-06-11 11:52:59 +02:00
cbc770deb3
Improve TCP sockets latency
2017-06-10 19:38:42 +02:00
9b9d9e2582
Add Uart monitor in the briey testbench
2017-06-10 16:09:14 +02:00
11a63491bd
Add YAML feature to store CPU info
2017-06-09 16:06:18 +02:00
4b9668c063
Remove speed factor overriding when Trace
2017-06-09 08:41:12 +02:00
f46ec583d6
Briey is now working with DataCache on FPGA
2017-06-07 23:02:34 +02:00
8dcf5cf68a
Add missing import in Briey testbench
2017-06-07 16:56:29 +02:00
8da413dec3
Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK)
...
Add SDRAM Verilator model
2017-06-07 04:19:35 +02:00
1e18daecc0
Add ICache and DCache axi bridges functions
...
Add StaticMemoryTranslationPlugin
2017-06-01 17:54:56 +02:00
ac16558b6b
Add haltItByOther
...
Axi4, remove some pipelining
2017-05-30 17:49:29 +02:00
6b62d8da52
VexRiscv in Briey SoC is working on FPGA (including jtag debugging)
2017-05-29 21:17:14 +02:00
213e154b40
Fix regression test debugPlugin bus
2017-05-28 17:41:09 +02:00
8dddc7e334
GDB + openOCD successfully connect !
2017-05-25 13:36:54 +02:00
75f6b78daf
OpenOCD successfuly connected to target
2017-05-24 23:53:31 +02:00
1efed60307
Fix DebugPlugin
...
Add DebugPlugin regression (PASS)
2017-05-22 19:23:11 +02:00
cc875d1c0b
Add TCP server socket to manage debug access from openOCD (as instance)
2017-05-22 00:42:19 +02:00
5cda2632df
Start implementing debugPlugin test infrastructures
2017-05-21 23:50:40 +02:00
9995c5109d
move tests
2017-05-21 16:53:48 +02:00
6c1d953647
DebugPlugin fully implemented
2017-05-20 18:15:15 +02:00
619739d33a
preliminary DebugPlugin
2017-05-20 15:16:45 +02:00
a5364ad001
Add flush support instruction into the instruction cache
2017-05-19 11:20:33 +02:00
736478ff1d
CsrPlugin now catch illegal CSR access (wrong address + to low privilege level)
2017-05-09 00:40:44 +02:00
fe184636dd
Improve CsrPlugin FMax
2017-05-08 22:59:05 +02:00
c69fdf7987
Add basics of the USER mode to CsrPlugin
2017-05-07 23:41:54 +02:00
579e93bb5a
Rename MachineCsr plugin into CsrPlugin
2017-05-07 22:26:17 +02:00
392f3a7d8c
Add PrivilegeService (User) (not implemented)
...
Split caches from their plugins file
2017-05-07 20:16:41 +02:00
a51c27970b
Add opcode for clean/invalidate the datacache
...
Change mmu opcodes
2017-05-07 16:02:55 +02:00
4d6a6fbb02
Fix Instruction Data cache exceptions
...
Pass all tests including CSR/FreeRTOS
2017-05-07 12:51:47 +02:00
ca1bc9cf69
DataCache plugin now support all exceptions
2017-05-07 10:44:41 +02:00
5ba8ab7947
DataCache add invalidate/clean/invalidateClean on a virtual address/way
2017-05-05 00:43:41 +02:00
48a5dc8e79
DCache move the exception bus outside the cache component
2017-05-04 21:01:08 +02:00
534a4c3494
mmu working for instruction and data bus (both tested)
2017-05-03 18:42:54 +02:00
c647ef8bb6
Rework constructors
2017-05-01 20:20:21 +02:00
889a040f90
Fix multi port MMU design
...
Change machineCSR to handle exceptions from the writeBack stage
Change the DBusCachedPlugin to emit miss exception
2017-05-01 14:29:37 +02:00
2ed33106d6
MMU pass simple regression !
2017-04-29 19:58:17 +02:00
227772f19c
Add miss files
2017-04-28 16:41:44 +02:00
010ba568f0
MMU implemented
...
Datacached using MMU implemented
It compile, but nothing is tested
2017-04-28 16:41:23 +02:00
ba2ca77114
Two stage datacache now pass dhrystone benchmark without error
2017-04-23 23:15:38 +02:00
9040326273
WIP two stage DCache, nearly passed the dhrystone benchmark
2017-04-23 18:31:16 +02:00
e00bf028cb
Add HazardPessimisticPlugin for light and very good FMAX hazard tracking
2017-04-17 17:56:47 +02:00
024e14ae58
Smaller and faster single stage instruction cache
...
Add fast two stage instruction cache
Remove useless address == 0 checks in the HazardPlugin
2017-04-13 18:27:03 +02:00
c83a157c64
IBusCachedPlugin with twoStage config is now compatible with syncronous regfile
2017-04-09 11:59:09 +02:00
9a4c35d7b6
IBusCachedPlugin twoStage config fix
2017-04-08 18:34:44 +02:00
e3b9e671ec
IBusCachedPlugin add two stage cache option for better FMax and better scaling
2017-04-08 17:42:13 +02:00
5c594d6d2a
IBusCachedPlugin move memory access outside the pipeline
2017-04-07 13:27:47 +02:00
8f09867bda
Cleaning
2017-04-07 13:09:31 +02:00
efb27390a7
Better IntAluPlugin
...
Better SrcPlugin
Better DBusCachedPlugin
2017-04-06 01:28:52 +02:00
2e02a6f0e7
DBusCachedPlugin better write to read hazard logic (FMAX)
...
Add some TODO FMAX comments
2017-04-05 18:37:02 +02:00
179e7f7b4c
IBusCachedPlugin add asyncTagMemory option
2017-04-05 14:25:11 +02:00
2b24cbc8e1
Add pessimistic harzard options
...
Add separated add/sum option in srcPlugin
2017-04-04 00:25:39 +02:00
acb85a1fb8
Add some decoder comments
2017-04-03 01:33:54 +02:00
8ff05bd2a8
Much better decoder using Quine-Mc Cluskey
2017-04-02 21:05:25 +02:00
a9f7177181
Data cache pass dhrystone benchmark.
...
Data cache todo -> bus error handling
2017-04-01 17:06:59 +02:00
2f384364d8
Data cache WIP
...
refractoring
2017-03-31 15:20:51 +02:00
26597f78cd
cleaning
2017-03-31 11:06:40 +02:00
19fe998a52
Instruction cache is now able to catch bus errors
2017-03-30 17:34:24 +02:00
95585b4d9a
Add instruction cache plugin (tested)
2017-03-30 10:03:53 +02:00
32d32845bd
Add tests for iRsp, dRsp access faults
2017-03-28 20:25:58 +02:00
2cb0e90077
refractoring/cleaning
2017-03-28 01:53:37 +02:00
62a55c4cf4
Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions
2017-03-28 01:24:29 +02:00
eecc1e6b18
Add MachineCsr.mbadaddr logics
2017-03-27 18:35:27 +02:00
349d600182
Better readme
...
cleaning
2017-03-27 00:33:34 +02:00
91c52f4e46
Decoder now catch illegal instructions
2017-03-26 18:02:48 +02:00
c5520656e5
Now able to catch missaligned instruction/data addresses
...
Modify arbitration with an flushAll + isFlushed
2017-03-26 17:20:07 +02:00
4000191966
FreeRTOS tested
...
removeIt no more colapse bubbles
2017-03-25 16:44:42 +01:00
9bbf3ee3e7
MachineCsr fix csr set/clear with zero
...
MachineCsr pass external/timer interrupts test
2017-03-24 17:40:37 +01:00
72d65841d2
MachineCsr pass simple interrupt and exception tests
2017-03-23 23:12:44 +01:00
ed0660237f
MachineCsr wireing/logic done
2017-03-23 01:00:24 +01:00
de4c2470c8
MachineCsr add mcycle and minstret
2017-03-22 20:38:43 +01:00
94770f8e0b
Add MachineCsr (untested)
2017-03-22 18:29:34 +01:00
e9d3977737
Add Arbitration.flushIt
...
Add ExceptionService
Add unremovableStage
Add MachineCsr (untested)
2017-03-21 18:40:50 +01:00
c49373f3d1
Fix missing JAL, JALR encoding
2017-03-21 10:29:09 +01:00
787682d4f6
Add comments
...
Some refractoring
2017-03-20 14:49:49 +01:00
51058f851e
Renaming
2017-03-20 12:37:53 +01:00
ecf853f491
Add Static/Dynamic branch prediction
2017-03-20 12:37:20 +01:00
d569242124
Add Static branch prediction in decode stage
2017-03-19 23:27:35 +01:00
88dee6d2bc
Reduce area with reg[0] optimisation
2017-03-18 19:32:54 +01:00
fc1bb7249a
Add trace option to regresion
2017-03-18 14:06:42 +01:00
5e9da0f27a
Add self checked dhrystone test
2017-03-18 12:32:14 +01:00
31db6511dc
Fix performance of removed instruction which halt were halting the pipeline
2017-03-18 10:51:55 +01:00
20ca348707
Fix dCmd sent while the execute stage is removed
...
Pass dhrystone benchmark without error !
2017-03-17 21:26:42 +01:00
7517ac797d
Add MUL/DIV/REM support with plugins (pass Riscv-Tests)
2017-03-17 11:45:01 +01:00
52a524be06
Add light shifter plugin
2017-03-16 15:11:06 +01:00
401be6ca83
Reorganize project
2017-03-16 13:14:25 +01:00
bf5bebda08
PcManager now drive PC asyncronously (use 1 cycle less in jump)
...
Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
2017-03-15 21:10:44 +01:00
83232e9860
Faster pipeline arbitration logic (200 Mhz on cyclone IV c6)
...
Branch plugin with jump in execute or memory stages (parameter)
2017-03-15 20:02:56 +01:00
c6610ea454
Fix halt arbitrations
2017-03-15 17:14:58 +01:00
11797fbb6e
Add sim performance print
2017-03-14 23:25:04 +01:00
70d910e7d7
Load/Store pass Riscv-Tests
2017-03-14 23:00:24 +01:00
7065ed5d93
All base instruction pass Riscv-Test (load/store not tested)
2017-03-14 20:13:35 +01:00
ad6964f0bb
Classify tests
...
Riscv-test integration wip
2017-03-14 00:42:48 +01:00
df99a0d963
Better decoding
2017-03-13 18:30:37 +01:00
e36c90af03
Add decoder bench
2017-03-13 16:17:57 +01:00
9fc82c9736
Pass verilator simple literal, add, jump
2017-03-12 20:12:40 +01:00
ec4837a744
wip
2017-03-12 12:39:33 +01:00
cb1b73bc2b
Add branch
2017-03-11 19:07:08 +01:00
23abdb7f95
Add hazard tracking plugin
2017-03-11 16:45:04 +01:00
e58f28bc27
Add store/load
2017-03-11 15:35:56 +01:00
fcb70a333f
WIP
2017-03-11 00:34:49 +01:00
fc7e9a7730
wip
2017-03-09 01:07:55 +01:00
130ed6345c
boot
2017-03-08 22:17:48 +01:00
Dolu1990
Ubuntu
Dolu1990